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Messages from 28850

Article: 28850
Subject: Re: Advice on FPGA board.
From: "Bill Blyth" <bb@alphadata.co.uk>
Date: Fri, 26 Jan 2001 09:45:42 -0000
Links: << >>  << T >>  << A >>
Have you tried www.alphadata.co.uk ?

The ADM-XRC is a PCI card with PLX ( for DMA etc ) and Virtex up to 2000E
with Virtex II boards out soon.

Bill

"Pratip Mukherjee" <pratipm@hotmail.com> wrote in message
news:ah6c6.14773$t3.3374499@typhoon.ne.mediaone.net...
> A near fit would be http://technology.celoxica.com/boards/boards_001.asp
>
> In article <94qcnq$d46$1@nnrp1.deja.com>, jimmy75@my-deja.com wrote:
> >
> >> None of our boards will fit this particular application.  A board
> >> with a PCI bus interace is needed for the high-speed transfers
> >> between the FPGA board memory and the PC running the desktop
> >> publishing app.  All our boards interface through the
> >> parallel port which is too slow for this type of application.
> >
> >Yep. We need a PCI board for our purpose preferably with a DMA
> >controller and a Xilinx Virtex chip(s) and lots of memory. If only we
> >could make one on our own!
> >I had a look on the web and didn't find all these features altogether
> >in one board. We were hoping that somebody out there could help us.
> >
> >-- Jim
> >
> >
> >Sent via Deja.com
> >http://www.deja.com/



Article: 28851
Subject: Re: UK parts
From: Jon Schneider <jms@geriatrix.circlesquared.cXoXm>
Date: 26 Jan 2001 09:52:52 +0000
Links: << >>  << T >>  << A >>
After contacting several bits of Insight both here and in Europe,
Cedar and Amtel I have received one set of prices for one-offs from
Insight UK.

The 10k gate Spartan in an 84 pin PLCC (XCS010somethingorotherPC84)
was in the £5-10 range which is ok. They didn't say anything about
programming cables. Anybody found them over here ?

The SpartanII is a bit cheaper but of course not so easy for
prototyping.

I haven't got to ordering but could in theory open a company account.

        Jon

Article: 28852
Subject: Re: Foundation FPGA Editor hard macros in VHDL
From: kolja@prowokulta.org
Date: Fri, 26 Jan 2001 10:08:36 GMT
Links: << >>  << T >>  << A >>


The FPGA editor documentation is OK, and I get along with the editor
very well, but the documentation that I found only explains how to
use the FPGAEditor macros in FPGAEditor design.

In the old days you coudl just instanciate .NMC macros in XNF files.
XNF is not supported any longer, but I guess something like this is
still possible.

However, I could not find documentation on
- In which directory should the NMC file be placed to be used in a
VHDL    design?
- Do I need to use any special library or can I just instanciate them?
- Can I make my NMC macro show up in the library manager to create a
  symbol for it?

I need to control the routing of a very small part of my design, and the
FPGA Editor seems easier to use then JBits which would obviously solve
the problem.

Any help is appriciated.

Kolja

  mrandelzhofer@my-deja.com wrote:
> our team has done lots of successful xc3000/xc4003 designs just at the
> chip level.
> - all the device specific stuff can be used, or used easier as in any
> hdl.
> - you get the highest speed and area optimization out of the logic
> - they are only useful for the fpga family they are designed for, and
> only for one special size of fpga
> - good for ip-property protection
> - only used by the hardliners, a hardmacro can take lots of time and
> know how
> - its the only way to access the special virtex trdy/irdy logic ?
> an appnote about all these fpga pip, net, block, etc hackings would be
> great !
>
> In article <94jqd7$ilp$1@nnrp1.deja.com>,
>   sulimma@my-deja.com wrote:
> > Does anybody know, where I can find documentation about
> > using hard macros created with the FPGA editor of Xilinx
> > foundation software
> >
> > a) In a schematic
> > b) In a VHDL design


Sent via Deja.com
http://www.deja.com/

Article: 28853
Subject: Re: UK parts
From: kolja@prowokulta.org
Date: Fri, 26 Jan 2001 10:14:13 GMT
Links: << >>  << T >>  << A >>

> > Maybe I'll look towards Europe for a supplier.
> >
> >         Jon
>
> Jon,
>
> Keep us up to date with your 'ordering from Europe' exploits
> won't you?
>
> How will you pay for small quantities, credit card?
>
> Nial.

Most distributors will not ship overseas, in either direction.
I am living in germany, an I am glad to know people in the UK
and in the US that serve as "proxies" for part orders.

Paypal and thelike make it easy to get the money to the US.
To get money to the UK I use another proxy: A friend from the UK
who has still an acount there. I give him cash an he transfers the
money.

All in all it is very inconvinient to buy small quantities overseas,
but it works. Especially as phone calls to the US are now down to 4
cents a minute.

Kolja


Sent via Deja.com
http://www.deja.com/

Article: 28854
Subject: Re: Field Programmable Gate Array selection and task suitability
From: Cemal Coemert <coemert@fokus.gmd.de>
Date: Fri, 26 Jan 2001 11:27:25 +0100
Links: << >>  << T >>  << A >>
"J.H.R. Schrader" wrote:
> 
> Hi,
> 
> For my university master's, I am currently designing a controller for an
> 
> all-optical ATM switch. The first thing we want to accomplish is the
> replacement of the ATM header by using a table look-up. The line speed
> would be 155 Mbit/s. Can this task be accomplished by using a FPGA? Does
> 
> anybody have some general information about these devices, because I
> only have the information from the Altera web-site. I don't know much
> about these devices and their functionality.
> 
> Thanks,
> 
> Jan-Rutger Schrader
> University of Twente
> the Netherlands

Hi, 

take a look at 
http://www.fokus.gmd.de/research/cc/tip/projects/tanya/tanya_new_over.html

This Network Interface Card utilizes an Xilinx FPGA for Processing ATM
Cells.


Cemal Cömert

Article: 28855
Subject: Re: can not start coregen
From: "JianyongNiu" <cop00jn@sheffield.ac.uk>
Date: Fri, 26 Jan 2001 11:11:47 -0000
Links: << >>  << T >>  << A >>
right. following the instructions on the xilinx website, three steps must be
taken in the right order: (1) install the Virtex II Device Update CD, (2)
then Service Pack 6, (3) then apply the Speed Files and BitGen patch...

My question is: where can I get the Virtex II Device Update CD?

thanx.

"Rune Baeverrud" <fpga@no.spam.iname.com> wrote in message
news:980420700.206607@news2.cybercity.dk...
> > I got a problem that I can not start up the core generater either from
> > windows tastbar or desktop. it does not work in DOS shell as well.
anybody
> > knows the reason?
>
> Sounds like a familiar problem. If it is what I think it is - there's a
fix
> for it here:
>
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=
> 1&getPagePath=10434
>
> ...or download and install Service Pack 6.
>
> Rune Baeverrud
>
>



Article: 28856
Subject: Re: how to reduce number of gates in xor reducing in crc computing?
From: kolja@prowokulta.org
Date: Fri, 26 Jan 2001 12:56:54 GMT
Links: << >>  << T >>  << A >>
I assume that each of your channels evaluates a 64bit polynomial to
produce a 16 bit output. This requires a 64 by 16 matrix multiply.
If you want programmable polynomials you have a 128 Bit input function
for each out, which nees at least 32 + 8 + 2 + 1 = 43 LUTs, or a total
of more than 600 LUTs per channel. In this case you can not share logic
as the other posting suggests.

If you have a fixed code, you have 64 inputs less, and you only need to
implement the matrix fields that contain a '1'. There are codes that
have <= N/2 set bits, which will reduce the number of inputs to 32 per
output. You only need 8 + 2 + 1 = 11 LUTs per channel in this case, and
you usually can share logic. You might get along with less than 100 LUTs
per channel.

Therefore you shoudl check if you can restrict the circuit to fixed
polynomials.
You could write a JBits generator that produces a circuit for any
required polynomial.

CU,
	Kolja



In article <20010125112159.3493.qmail@web514.mail.yahoo.com>,
>  I have written a synthesizable VHDL code for a
> programmable crc engine which accepts generator
> polynomials with degree up to 64 in two separate 16
> bit wide channels which can be added to each other to
> build one 32 bit wide channel.


Sent via Deja.com
http://www.deja.com/

Article: 28857
Subject: mutiplier !!
From: "Seb C" <Seb@stien.bizland.com>
Date: Fri, 26 Jan 2001 14:09:50 GMT
Links: << >>  << T >>  << A >>
Hi,

someone can give me an example of a 2's complement multiplier with parallel
loading in schematic for FPGA ??
Thx a lot

SEB

--

****************************
Seb@stien.bizland.com
****************************



Article: 28858
Subject: Re: really fast counter in SpartanXL?
From: Ray Andraka <ray@andraka.com>
Date: Fri, 26 Jan 2001 15:01:26 GMT
Links: << >>  << T >>  << A >>
No need to use a ripple counter for this.  A 24 bit synchronous counter will do
the trick.  In most of the current crop of FPGAs you can get a 24 bit counter
running at 100 MHz (any virtex or spartanII, faster speed grades of 4K, Altera
10K).   If you happen to be using an older FPGA, then split the counter into 2
12 bit counters, register the carry out of the first to use as an enable to the
second.  Just about anything with a carry chain produced since 1995 or so will
do a 12 bit count at 100 MHz.

Scott Taylor wrote:
> 
> Does anyone have an example of a ripple counter in VHDL? I need to divide a 100MHz clock down to under 10Hz (non-critical). I only need the final output. No intermediate stages will be used for any purpose.
> 
> Thanks.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com
Article: 28859
Subject: Re: CORDIC ALGORITHM
From: frouatbi@my-deja.com
Date: Fri, 26 Jan 2001 15:09:32 GMT
Links: << >>  << T >>  << A >>
In article <94r6e9$214$1@nnrp1.deja.com>,
  saqib_03@hotmail.com wrote:
>  Hi!
> The CORDIC algorithm seems to implement a lot of functions just by
> iterative add-shift procedure but at the same time there are some
> points that remain unclear...specially in the Linear and Hyperbolic
> modes...can anybody help me to get more Theoritical details on these
> CORDIC algorithm modes?
>
> Thanx
> --
> --saqib yaqub--
>
> Sent via Deja.com
> http://www.deja.com/
>

I worked with a cordic algorithm you can find information on this site:
http://www.dspguru.com/info/faqs/cordic.htm

Fredj Rouatbi


Sent via Deja.com
http://www.deja.com/

Article: 28860
Subject: Re: looping and ranges
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Fri, 26 Jan 2001 10:18:08 -0500
Links: << >>  << T >>  << A >>
Paul Campbell wrote:
> 
> Rick Collins wrote:
> 
> > So I wanted to change it to a loop, like this.
> >
> > integer j;
> >
> > always @(bar)
> >   for (j=1; j<14; j=j+1)
> >     foo[j] <= bar[423-((13-j)*8):423-((13-j)*8)-7];
> >
> > The ModelSim simulator compiler complains that the range of bar has to
> > be a constant. A coworker tells me that the real problem is that verilog
> > won't let you use a loop variable in a range while it will let you use
> > the loop variable for a single array element.
> >
> > So I wanted to try a different approach where I use the loop variable to
> > assign the bits one at a time, but I could not figure out how to refer
> > to the individual bits of foo[j]. foo[j][k] did not work.
> 
> OK - there are two problems here (both solved in Verilog 2000 by the way).
> 
> 1) you can't index a range of a vector, just a bit (basicly because the
> size of the result has to be fixed at compile time for the compiler)
> 
> 2) you can't both index an array of vectors and a bit from it at the same
> time
> 
> Anyway while you're waiting for v2k what you can do is variable bit indexes
> and then concat them together:
> 
>         integer j;
>         always @(bar)
>                 for (j = 1; j < 14; k=j+1)
>                         foo[j] <= {bar[423-((13-j)*8)],
>                                    bar[423-((13-j)*8)-1],
>                                    bar[423-((13-j)*8)-2],
>                                    bar[423-((13-j)*8)-3],
>                                    bar[423-((13-j)*8)-4],
>                                    bar[423-((13-j)*8)-5],
>                                    bar[423-((13-j)*8)-6],
>                                    bar[423-((13-j)*8)-7]};
> 
> not as pretty as you might like but it will get the job done
> 
>         Paul Campbell
>         paul@verifarm.com

As you say, it is not pretty, but I think it is the best way. Thanks a
lot!  :)

What will the construct look like in V2K to access bits from an array of
vectors? 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX
URL http://www.arius.com

Article: 28861
Subject: Re: Advice on FPGA board.
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Fri, 26 Jan 2001 15:46:08 GMT
Links: << >>  << T >>  << A >>

Dear Jim,

I offered to help and asked some questions.

I got no response.

Then I see you post again asking if anyone can help ?

Please reply to my first post.


1st post -------------------------------------------1st post
Hi Jim,

I design frame grabbers/ image processing boards using Xilinx FPGAs.

What university are you at ? What is the name of the course ?

my FPGA boards are at http://www.pixelsmart.com

If I can help please let me know.

What need is there for filtering a DTP bitmap ??

Sincerely
Daniel DeConinck
High Res Technologies, Inc.





Article: 28862
Subject: 6845
From: net9147@yahoo.com
Date: Fri, 26 Jan 2001 17:21:18 +0100
Links: << >>  << T >>  << A >>
Vanted 6845 CGA crt controler in VHDL or etc...


Article: 28863
Subject: RAM reset question - Xilinx Virtex
From: "Jamie Sanderson" <jamie@nortelnetworks.com>
Date: Fri, 26 Jan 2001 11:39:30 -0500
Links: << >>  << T >>  << A >>
Hello experts;

I have a question about block and distributed RAM in the Virtex. When using
coregen, you can specify initial values for the memory. If not specified,
for example when RAM is inferred in synthesis, the initial values are 0. My
question is, under what conditions are those values loaded?

- After configuration? Yes, I'm pretty sure of this.
- After a global reset using the startup block? I think so, but I'm not
sure.
- After a non-global reset? Probably not, but again I don't know.

Since Virtex came out, Xilinx has been recommending against use of the
global reset logic. I'm wondering now if that doesn't affect initialisation
of memory components. If I do require my memories to be re-initialised,
could I simply hook up my reset line to a manually instantiated startup
block, without changing any of my other logic? Or is it an all or nothing
decision?

Your input is appreciated!

Regards,
Jamie



Article: 28864
Subject: Re: 6845
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Fri, 26 Jan 2001 16:57:06 GMT
Links: << >>  << T >>  << A >>
I do something similar but in schematics.

It is used in these products: http://www.pixelsmart.com

What type of application do you have ?


Sincerely
Daniel DeConinck
High Res Technologies, Inc.





Article: 28865
Subject: Re: RAM reset question - Xilinx Virtex
From: Philip Freidin <philip@fliptronics.com>
Date: Fri, 26 Jan 2001 09:00:44 -0800
Links: << >>  << T >>  << A >>
On Fri, 26 Jan 2001 11:39:30 -0500, "Jamie Sanderson" <jamie@nortelnetworks.com>
wrote:
>Hello experts;
>
>I have a question about block and distributed RAM in the Virtex. When using
>coregen, you can specify initial values for the memory. If not specified,
>for example when RAM is inferred in synthesis, the initial values are 0. My
>question is, under what conditions are those values loaded?
>
>- After configuration? Yes, I'm pretty sure of this.

Yes, it is part of the configuration bitstream

>- After a global reset using the startup block? I think so, but I'm not
>sure.

No. initial state is no longer available. Will retain contents of RAM
prior to reset.

>- After a non-global reset? Probably not, but again I don't know.

No. Same reason and result.

>
>Since Virtex came out, Xilinx has been recommending against use of the
>global reset logic. I'm wondering now if that doesn't affect initialisation
>of memory components. If I do require my memories to be re-initialised,
>could I simply hook up my reset line to a manually instantiated startup
>block, without changing any of my other logic? Or is it an all or nothing
>decision?
>
>Your input is appreciated!
>
>Regards,
>Jamie
>

Philip Freidin
Fliptronics

Article: 28866
Subject: Re: really fast counter in SpartanXL?
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Fri, 26 Jan 2001 09:13:21 -0800
Links: << >>  << T >>  << A >>
Ray, he needs 24 bits, but your comment is well taken. I just wanted to help him with the ripple counter, which takes less power.

Peter
=====================
Ray Andraka wrote:

> No need to use a ripple counter for this.  A 24 bit synchronous counter will do
> the trick.  In most of the current crop of FPGAs you can get a 24 bit counter
> running at 100 MHz (any virtex or spartanII, faster speed grades of 4K, Altera
> 10K).   If you happen to be using an older FPGA, then split the counter into 2
> 12 bit counters, register the carry out of the first to use as an enable to the
> second.  Just about anything with a carry chain produced since 1995 or so will
> do a 12 bit count at 100 MHz.
>
> Scott Taylor wrote:
> >
> > Does anyone have an example of a ripple counter in VHDL? I need to divide a 100MHz clock down to under 10Hz (non-critical). I only need the final output. No intermediate stages will be used for any purpose.
> >
> > Thanks.
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com

Article: 28867
Subject: Re: Advice on FPGA board.
From: "Chuck Woodring" <woodringCT@nuwc.npt.navy.mil>
Date: Fri, 26 Jan 2001 12:32:30 -0500
Links: << >>  << T >>  << A >>
try http://www.signal-isp.com  they have a dspchip, a virtex chip and a
microcontroller all on a pci board.



Article: 28868
Subject: Re: Advice on FPGA board.
From: Ray Andraka <ray@andraka.com>
Date: Fri, 26 Jan 2001 17:47:49 GMT
Links: << >>  << T >>  << A >>
You didn't bother to ask how much that 10 million gate part costs, did you?  You
get considerably less multipliers with the smaller parts, down to only 4 with
the
2v40 (vs 192 in the big part).
Another note, I don't believe any 5v I/O standards are supported by the Virtex2. 
That would seem to preclude its use for 5v PCI (I hope I am wrong on this).


-ackNnak- wrote:
> 
> I just attended the Xilinx "Xtreme DSP" seminar introducing the
> Virtex-II architecture and applications for DSP.  With the new
> integral 18x18 multiplier blocks in the logic fabric they claim the
> largest part (~10M gates) could perform 600 billion (8x8)MAC's/sec.
> It also incorporates what they call "SelectIO" which appears to
> support just about any IO type under the sun.  Couple that with the
> digitally controlled out impedance blocks and your board with a single
> FPGA.  You could probably piece together a good bit of it from the
> free "LogiCore" IP.   No, I don't work for Xilinx.
> 
> -Noel
> 
> On Thu, 25 Jan 2001 23:27:00 GMT, jimmy75@my-deja.com wrote:
> 
> >
> >> None of our boards will fit this particular application.  A board
> >> with a PCI bus interace is needed for the high-speed transfers
> >> between the FPGA board memory and the PC running the desktop
> >> publishing app.  All our boards interface through the
> >> parallel port which is too slow for this type of application.
> >
> >Yep. We need a PCI board for our purpose preferably with a DMA
> >controller and a Xilinx Virtex chip(s) and lots of memory. If only we
> >could make one on our own!
> >I had a look on the web and didn't find all these features altogether
> >in one board. We were hoping that somebody out there could help us.
> >
> >-- Jim
> >
> >
> >Sent via Deja.com
> >http://www.deja.com/

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 28869
Subject: Re: mutiplier !!
From: Ray Andraka <ray@andraka.com>
Date: Fri, 26 Jan 2001 17:49:07 GMT
Links: << >>  << T >>  << A >>
See my website.  It describes various multipliers for FPGAs.

Seb C wrote:
> 
> Hi,
> 
> someone can give me an example of a 2's complement multiplier with parallel
> loading in schematic for FPGA ??
> Thx a lot
> 
> SEB
> 
> --
> 
> ****************************
> Seb@stien.bizland.com
> ****************************

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 28870
Subject: Re: CORDIC ALGORITHM
From: Ray Andraka <ray@andraka.com>
Date: Fri, 26 Jan 2001 17:51:21 GMT
Links: << >>  << T >>  << A >>
You might also download a copy of my cordic paper from my website.  I've been
told that it is one of the most understandable explanations of the cordic
algorithm.  The paper is "A surevey of CORDIC algorithms for FPGA based
processors".



-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 28871
Subject: Re: Synthesizing Virtex Block Memories with Leonardo v1999.1i = Slooow
From: Newsbrowser@Newsbrowser.com (Newsbrowser)
Date: Fri, 26 Jan 2001 18:34:47 GMT
Links: << >>  << T >>  << A >>
On Fri, 26 Jan 2001 06:53:04 GMT, Phil Hays <spampostmaster@home.com>
wrote:

>Newsbrowser wrote:
>
>> Anybody know how to speed things up.
>
>Get a trial licence for Synplify.
>
>www.synplicity.com
>
>
>-- 
>Phil Hays

Unfortunately, those of us in big company's really don't go willy
nilly with using whatever tool we want. 


Ralph Watson 
Return Email Address is: 
ralphwat dot home at excite dot com 
just type the address in like it should look like

Article: 28872
Subject: Re: looping and ranges
From: Stephen Williams <steve@icarus.com>
Date: 26 Jan 2001 18:47:06 GMT
Links: << >>  << T >>  << A >>
always @(bar)
  for (j=1; j<14; j=j+1)
    foo[j] <= bar[423-((13-j)*8):423-((13-j)*8)-7];

Nope.

Part selects (that is, ranges of bits) must have constant indices in
Verilog. Verilog 200? relaxes this constraint. An in addition, you
cannot address single bits of vector arrays. Verilog 200? relaxes this
restriction as well.

However, for what you want to do, you can probably make more use of
parameter expressions to make the unrolled version more manageable.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve@icarus.com              But I have promises to keep,
steve@picturel.com            and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

Article: 28873
Subject: what is the best FPGA development toolkit?
From: "JianYong Niu" <cop00jn@shef.ac.uk>
Date: Fri, 26 Jan 2001 19:03:04 -0000
Links: << >>  << T >>  << A >>
Any suggestionis on Language, and tools for
synthesis/simulation/verification/place and rout etc?




Article: 28874
Subject: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip multiprocessor!
From: "Jan Gray" <jsgray@acm.org>
Date: Fri, 26 Jan 2001 19:24:22 GMT
Links: << >>  << T >>  << A >>
Yesterday's XtremeDSP Simulcast was excellent. Well, what do you know -- the
promised "...delicious plate ... of goodies ... " was not just hyperbole.
Here are some impressions and speculations.

1. We FMAP'ing/RLOC'ing dinosaurs shouldn't feel so bad. We may soon be
joined by the Verilog/VHDL dinosaurs.

2. There are a ton of compelling applications of 100K logic cells and 100s
of multipliers. Time to crack open a signal processing textbook.

3. With the new buffered programmable interconnect, that graph of number of
net loads, to ns delay, was pretty darn flat...

4. There were a couple of hints that there might be another tier of on-chip
RAM coming -- perhaps suitable for storing an entire frame. Great -- but
multiported, or at least multibanked would be nice -- and please, don't
count such a RAM as a zillion system gates. :-)

5. XCITE is awesome. I looked around our downlink site and 'most every
attendee was grinning and/or nodding (though not quite high-fiving). In some
circumstances you can even use the XCITE controlled impedance technology to
parallel terminate inputs from other unterminated drivers.

6. Erich Goetting, Xilinx VP, revealed the forthcoming Virtex-II with
PowerPC and multiple 3.125 Gbps links will be called Virtex-II Pro.

7. The Virtex-II Pro's Conexant-licensed 3.125 Gbps links (nice eye
diagrams) are driven at 32-bits at 78 MHz. That looks easy enough to
interface to.

8. I loved the hypothetical (?) die layout diagram of a Virtex-II Pro part
with *four* embedded PowerPC cores. Coooool. Here I was thinking that soft
cores might be relevant as chip-multiprocessors
[http://www.fpgacpu.org/usenet/soft.html] -- but perhaps not if the world
embraces hard core chip-multiprocessors embedded in the programmable logic
fabric.

Very nice work, Xilinxers!

With a multi-hundred-million-transistor budget to play with, it will be
quite fascinating to see what Virtex-II 'immerses' next. I can think of
several interesting hard cores.

Jan Gray, Gray Research LLC
FPGA CPU News: www.fpgacpu.org






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