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Messages from 28575

Article: 28575
Subject: Re: Looking for prototyping board
From: "Manfred Kraus" <newsreply@cesys.com>
Date: Wed, 17 Jan 2001 16:15:30 +0100
Links: << >>  << T >>  << A >>
I designed a PCI-based prototype board
for SPARTAN-II devices.
The datasheet can be downloaded from
www.cesys.com as soon as it is available.
I promise this will be in about 3 days  :-))
The boad is a low-cost board (about $199)
This means there is no RAM on the board,
only the PCI interface chip, the SPARTAN-II,
the clock generator and connectors.

-
Manfred




Article: 28576
Subject: Re: Xilinx UCF/ngdbuild problem
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Wed, 17 Jan 2001 15:41:19 +0000
Links: << >>  << T >>  << A >>
On Tue, 16 Jan 2001 16:02:47 +0100, Nicolas Matringe
<nicolas.matringe@IPricot.com> wrote:

>Utku Ozcan wrote:
>
>> Are the lines separated by newline characters? Maybe
>> Ngdbuild UCF parser might not handle newline characters.
>> Can it be the case?
>
>There is only one line with all the FFs names. I even tried to replace
>the separating spaces with dots
>(FFS(copier_cout(41):copier_cout(42):...) but it gave the same error.
>
>I'm puzzled that a Xilinx tool generates things that are not recognized
>by other Xilinx tools...

Line too long? 

The symptom is obviously a missing ) so the remainder of the entire file
is part of the TIMEGRP. 

Utku's answer is a way of splitting the line, but there may be others.

- Brian

Article: 28577
Subject: Re: Virtex-II officially launched
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 17 Jan 2001 08:04:22 -0800
Links: << >>  << T >>  << A >>
Bob,

The impedance updates are asynchronous, and are done in such a manner that
the updates trim values are all extremely small.  The resultant dR/dt is
undetectable in the signal integrity of the output.

They must have really done a bad job in the ASIC's if it affected the SI.
Too bad that when they do an ASIC they have no time to get it right.

Austin

Bob Perlman wrote:

> On Mon, 15 Jan 2001 10:14:39 -0800, Peter Alfke
> <peter.alfke@xilinx.com> wrote:
>
> >Highest on my list of exciting features is the Digitally Controlled
> >Impedance, which effectively puts the series termination resistor
> >right into the output driver, or the parallel termination right into
> >the input buffer ( all optionally of course). It will be a gods-end
> >for people putting >500-pin packages on a pc-board, not having to
> >bother with resistor packs...
>
> This will be extremely useful.
>
> One question, Peter: some ASIC vendors have been offering this feature
> for a while, but some implementations are problematic.  Is the Virtex
> II impedance update mechanism asynchronous to the user's clock?  If
> so, is there a guarantee that the impedance can't glitch (say, the way
> a D/A might) at a critical moment?
>
> Thanks,
> Bob Perlman


Article: 28578
Subject: Re: Virtex-II officially launched
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 17 Jan 2001 08:09:37 -0800
Links: << >>  << T >>  << A >>
Gary,

The battery backed up key RAM for the DES keys holds six 56 bit numbers.

If you were to use the BBRAM in the non-secure mode (ie not using the DES
encryption feature), then these locations are kept and can be written and read
through the JTAG port (only) for test purposes (or for any other purpose).

When you set the unit for DES operation, then these keys may be written to, but
not read back out.  Any attempt to fiddle with it (ie changing back to
non-secure mode) wipes out the keys, and cleans out the part's configuration.

The BBRAM supply is less than 100 pA (room temp), so a 350 mA lithium coin cell
would last 15 years.

Austin

Gary Watson wrote:

> In a volume production environment, is there any way to load a unique serial
> number into a Virtex-II?  (Assuming that this is a SOC application where
> there is no external microprocessor...)
>
> --
>
> Gary Watson
> gary2@nexsan.com  (you should leave off the digit two for email)
> Nexsan Technologies Ltd.
> Derby DE21 7BF  ENGLAND
> UK-based Engineers: See our job postings at
> http://www.nexsan.com/pages/careers.htm
>
> "Rune Baeverrud" <fpga@no.spam.iname.com> wrote in message
> news:979567585.218715@news2.cybercity.dk...
> > Hello,
> >
> > Xilinx Virtex-II has now been officially announced.
> >
> > Check out the press release:
> > http://www.xilinx.com/prs_rls/vtx2ship.htm
> >
> > and the Virtex-II Handbook:
> > http://www.xilinx.com/products/virtex/handbook/index.htm
> >
> > Some highlights are:
> > - digitally controlled impedances for input and output pins
> > - new resources for clock management and clock synthesis
> > - digital spread spectrum clocking
> > - encrypted bitstreams
> > - dedicated multipliers
> >
> > Go and see for yourself!
> >
> > Regards,
> > Rune Baeverrud
> >
> >
> >


Article: 28579
Subject: Re: Virtex counter speed
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 17 Jan 2001 08:35:40 -0800
Links: << >>  << T >>  << A >>
This is a hot-button of mine.
Three years ago I put a frequency counter into an XC4002XL, and it runs at 420

MHz, close to 500 MHz when the 3.6 V batteries are fully charged.  :-)
I have written some stories about that in XCell, our quartely magazine.

That's why I am now shooting for 1 GHz with the newest Virtex-II
(clock-Q is max 0.41 ns and set-up time through a LUT is 0.68 ns.
So I cannot quite do 1 GHz worst case. But almost, and there will be faster
speed grades coming...)

In any newer Virtex or Spartan-II I can easily guarantee >300 MHz resolution
for a ripple counter.
And a ripple counter ( actually a ripple cascade of 2-bit Johnson counters)
always gives you the highest frequency resolution. Not synchronous, so you
have to be careful what you do with the counter outputs...

In Virtex-II you will be able to run a full-fledged 24-bit synchronous counter

at just about 300 MHz .  And 64 bits at almost 200 MHz , without any tricks
whatsoever.
Just pushbutton design.

Peter Alfke, Xilinx Applications




Article: 28580
Subject: Re: CMOS or TTL
From: steve (Steve Rencontre)
Date: Wed, 17 Jan 2001 16:46 +0000 (GMT Standard Time)
Links: << >>  << T >>  << A >>
In article <9443qv$njm$1@nnrp1.deja.com>, erika_uk@my-deja.com () wrote:

> hello,
> 
> which provides better performance CMOS or TTL based devices?
> I believe that CMOS gives better performance, and it's the CMOS based
> devices which are more expensive...but my friend told me the inverse ?
> 
> but what let the better to be better ?
> are all fpga based CMOS devise ?

Real, genuine TTL is a bit of a museum piece these days. Most of what is 
casually called "TTL" is actually CMOS designed to run with voltages that 
match the original bipolar TTL values.

This is an oversimplification, but to a first approximation, CMOS is 
faster, smaller, more efficient and cheaper than TTL, which is why it's 
more-or-less taken over completely.

--
Steve Rencontre		http://www.rsn-tech.co.uk
//#include <disclaimer.h>


Article: 28581
Subject: Re: Virtex-II officially launched
From: Newsbrowser@Newsbrowser.com (Newsbrowser)
Date: Wed, 17 Jan 2001 17:09:10 GMT
Links: << >>  << T >>  << A >>
On Mon, 15 Jan 2001 16:30:14 GMT, Ray Andraka <ray@andraka.com> wrote:

>
>
>erika_uk@my-deja.com wrote:
>> 
>> Hi,
>> 
>> Does the tool handle it well ?
>
>Like any other new architecture, I suspect it will take a while
>for the tools to catch up to the new silicon.  In the past,
>it has taken about a year after the introduction of the 
>silicon before the tools were close to ready for prime time.
>Macro libraries lag even further behind.  In the case of Virtex,
>I didn't start recommending them for customers until a little
>over a year ago...because of tools issues.
>
>
I just have to chime my 0.02 cents in here 

Irregardless of what the Xilinx folks say. My Experience parallels
Ray's. It will be a year or so before I can be convinced to put this
part in a new design. 

I learned long ago never be first out of the gate to use these new
parts unless you really really really have to. Then you have to make
sure you justified the added expense and frustration you will receive.




>> 
>> --Erika
>> In article <979567585.218715@news2.cybercity.dk>,
>>   "Rune Baeverrud" <fpga@no.spam.iname.com> wrote:
>> > Hello,
>> >
>> > Xilinx Virtex-II has now been officially announced.
>> >
>> > Check out the press release:
>> > http://www.xilinx.com/prs_rls/vtx2ship.htm
>> >
>> > and the Virtex-II Handbook:
>> > http://www.xilinx.com/products/virtex/handbook/index.htm
>> >
>> > Some highlights are:
>> > - digitally controlled impedances for input and output pins
>> > - new resources for clock management and clock synthesis
>> > - digital spread spectrum clocking
>> > - encrypted bitstreams
>> > - dedicated multipliers
>> >
>> > Go and see for yourself!
>> >
>> > Regards,
>> > Rune Baeverrud
>> >
>> >
>> 
>> Sent via Deja.com
>> http://www.deja.com/
>
>-- 
>-Ray Andraka, P.E.
>President, the Andraka Consulting Group, Inc.
>401/884-7930     Fax 401/884-7950
>email ray@andraka.com  
>http://www.andraka.com  or http://www.fpga-guru.com

Ralph Watson 
Return Email Address is: 
ralphwat dot home at excite dot com 
just type the address in like it should look like

Article: 28582
Subject: Re: Virtex-II officially launched
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 17 Jan 2001 09:59:55 -0800
Links: << >>  << T >>  << A >>

Newsbrowser wrote:

> Irregardless of what the Xilinx folks say. My Experience parallels
> Ray's. It will be a year or so before I can be convinced to put this
> part in a new design.
>
> I learned long ago never be first out of the gate to use these new
> parts unless you really really really have to. Then you have to make
> sure you justified the added expense and frustration you will receive.

Well, it is up to us at Xilinx to pack so many goodies into the new
family ( and to provide good software and libraries, of course) that you
will overcome you conservative hesitation and give the new parts a try.

Size, speed, big RAMs, controlled I/O impedance, fast multipliers, clock
management, bitstream encryption, etc.

We hope that we can entice you to look forwards, not only backwards.
Progress is only made by the brave...

Peter Alfke, Xilinx Applications

>
>


Article: 28583
Subject: Re: CMOS or TTL
From: plogic1@my-deja.com
Date: Wed, 17 Jan 2001 18:02:26 GMT
Links: << >>  << T >>  << A >>
Its all depend on what you are trying to do.Industry prefers CMOS
due to its size of the devices and the relative low power. But on the
other hand the devices may be a bit expensive.

Reg

plogic1

In article <9443qv$njm$1@nnrp1.deja.com>,
  erika_uk@my-deja.com wrote:
> hello,
>
> which provides better performance CMOS or TTL based devices?
> I believe that CMOS gives better performance, and it's the CMOS based
> devices which are more expensive...but my friend told me the inverse ?
>
> but what let the better to be better ?
> are all fpga based CMOS devise ?
>
> any input  ?
>
> --Erika
>
> Sent via Deja.com
> http://www.deja.com/
>


Sent via Deja.com
http://www.deja.com/

Article: 28584
Subject: Re: Virtex-II officially launched
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Wed, 17 Jan 2001 11:02:35 -0700
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
> 
> Erika,
> 
> The new features are very well supported.  We have been pushing designs
> by the thousands through the tools since last year to (hopefully) remove
> as many bugs as humanly possible.  I think our software team has done a
> superb job supporting all of the new features.
> 
> And how would I know?  I manage the FPGA Lab team, who's task it is to
> test every single feature (characterization and verification).
> Additionally our product test team also uses our own software (as well
> as everyone else here).

So how come Xilinx never made it a priority to let us use the tri-state
registers in the IOBs of the 4KX/L/A and SpartanXL parts without the
silly perl-script workaround?  Instead, this feature was relegated to
the "do not fix" pile.

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

"It is better to be silent and thought a fool, 
 than to send an e-mail to the entire company
 and remove all doubt."

Article: 28585
Subject: Re: Synplify Pro6.13
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Wed, 17 Jan 2001 11:04:42 -0700
Links: << >>  << T >>  << A >>
Arnd Sluiter wrote:
> 
> On Sun, 14 Jan 2001 17:34:42 -0800, chsw
> <chen.songwei@mail.zte.com.cn> wrote:
> 
> hello,
> 
> if you use synplify a bus in your top entity like
> data : out std_logic_vector ( 7 downto 0);
>  is generateted in the edif netlist as
> data(7) .... data(0). With fpga express the
> bus ist described as data<7> ... data<0>. Therefore
> this difference is important for your constraint
> file for the xilinx tool.
> 
> example xilinx.ucf:
> 
> with synplify:
> NET data(7) LOC =P10;
> ...
> NET data(0) LOC =P17;
> 
> with fpga express
> NET data<7> LOC = P10;
> ...
> NET data<0> LOC = P17;
> 
> thats one difference i found out !

You can put a global attribute in Synplify's .SDC file which will write
out the edif file in your desired format.

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

"It is better to be silent and thought a fool, 
 than to send an e-mail to the entire company
 and remove all doubt."

Article: 28586
Subject: Re: Computer Wizard!
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Wed, 17 Jan 2001 11:05:13 -0700
Links: << >>  << T >>  << A >>
Crystal Coons wrote:
> 
> Got questions about your computer and need answers right away? Don't
> know
> what your system is compatible with?
> Need help?
> The Computer Wizard is here to help you!
> 
> The Computer Wizard is a free service provided by Dynamic Computer
> Systems.
> Ask any computer-related question that you need help with, and receive a
> response within 24-48 hours.
> 
> Guaranteed! Go to http://www.dcsinter.net and give it a try! This is a
> FREE
> service here to help you!

Hi!  I can't connect my computer to the internet. How do I use your
service?

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

"It is better to be silent and thought a fool, 
 than to send an e-mail to the entire company
 and remove all doubt."

Article: 28587
Subject: Re: I wanna Model Sim cracked
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Wed, 17 Jan 2001 11:14:08 -0700
Links: << >>  << T >>  << A >>
Christoph Hauzeneder wrote:
> 
> This is a bit stupid. Because each license file of Model Sim can be used
> only for one year. You can get a free license to evaluate Package Power
> from Mentor Graphics (this program includes Model Sim) for 30 days.

Actually, that's not true.  The key won't let you run any version of the
software dated after the key expires.  So, if the older software works
for you, you can cancel the support and keep working.  I'm not sure what
effect that has on Mentor's revenue stream.

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

"It is better to be silent and thought a fool, 
 than to send an e-mail to the entire company
 and remove all doubt."

Article: 28588
Subject: Re: grey code counters
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Wed, 17 Jan 2001 11:17:19 -0700
Links: << >>  << T >>  << A >>
Bill Lenihan wrote:
> 
> This sounds convenient, but the problem remains .... if a normal binary up
> counter looks like this:
> 
> always @(posedge clk) count <= count +1;
> 
> and we want the synthesis tool to turn this into a grey code counter for us:
> 
> always @(posedge clk) count <= count +1 /* synthesis counter = grey */ ;
> 
> .... then there's going to be a big discrepency between RTL & gate-level
> simulation results, if our simulator checks the counter!

I see your point.  Might be a problem for sign-off.

Yeah, but what if your _simulator_ looked at the attribute and "did the
right thing"?

That's probably too much to ask.

> >
> > What I'd like to see (and I think I suggested this to the Synplicity
> > guys) is an attribute or something in the synthesis tool that lets you
> > select gray-code or binary-code counters.
> >
> > That would be useful.

-- 
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

"It is better to be silent and thought a fool, 
 than to send an e-mail to the entire company
 and remove all doubt."

Article: 28589
Subject: Re: Spartan programming error
From: plogic1@my-deja.com
Date: Wed, 17 Jan 2001 18:25:42 GMT
Links: << >>  << T >>  << A >>
Done pin got a weak internal pull-up so this will go HI if the programe
is succesful. Also you can check the INIT pin to see if there a Frame
error. For more information check the folloing Xilinx Page :

http://service.xilinx.com/support/cgi-bin/webcgi.exe/,/?Session=42496,U=
1,ST=23,N=0000,K=10831,SXI=1,Decision_Tree=obj(80)




In article <942i65$glr$1@nnrp1.deja.com>,
  Leon Heller <leon_heller@hotmail.com> wrote:
> In article <93v2rr$f97$1@nnrp1.deja.com>,
>   bjorn_lindegren@my-deja.com wrote:
> > Hi
> >
> > I use a Spartan device, and some thing is wrong when programming it.
> >
> > I know that I can check on an out pin for a check sum.
> > This check sum tells me when the fpga is right programed.
> >
> > But whitch pin do I have to check on?
>
> I use an LED on the DONE pin.
>
> Leon
> --
> Leon Heller, G1HSM
> Tel: (Mobile) 079 9098 1221 (Work) +44 1327 357824
> Email: leon_heller@hotmail.com
> Web: http://www.geocities.com/SiliconValley/Code/1835
>
> Sent via Deja.com
> http://www.deja.com/
>


Sent via Deja.com
http://www.deja.com/

Article: 28590
Subject: Re: Alliance for Linux
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Wed, 17 Jan 2001 11:26:38 -0700
Links: << >>  << T >>  << A >>
Jamie Lokier wrote:

> "You've already got two computers".  (The
> computer cost more than the software that runs on it after all).

Um, I'm typing this on a Gateway POS PIII/550.  The machine next to it's
a PIII/750.  Both have 21" monitors.

All that's STILL cheaper than a single copy of Hyperlynx' BoardSim. 
(Which is NT-only and has a dongle.)
Cheaper than Synplify Non-Pro, too. (Ditto, as followers of the Big Fat
Idiot would say.)
And ModelSim, too.
And PCAD 2000 (our PCB layout tool), too.

The 550 will be a Linux box Real Soon Now, but not for EDA tools.

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

"It is better to be silent and thought a fool, 
 than to send an e-mail to the entire company
 and remove all doubt."

Article: 28591
Subject: Re: CRC - from long division to XOR, how?
From: Phil Short <pjs@nospam.switchingpost.com>
Date: Wed, 17 Jan 2001 18:29:12 GMT
Links: << >>  << T >>  << A >>
eml@riverside-machines.com.NOSPAM wrote:
> 
> On Mon, 15 Jan 2001 15:31:29 -0500, "Jamie Sanderson"
> <jamie@nortelnetworks.com> wrote:
> 
> >I will continue searching for the elusive app note... Sounds like just the
> >thing I need.
> >
> >Regards,
> >Jamie
> 
> Found it - 'Implementing parallel CRC for reliable high-speed
> point-to-point communication using TAXI', AMD pub.#12572. There's not
> much more than you already know. It doesn't seem to be on the website,
> so I've scanned the relevant 3 pages to:
> 
> www.riverside-machines.com/pub/AMD_12572.zip
> 
> Have fun -
> 
> Evan

Good article, thanks for scanning it in.

--

Phil

Article: 28592
Subject: Re: CMOS or TTL
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 17 Jan 2001 10:56:25 -0800
Links: << >>  << T >>  << A >>
This discussion looks like a time warp.
TTL was created in the 'sixties and, through Low-power Schottky variations,
served us into the 'eighties. But that's almost 20 years in the past...
All modern development is, and has been, in CMOS, with some GaAs and
belated ECL thrown in for extra high speed.
I spent the first half of my professional life designing with TTL, but that
is now just a faint memory...

Peter Alfke


plogic1@my-deja.com wrote:

> Its all depend on what you are trying to do.Industry prefers CMOS
> due to its size of the devices and the relative low power. But on the
> other hand the devices may be a bit expensive.
>
> Reg
>
> plogic1
>
> In article <9443qv$njm$1@nnrp1.deja.com>,
>   erika_uk@my-deja.com wrote:
> > hello,
> >
> > which provides better performance CMOS or TTL based devices?
> > I believe that CMOS gives better performance, and it's the CMOS based
> > devices which are more expensive...but my friend told me the inverse ?
> >
> > but what let the better to be better ?
> > are all fpga based CMOS devise ?
> >
> > any input  ?
> >
> > --Erika
> >
> > Sent via Deja.com
> > http://www.deja.com/
> >
>
> Sent via Deja.com
> http://www.deja.com/


Article: 28593
Subject: Re: FPGA driving clock line
From: Dean Armstrong <daa1@cs.waikato.ac.nz>
Date: Thu, 18 Jan 2001 08:13:21 +1300
Links: << >>  << T >>  << A >>
Hi,

Thanks for all the help guys. I think having a clock enable seems to be the
best bet, so I'll try that.

Regards,
Dean Armstrong

Dean Armstrong wrote:

> Hi All,
>
> Is it possible to drive a clock line for a Spartan II device and three
> Xilinx XC9500XL CPLD devices from a user IO pin on another Spartan II.
> The application is one where I want logic within the main Spartan to
> select between two different input clocks. To be used for itself and the
> other devices.
>
> Thanks
> Dean Armstrong


Article: 28594
Subject: About programming cables
From: "Juan M. Rivas" <jmrivas@media.mit.edu>
Date: Wed, 17 Jan 2001 14:27:29 -0500
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------E7E1A04CC3A0F98E290F3FB3
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

I'm looking for a Progrmming Cables from Xilinx, for a stand alone FPGA
proyect:  Does anyone know wher I can by one, and which one is good?

I've been looking for the Multilinx, and the Xcheqer,  but I can't
decide...Besides I can't find where to find them (Always out of stock)

Suggestions???

Thanks all
--------------E7E1A04CC3A0F98E290F3FB3
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n:Rivas;Juan M.
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--------------E7E1A04CC3A0F98E290F3FB3--


Article: 28595
Subject: Re: Virtex-II officially launched
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 17 Jan 2001 13:32:21 -0800
Links: << >>  << T >>  << A >>
Gary,

Oh well.

I have been corrected (again!  twice in one day).

The BBRAM is cleared if you go from secure to non-secure mode.

The unit powers on to the secure mode.

To read the BBRAM you have to be in non-secure mode.

This was to prevent back door sneak attacks.

Oh, and the battery is disconnected once you are running so you can not see what
the keys are from the power drain signature on the Vbatt pin.

Sorry about the serial number,

Austin

Gary Watson wrote:

> In a volume production environment, is there any way to load a unique serial
> number into a Virtex-II?  (Assuming that this is a SOC application where
> there is no external microprocessor...)
>
> --
>
> Gary Watson
> gary2@nexsan.com  (you should leave off the digit two for email)
> Nexsan Technologies Ltd.
> Derby DE21 7BF  ENGLAND
> UK-based Engineers: See our job postings at
> http://www.nexsan.com/pages/careers.htm
>
> "Rune Baeverrud" <fpga@no.spam.iname.com> wrote in message
> news:979567585.218715@news2.cybercity.dk...
> > Hello,
> >
> > Xilinx Virtex-II has now been officially announced.
> >
> > Check out the press release:
> > http://www.xilinx.com/prs_rls/vtx2ship.htm
> >
> > and the Virtex-II Handbook:
> > http://www.xilinx.com/products/virtex/handbook/index.htm
> >
> > Some highlights are:
> > - digitally controlled impedances for input and output pins
> > - new resources for clock management and clock synthesis
> > - digital spread spectrum clocking
> > - encrypted bitstreams
> > - dedicated multipliers
> >
> > Go and see for yourself!
> >
> > Regards,
> > Rune Baeverrud
> >
> >
> >


Article: 28596
Subject: back-annotation is not possible
From: karenwlead@my-deja.com
Date: Wed, 17 Jan 2001 22:58:23 GMT
Links: << >>  << T >>  << A >>
hey,

can someone expalin me what such warning means !!!!

WARNING:Anno:197 - NGDAnno found 2 physical component(s) for which 100
percent  back-annotation is not possible. Simulation models for these
components will  be constructed from the NCD. Rerun NGDAnno with the -
report option for   additional details, including any net and instance
names which are lost in   this process.

regards


Sent via Deja.com
http://www.deja.com/

Article: 28597
Subject: spartanII chip availability
From: "Chuck Woodring" <woodringfam@earthlink.net>
Date: Thu, 18 Jan 2001 00:11:27 GMT
Links: << >>  << T >>  << A >>
Hi,
    I am looking at building a small number 10-20 pcbs that will use one of
Xilinx's FPGAs.  The logic required is small but may be expanded later.
Essentially it is a FPDP i/f feeding some fifos that are feeding a D/A.

    I am looking initially at a Spartan II for a fifo or DPRAM to hold some
data for the D/A.
I like the idea of using the block ram for the small DPRAM or fifo. Speed is
slow by most people's standards on this group. D/A will be run at 120KSa/s
or so but I am doing
8 channels + on each FPGA.


    The gist of my question is for a small number of chips, am I going to
have trouble
obtaining the chip I want.  Luckily the design should be generic across a
few variants of the same family, so I can design the logic, use a proto
board to check it out and then
order the chips I need to build the boards.

I have checked with Insight Electronics and they seem to have a fair number
of chips in
stock but many are larger than I need.  I may end up using an older Xilinx
XC4000 or something (no block ram) and Insight seems to have plenty of them.
Anyone having issues obtaining small number of parts?






Article: 28598
Subject: Re: spartanII chip availability
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 17 Jan 2001 16:43:09 -0800
Links: << >>  << T >>  << A >>
Chuck, you did not mention the total FIFO size ( how important is BlockRAM) and
the number of I/O.

Peter Alfke, Xilinx

Chuck Woodring wrote:

> Hi,
>     I am looking at building a small number 10-20 pcbs that will use one of
> Xilinx's FPGAs.  The logic required is small but may be expanded later.
> Essentially it is a FPDP i/f feeding some fifos that are feeding a D/A.
>
>     I am looking initially at a Spartan II for a fifo or DPRAM to hold some
> data for the D/A.
> I like the idea of using the block ram for the small DPRAM or fifo. Speed is
> slow by most people's standards on this group. D/A will be run at 120KSa/s
> or so but I am doing
> 8 channels + on each FPGA.
>
>     The gist of my question is for a small number of chips, am I going to
> have trouble
> obtaining the chip I want.  Luckily the design should be generic across a
> few variants of the same family, so I can design the logic, use a proto
> board to check it out and then
> order the chips I need to build the boards.
>
> I have checked with Insight Electronics and they seem to have a fair number
> of chips in
> stock but many are larger than I need.  I may end up using an older Xilinx
> XC4000 or something (no block ram) and Insight seems to have plenty of them.
> Anyone having issues obtaining small number of parts?


Article: 28599
Subject: Re: About programming cables
From: John Grider <jgrider@umr.edu>
Date: Wed, 17 Jan 2001 19:30:34 -0600
Links: << >>  << T >>  << A >>
"Juan M. Rivas" wrote:
> 
> I'm looking for a Progrmming Cables from Xilinx, for a stand alone FPGA
> proyect:  Does anyone know wher I can by one, and which one is good?
> 
> I've been looking for the Multilinx, and the Xcheqer,  but I can't
> decide...Besides I can't find where to find them (Always out of stock)
> 
> Suggestions???
> 
> Thanks all

You could always build your own parallel/jtag cable - the schematics are
availible from xilinx's web site.  It looks simple, just two 74xxx's and
a couple diodes, caps, etc.
-- John
___________________________________________________________
N recursive algorithms on the wall,
N recursive algorithms,
You take one down, pass it around.
N-1 recursive algorithms on the wall.
-----------------------------------------------------------
John Grider  REMOVEjgrider@umr.edu	(573) 308 - xxxx
Electrical Engineering			1301 N. Oak St. #9
University of Missouri - Rolla  	Rolla, MO 65401
-----------------------------------------------------------



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