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Messages from 28800

Article: 28800
Subject: Re: Xilinx will NEVER support Linux
From: cybin <cybin@home.com>
Date: Wed, 24 Jan 2001 19:01:42 GMT
Links: << >>  << T >>  << A >>
The second and most interesting, to me, issue is, "just what OS does
Xilinx expect the average guy to want to run on his new Power PC Vertex
II whizbangit?"

PSOS, Wind River, uCOS, all great operating systems to be sure, but I
don't think so.

So, for all you lurkers out there. What OS will you want to run on your
new 
Vertex Whizbangit?

cybin

Article: 28801
Subject: Re: Virtex counter speed
From: Ray Andraka <ray@andraka.com>
Date: Wed, 24 Jan 2001 19:41:42 GMT
Links: << >>  << T >>  << A >>
In virtexe-6, it is 1.0ns for the flip-flop, 3.2ns for the SRL16.  This is
mitigated somewhat if oyu make sure your SRL16 is output through a flip-flop in
the same slice, as you avoid the routing delays then.  Also, logic in front of
the flip flop tends to equalize that difference.  If you went for a straight max
toggle rate though, the flip-flp has about a 3:1 advantage.

Falk Brunner wrote:
> 
> Ray Andraka schrieb:
> >
> > You haven't compared the clock-to-Qs of the flip-flops and SRL16's have you?
> 
> Ahhh, No. Whats the differnce?? (Iam to lasy to look at the data sheet
> ;-))
> 
> --
> MFG
> Falk

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 28802
Subject: Re: Encryption is supported in new Virtex II but.....
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 24 Jan 2001 13:25:06 -0800
Links: << >>  << T >>  << A >>
"Dan" <daniel.deconinck@sympatico.ca> writes:
> The Virtex II encryption requires a battery to always be on.
> 
> Xilinx says the current is <100nA and the battery will last as long as the
> battery's shelf life.
> 
> They do not discuss battery technologies of choice. I only know how to
> change the batteries on my baby's toys.
> 
> What would a good battery technology be ? What would the shelf life be ?

What you want is a small lithium coin cell.  These are available either
socketable or with solder terminals.  Even a very small one like
a BR1216 (12.5 mm diamater x 1.6 mm height) should work fine for ten
years, if you are careful about the design and manufacture of your
board.  If there are contaminants on the PCB after manufacture, there can
be resistive paths that drain the battery.  They may seem like high
resistance, but at 3 volts even as high a resistance as a megohm with
result in 3 uA drain, which is thirty times more than the 100 nA drain
from the Virtex II.

Also note that PCB handling during transport and storage becomes much
more problematic if there is a battery installed.  This is a good reason
to use a battery holder rather than soldering the battery in.  On the
down side, the battery holder is not good if the system is subject to
much vibration.

There are also rechargeable lithium batteries.

Digikey carries a good selection of Panasonic lithium batteries.

Article: 28803
Subject: Re: Encryption is supported in new Virtex II but.....
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Wed, 24 Jan 2001 13:46:32 -0800
Links: << >>  << T >>  << A >>
Most of us have a quarz watch on our wrist.
Such a watch consumes about 10 microamps, to run the crystal, the divider,
plus the solenoid driving the second hand around.
Its tiny battery lasts more than a year, at least 10,000 hours. I think we
all agree.

The internal back-up memory in Virtex-II consumes 100 ( really 1000 ) times
less current, and consumes this current only when Vcc is not present.
So from a charge capacity point of view, the little battery would easily last
a few hundred years.

But: There is a self-discharge mechanism that is the real limitation.
Good 3-V Lithium batteries have a shelf life of 15 years or more.
I have one in my $19.- Casio watch, and it has lasted 8 years already. Still
going strong.

We did not publish a specific battery type because that would make this
non-problem look like a problem...

Peter Alfke, Xilinx Applications


Dan wrote:

> The Virtex II encryption requires a battery to always be on.
>
> Xilinx says the current is <100nA and the battery will last as long as the
> battery's shelf life.
>
> They do not discuss battery technologies of choice. I only know how to
> change the batteries on my baby's toys.
>
> What would a good battery technology be ? What would the shelf life be ?
>
> What is your opinion of this battery method ?
>
> I have opened a case with Xilinx. Their support could not find more
> information at this time.
>
> Sincerely
> Daniel DeConinck
> High Res Technologies, Inc.


Article: 28804
Subject: Re: Virtex counter speed
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 24 Jan 2001 23:01:10 +0100
Links: << >>  << T >>  << A >>
Ray Andraka schrieb:
> 
> In virtexe-6, it is 1.0ns for the flip-flop, 3.2ns for the SRL16.  This is
> mitigated somewhat if oyu make sure your SRL16 is output through a flip-flop in
> the same slice, as you avoid the routing delays then.  Also, logic in front of
> the flip flop tends to equalize that difference.  If you went for a straight max
> toggle rate though, the flip-flp has about a 3:1 advantage.

But how comes this??? At the end, the SRL16 is just 16 FF, should be the
same FFs as the individual FFs??
OK, there is the multiplexer after the FF output, but this should not be
THAT difference, because delay through a LUT is 0.7 ns (Spartan2-5).
Hmmm.

BTW I had a look at your website, very interesting stuff.

-- 
MFG
Falk

Article: 28805
Subject: Re: Virtex counter speed
From: Ray Andraka <ray@andraka.com>
Date: Wed, 24 Jan 2001 22:29:07 GMT
Links: << >>  << T >>  << A >>


Falk Brunner wrote:
> 
> Ray Andraka schrieb:
> >
> > In virtexe-6, it is 1.0ns for the flip-flop, 3.2ns for the SRL16.  This is
> > mitigated somewhat if oyu make sure your SRL16 is output through a flip-flop in
> > the same slice, as you avoid the routing delays then.  Also, logic in front of
> > the flip flop tends to equalize that difference.  If you went for a straight max
> > toggle rate though, the flip-flp has about a 3:1 advantage.
> 
> But how comes this??? At the end, the SRL16 is just 16 FF, should be the
> same FFs as the individual FFs??

Well, not entirely.  The SRL 16 is constructed from the LUT resources, where the
flip-flops are dedicated flip-flops.  I'm not intimately familiar with the
transistor level design of the CLB.  I'm guessing the storage elements for the
SRL16/CLB_RAM/LUT are latches with a timed write pulse rather than flip-flops
where the flip flop element really is a flip-flop.  This would be consistent
with the history of the CLB RAM which started out as an async RAM with difficult
to use timing characteristics.  A write pulse generator was added to the logic
in later families.  In any event, the clock to Q for the SRL16 is long, but
there is no routing delay for connecting to the flip-flop in the same slice. 
The long clock to Q is shorter than the propagation delay between flip-flops for
most designs, so it usually isn't an issue provided you follow the SRL16 with a
flip-flop in the same CLB.

> OK, there is the multiplexer after the FF output, but this should not be
> THAT difference, because delay through a LUT is 0.7 ns (Spartan2-5).
> Hmmm.
> 
> BTW I had a look at your website, very interesting stuff.
> 
> --
> MFG
> Falk

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 28806
Subject: can not start coregen
From: "JianyongNiu" <cop00jn@sheffield.ac.uk>
Date: Wed, 24 Jan 2001 22:50:24 -0000
Links: << >>  << T >>  << A >>
I got a problem that I can not start up the core generater either from
windows tastbar or desktop. it does not work in DOS shell as well. anybody
knows the reason?

thanx in advance

J.

-------
cop00jn@shef.ac.uk



Article: 28807
Subject: Re: can not start coregen
From: "JianyongNiu" <cop00jn@sheffield.ac.uk>
Date: Wed, 24 Jan 2001 23:03:35 -0000
Links: << >>  << T >>  << A >>
The log indicates that the system can not find the path specified. although
I tried to execute the coregen.bat from its right directory, it failed due
to the same reasure as well.


"JianyongNiu" <cop00jn@sheffield.ac.uk> wrote in message
news:94nm7h$7be$1@bignews.shef.ac.uk...
> I got a problem that I can not start up the core generater either from
> windows tastbar or desktop. it does not work in DOS shell as well. anybody
> knows the reason?
>
> thanx in advance
>
> J.
>
> -------
> cop00jn@shef.ac.uk
>
>



Article: 28808
Subject: Re: Xilinx will NEVER support Linux
From: Simon Gornall <simon@unique-id.com>
Date: Wed, 24 Jan 2001 23:07:21 +0000
Links: << >>  << T >>  << A >>
cybin wrote:
> 
> The second and most interesting, to me, issue is, "just what OS does
> Xilinx expect the average guy to want to run on his new Power PC Vertex
> II whizbangit?"
> 
> PSOS, Wind River, uCOS, all great operating systems to be sure, but I
> don't think so.
> 
> So, for all you lurkers out there. What OS will you want to run on your
> new
> Vertex Whizbangit?

For me, as an FPGA wannabe, running linux is what makes the grade. 
I have seven AVR pcbs in each of our delivered systems which could 
be easily subsumed into a single spartan-II FPGA. It won't happen
until I can run the xilinx place-and-route tools under Linux. We
use that OS exclusively. The entire company does. I accept
we're not typical, but I think we're predictive. Time will tell.

I mean come on! How hard can it be to port the java-based web
tools to any other java platform? Is it a days work ? Maybe 2.

I own my company. I understand the support/maintenance argument.
I think Xilinx underestimate the "we'll do that" attitude of 
most linux users - if the 'difficult' part (ie: the place-and-route
bit that probably shouldn't be released to the public - trade 
secrets and all that) were still kept private, only the most rabid
linux advocates would still complain. Guys(Gals) we're just like
everyone else. We only want to use Xilinx stuff. You are 
stopping us. What do you expect us to do ? Frankly we'll
carry on doing without xilinx...

Well, just my $0.02 worth. I doubt it'll change the world, but I'm
not looking for a new England. All I want is to make the point
that there's a huge untapped (by Xilinx) market out there. 
Strange, really.

Simon
-- 
Physicists get hadrons!

Article: 28809
Subject: Spartan-II serial vs. parallel configuration
From: John Grider <jgrider@umr.edu>
Date: Wed, 24 Jan 2001 18:46:15 -0600
Links: << >>  << T >>  << A >>
Hello all!
	Can anyone shed some light on how the spartan2 configuration data is
formatted?  With the spartan the data was just 8 bits padded with ones
for a 32bit word; on the Spartan/XL, it's a true 32bits.  I'd like to
use an external flash and configure in parallel, but it would help to
know how to feed it the data.  A few e-mails and calls yielded a Xilinx
parrot saying "everything is in the data sheets" but I've read the data
sheets, and it IS NOT there.  Anybody here know?
-- John
___________________________________________________________
N recursive algorithms on the wall,
N recursive algorithms,
You take one down, pass it around.
N-1 recursive algorithms on the wall.
-----------------------------------------------------------
John Grider  REMOVEjgrider@nohormelproductsumr.edu
Electrical Engineering			1301 N. Oak St. #9
University of Missouri - Rolla  	Rolla, MO 65401
-----------------------------------------------------------

Article: 28810
Subject: Re: Encryption is supported in new Virtex II but.....
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Thu, 25 Jan 2001 01:54:20 GMT
Links: << >>  << T >>  << A >>
Dear Eric,

Great 'reply post'.  Thanks.

Why is it that PCB handling during transport and storage becomes much
more problematic for soldered versus socketed batteries ?


Sincerely
Daniel DeConinck
High Res Technologies, Inc.





Article: 28811
Subject: Re: Encryption is supported in new Virtex II but.....
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 24 Jan 2001 19:13:12 -0800
Links: << >>  << T >>  << A >>
Dan,

New topic for FPGA's: how long will the bunny keep banging that drum?

Seriously, there are primary cells (non-rechargable) and secondary cells
(rechargable) batteries.  (I love that technical battery talk).

First you need to decide which type you want to use.

Temperature ranges are important, most batteries hate getting any hotter than
50C, and most don't like getting below 0C either.

Also, some batteries use hazardous waste chemicals, and they represent
hazardous waste problems on disposal.

The standard lithium coin cell last 15 years on self discharge.  There is an
extended temperature range version available that is recommended for both
commercial and industrial temperature ranges. It is environmentally friendly.

The Vbat pin requires from 1.0 Vdc to 4.0 Vdc.  We did this so you could use
any battery technology now known.  Lithium, Nickel metal Hydride, Lead
calcium, lead acid, silver mercury, you name it, it will work with a single
cell.

If you use any type of rechargable battery, please use the IC that goes with
it to control its charging.  Battery manufacturers can help with suggesting
the proper charging circuits.

As Peter stated, the current is only required while the power to the FPGA is
off, so the intent is to allow for shipment of the product to the field, and
sitting on a shelf, before being turned on.

The lithium coin cells seem like the best compromise as it is unlikely they
will pay all that money for the new Virtex II chip -- and then not use it :)

Supercaps are nice, but they also have a self discharge curve, so I have not
recommended their use.  (It is silly to have someone ship it back if they
waited too long).

Even a primary alkaline battery (AA cell) will last three of four years if it
isn't abused over its temperature range.

The Panasonic battery website is excellent
 http://www.panasonic.com/industrial_oem/battery/battery_home.htm
as well as
http://data.energizer.com/batteryinfo/buttons/primary_batteries.htm
 http://www.sony-media.com/en/energy/products/primary.html
 http://www.rayovac.com/products/index.shtml

and many more,

Enjoy

Austin


Dan wrote:

> The Virtex II encryption requires a battery to always be on.
>
> Xilinx says the current is <100nA and the battery will last as long as the
> battery's shelf life.
>
> They do not discuss battery technologies of choice. I only know how to
> change the batteries on my baby's toys.
>
> What would a good battery technology be ? What would the shelf life be ?
>
> What is your opinion of this battery method ?
>
> I have opened a case with Xilinx. Their support could not find more
> information at this time.
>
> Sincerely
> Daniel DeConinck
> High Res Technologies, Inc.


Article: 28812
Subject: Re: Encryption is supported in new Virtex II but.....
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 24 Jan 2001 19:43:29 -0800
Links: << >>  << T >>  << A >>
"Dan" <daniel.deconinck@sympatico.ca> writes:
> Why is it that PCB handling during transport and storage becomes much
> more problematic for soldered versus socketed batteries ?

I should have been more clear on that.  The intent was that you defer
installing the battery until the board is assembled into the system.
If you install it sooner, you still have handling problems.

Article: 28813
Subject: Re: Encryption is supported in new Virtex II but.....
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Wed, 24 Jan 2001 22:04:25 -0700
Links: << >>  << T >>  << A >>
Falk Brunner wrote:
> 
> Why not using wrist watch technology like solar cells / automatic drive
> to charge a rechargable battery or a super cap when the power is off . .
> . ;-)))

I Can see it now -- in case of emergency break glass -- 2 D size batteries --
:)

-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
"Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk

Article: 28814
Subject: XC7272 vers XC9272.
From: "RDR" <rdruesne@prosyst.fr>
Date: Thu, 25 Jan 2001 11:08:09 +0100
Links: << >>  << T >>  << A >>
Bonjour,

        Y a t il  une demarche particuliere pour porter un design de xc7272
vers xc9272 ?
        Y a t il des pin a double utilisation (exple : jtag)?
        Y a t il un "convertisseur", une "passerelle" pour convertir les
fichiers de l'un vers l'autre?

Merci de répondre en priorite dans notre boite :
rdruesne@prosyst.fr




Article: 28815
Subject: Re: can not start coregen
From: "Rune Baeverrud" <fpga@no.spam.iname.com>
Date: Thu, 25 Jan 2001 13:05:20 +0100
Links: << >>  << T >>  << A >>
> I got a problem that I can not start up the core generater either from
> windows tastbar or desktop. it does not work in DOS shell as well. anybody
> knows the reason?

Sounds like a familiar problem. If it is what I think it is - there's a fix
for it here:
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=
1&getPagePath=10434

...or download and install Service Pack 6.

Rune Baeverrud



Article: 28816
Subject: how to reduce number of gates in xor reducing in crc computing?
From: imansz@yahoo.com (Iman SedehZadeh)
Date: 25 Jan 2001 14:08:44 +0100
Links: << >>  << T >>  << A >>
Does any body know how to reduce number of clbs
required to implement an XOR reduce tree especially
for XC4010E?
 I have written a synthesizable VHDL code for a
programmable crc engine which accepts generator
polynomials with degree up to 64 in two separate 16
bit wide channels which can be added to each other to
build one 32 bit wide channel. Now I want to implement
that on a XS40-010 board with a XC4010E fpga on it.
Leonardo synthesis tool reports clb usage of about
700% for that FPGA. I tried direct instantiation of
xor5 but it didn’t improve the usage.  Also I changed
xor computations with lookup to a table but didn’t
have any improvement. 
This is as part of my MS-thesis and I appreciate any
comments about that.


__________________________________________________
Do You Yahoo!?
Yahoo! Auctions - Buy the things you want at great prices. 
http://auctions.yahoo.com/

-- 
Posted from web514.mail.yahoo.com [216.115.104.229] 
via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 28817
Subject: Field Programmable Gate Array selection and task suitability
From: "J.H.R. Schrader" <jrs@dds.nl>
Date: Thu, 25 Jan 2001 14:17:46 +0100
Links: << >>  << T >>  << A >>
Hi,

For my university master's, I am currently designing a controller for an

all-optical ATM switch. The first thing we want to accomplish is the
replacement of the ATM header by using a table look-up. The line speed
would be 155 Mbit/s. Can this task be accomplished by using a FPGA? Does

anybody have some general information about these devices, because I
only have the information from the Altera web-site. I don't know much
about these devices and their functionality.

Thanks,

Jan-Rutger Schrader
University of Twente
the Netherlands


Article: 28818
Subject: Re: Encryption is supported in new Virtex II but.....
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Thu, 25 Jan 2001 13:59:51 GMT
Links: << >>  << T >>  << A >>
Austin,

Thanks for the helpful insight.


Sincerely
Daniel DeConinck
High Res Technologies, Inc.





Article: 28819
Subject: How does a flip chip differ from a BGA ?
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Thu, 25 Jan 2001 14:47:01 GMT
Links: << >>  << T >>  << A >>
How does a flip chip differ from a BGA ?


Sincerely
Daniel DeConinck
High Res Technologies, Inc.





Article: 28820
Subject: Re: Spartan-II serial vs. parallel configuration
From: Theron Hicks <hicksthe@egr.msu.edu>
Date: Thu, 25 Jan 2001 09:55:09 -0500
Links: << >>  << T >>  << A >>


John Grider wrote:

> Hello all!
>         Can anyone shed some light on how the spartan2 configuration data is
> formatted?  With the spartan the data was just 8 bits padded with ones
> for a 32bit word; on the Spartan/XL, it's a true 32bits.  I'd like to
> use an external flash and configure in parallel, but it would help to
> know how to feed it the data.  A few e-mails and calls yielded a Xilinx
> parrot

Xilinx Parrot... I like that!  I have dealt with parrot's from other
manufacturers also.  I really would like to get a parrot hunting license some
days.



> saying "everything is in the data sheets" but I've read the data
> sheets, and it IS NOT there.  Anybody here know?
> -- John
> ___________________________________________________________
> N recursive algorithms on the wall,
> N recursive algorithms,
> You take one down, pass it around.
> N-1 recursive algorithms on the wall.
> -----------------------------------------------------------
> John Grider  REMOVEjgrider@nohormelproductsumr.edu
> Electrical Engineering                  1301 N. Oak St. #9
> University of Missouri - Rolla          Rolla, MO 65401
> -----------------------------------------------------------


Article: 28821
Subject: Re: How does a flip chip differ from a BGA ?
From: Jonas Thor <thor@NOSPAMsm.luth.se>
Date: Thu, 25 Jan 2001 16:30:38 +0100
Links: << >>  << T >>  << A >>

You can't really compare flip chip with BGA. 

Flip chip is a method to mount a die. The die is mounted on a
substrate with the die pads facing the substrate. This requires less
space compared to wire bonding.

BGA is package type. Ball Grid Array. The die inside a BGA package may
be mounted as a flip chip.

/ Jonas Thor 

On Thu, 25 Jan 2001 14:47:01 GMT, "Dan"
<daniel.deconinck@sympatico.ca> wrote:

>How does a flip chip differ from a BGA ?
>
>
>Sincerely
>Daniel DeConinck
>High Res Technologies, Inc.
>
>
>


Article: 28822
Subject: Re: UK parts
From: Nial Stewart <nials@sqf.hp.com>
Date: Thu, 25 Jan 2001 15:31:35 +0000
Links: << >>  << T >>  << A >>
Jon Schneider wrote:
> 
> I've just got through to a Xilinx rep on my sixth phone call to him. I
> thought he was going to be really helpful, given that he had bothered
> to send two copies of an email with his phone number. Instead he just
> mentioned Insight and Avnet which he could have put in his email. Twat* !
> 
> Maybe I'll look towards Europe for a supplier.
> 
>         Jon


Jon,

Keep us up to date with your 'ordering from Europe' exploits
won't you?

How will you pay for small quantities, credit card?

Nial.

Article: 28823
Subject: Re: Can Virtex-II be programmed with MultiLINX?
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Thu, 25 Jan 2001 08:40:09 -0800
Links: << >>  << T >>  << A >>
Juan,

Yes.  That is what we use in the lab.  The config bank Vcco is set to 3.3
Vdc (per the spec sheet).

Austin

"Juan M. Rivas" wrote:

> Hi all!
>
> Is the Virtex-II (1.5 volt core) cappable of being programmed with the
> xilinx MultiLINX cable (2.5 - 5 Volt spec)?
>
> Thank you all for your answers
>
> attn. Juan


Article: 28824
Subject: Re: Encryption is supported in new Virtex II but.....
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Thu, 25 Jan 2001 08:45:43 -0800
Links: << >>  << T >>  << A >>
Dan,

They fall out of their sockets.  They are heavy.

Never let an electronic engineer design the mechanics.

Austin

Dan wrote:

> Dear Eric,
>
> Great 'reply post'.  Thanks.
>
> Why is it that PCB handling during transport and storage becomes much
> more problematic for soldered versus socketed batteries ?
>
> Sincerely
> Daniel DeConinck
> High Res Technologies, Inc.




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1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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