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Messages from 30150

Article: 30150
Subject: Re: No inputs on XC9536XL
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 26 Mar 2001 11:10:18 +0200
Links: << >>  << T >>  << A >>
Kolja Sulimma <kolja@bnl.gov> writes:

> What kind of an error message is this:
> 
> Fitting Status: Did NOT Fit
> ****************************  Errors and Warnings
> *************************
> ERROR:nd202 - Design 'confcpld' has no inputs.

http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=8003

Is the above link relevant?

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se

Article: 30151
Subject: What's new in Synplify 6.20 than 6.13
From: lyqin@cti.com.cn
Date: 26 Mar 2001 09:32:51 GMT
Links: << >>  << T >>  << A >>

Anyone knows?


 Leon Qin



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Article: 30152
Subject: Re: Senior I/O Designer - Canada
From: John Chambers <JohnC@ihr.mrc.ac.uk>
Date: Mon, 26 Mar 2001 12:21:12 +0100
Links: << >>  << T >>  << A >>

 
> The local Super-Valu had an outdoor sign up for many months:
> "visit our Aggressive Meat Department". I don't know
> what cracked me up most - the images that came to mind
> of rude, pushy butchers harassing customers or the
> aggressive meat itself assaulting them. Or maybe I was
> just amazed that an induhvidual could come up with
> such a dumb slogan.
> 
> regards, tom


Maybe they just had a special for Tiger steaks? (Buy two get a free
Python)

When I first saw "PCB Real Estate" instead of "PCB space" I could not
believe what I was seeing.

"Things should be described as simply as possible - but no simpler" -
Albert Einstein

Article: 30153
Subject: hybrid design entry
From: "catherina" <floreq10@hotmail.com>
Date: Mon, 26 Mar 2001 13:02:12 +0100
Links: << >>  << T >>  << A >>
Hi all,

Does F3.1 accepts  hybrid design top level entry ?

I want to instantiate in my top level entry, some modules based on :
1- schematic
2- Edif
3- Structural Vhdl
5- logicore
any help (or reference) on how to proceed?
if someone want to use behavioural VHDL, with the above based modules, how
should she/he perform?

<(.)~(.)>
CATHY




Article: 30154
Subject: Asynchronus Mashine States
From: "Marcin Michalak" <M.Michalak@aldec.zgora.pl>
Date: Mon, 26 Mar 2001 16:48:00 +0200
Links: << >>  << T >>  << A >>
Hi!!

    Anybody know something about modeling Asynchronus Machine States in
FPGA?
I need some information about that. If anyone knows pages about that or have
some
information please write to me.

regards

Marcin Michalak



Article: 30155
Subject: Re: Senior I/O Designer - Canada
From: Andy Peters <"apeters <"@> noao [.] edu>
Date: Mon, 26 Mar 2001 09:55:45 -0700
Links: << >>  << T >>  << A >>
Or Red Red Meat, who were also from Chicago...

"Lee I." wrote:
> 
> Also as opposed to "Dead Meat" or "Red Meat" from Cali.
> 
> -Lee - Former Jersey Punk myself.
> 
> "Andy Peters noao [.] edu>" <"apeters <"@> wrote in message
> news:99bdm9$2gi6$1@noao.edu...
> > Lee Iovino wrote:
> > >
> > > "Aggressive Meat" sounds like the name of a punk band from New Jersey.
> >
> > No, they were from across the river in Brooklyn.  You're thinking of the
> > Meatmen, who were actually from Chicago.
> >
> > -andy
> > former NJ punk rocker.

Article: 30156
Subject: Re: Simplified ISP of XCR3256XL from BIF file fails
From: Jennifer Jenkins <jennifer.jenkins@xilinx.com>
Date: Mon, 26 Mar 2001 10:03:57 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------1C9739A10A95AA887C541F3C
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Ian,

I'm not sure if the issue is with the Port Enable pin or not.  Is there a reason
you have the Port Enable pin connected to reset on the processor?  I'm sure
about the length of the processors' reset, but you may still be configuring the
device and toggling the Port Enable pin at the same time.   If you are not using
the JTAG pins for I/O, you should externally pull down the port enable pin.  The
Port Enable pin is only pulled high when the device has been configured where
the JTAG pins are used for I/O and it is desired to reclaim the JTAG pins.  For
more information on the Port Enable pin operation - please refer to XAPP343,
which can be found at http://www.xilinx.com/xapp/xapp343.pdf.

Are you able to perform a verify with the parallel cable and the PC-ISP
software?

Thanks,
Jennifer


Ian McCarthy wrote:

> Originally I had a 5V target system containing a PZ5128, this was programmed
> using the target CPU by bit-bashing the contents of a BIF file generated by
> the XPLA programmer software (as detailed in XAPP326 - Simplified in-circuit
> programming...).
>
> This worked perfectly.
>
> However now I have to use an XCR3256XL (3.3V) device in a 5V target system.
>
> I've re-made the design in WebPACK from a schematic and created a new BIF
> file.
>
> Bit-bashing this file into the device has no effect what so ever.
>
> The JTAG pins appear to be driven with the correct bit patterns.
>
> The PORT_EN pin is connected to the CPU RESET signal (active low) which is
> low as the system powers up and then goes high (although the port is also
> reserved in the design configuration).
>
> I've even put level translators in the TDI, TMS, TCK lines so the device
> JTAG port is driven at 3.3V rather than 5V but to no avail.
>
> Has anyone got any experience of this process with this device as at present
> I can see no solution.
>
> Many thanks in advance
>
> Ian McCarthy
> ianmccarthy@casella.co.uk

--------------1C9739A10A95AA887C541F3C
Content-Type: text/x-vcard; charset=us-ascii;
 name="jennifer.jenkins.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Jennifer Jenkins
Content-Disposition: attachment;
 filename="jennifer.jenkins.vcf"

begin:vcard 
n:Jenkins;Jennifer
tel;fax:(505) 858-3106
tel;work:(505) 798-4813
x-mozilla-html:FALSE
url:http://www.xilinx.com
org:Xilinx CoolRunner CPLDs;<br><img src="http://www.xilinx.com/images/xlogoc.gif" alt="Xilinx">
adr:;;7801 Jefferson St. NE;Albuquerque;New Mexico;87109;
version:2.1
email;internet:jennifer.jenkins@xilinx.com
title:Applications Engineer
fn:Jennifer Jenkins
end:vcard

--------------1C9739A10A95AA887C541F3C--


Article: 30157
Subject: Re: hybrid design entry
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Mon, 26 Mar 2001 19:11:40 +0200
Links: << >>  << T >>  << A >>
catherina schrieb:
> 
> Hi all,
> 
> Does F3.1 accepts  hybrid design top level entry ?
> 
> I want to instantiate in my top level entry, some modules based on :
> 1- schematic
> 2- Edif
> 3- Structural Vhdl
> 5- logicore
> any help (or reference) on how to proceed?

Iam not sure about 2), but the others work.

-- 
MFG
Falk

Article: 30158
Subject: Re: Asynchronus Mashine States
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Mon, 26 Mar 2001 19:14:36 +0200
Links: << >>  << T >>  << A >>
Marcin Michalak schrieb:
> 
> Hi!!
> 
>     Anybody know something about modeling Asynchronus Machine States in
> FPGA?
> I need some information about that. If anyone knows pages about that or have
> some
> information please write to me.

You really want to do asynchronous state machines?? AFAIK this is a big
NO-NO in most designs, because its too hard to debug, validate  . . . .


-- 
MFG
Falk

Article: 30159
Subject: Re: Asynchronus Mashine States
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Mon, 26 Mar 2001 09:44:44 -0800
Links: << >>  << T >>  << A >>
Marcin Michalak wrote:

> Anybody know something about modeling Asynchronus Machine States in
> FPGA?
> I need some information about that. If anyone knows pages about that or have
> some
> information please write to me.

A D-type flip flop is an asynchronous state machine.
Many digital textbooks show models.

If you design anything more complex, reserve time
for eliminating races and the resulting
state transition errors and output glitches.

 -Mike Treseler

Article: 30160
Subject: Re: Asynchronus Mashine States
From: Ray Andraka <ray@andraka.com>
Date: Mon, 26 Mar 2001 20:20:14 GMT
Links: << >>  << T >>  << A >>
ANd if in an FPGA, you better reserve time for instantiating the logic LUTs
too.  Otherwise your cover terms to avoid hazards are meaningless.  You also
have to be careful in FPGAs because the routing, which is not specified at
design capture, is a large part of the delay.



Mike Treseler wrote:
> 
> Marcin Michalak wrote:
> 
> > Anybody know something about modeling Asynchronus Machine States in
> > FPGA?
> > I need some information about that. If anyone knows pages about that or have
> > some
> > information please write to me.
> 
> A D-type flip flop is an asynchronous state machine.
> Many digital textbooks show models.
> 
> If you design anything more complex, reserve time
> for eliminating races and the resulting
> state transition errors and output glitches.
> 
>  -Mike Treseler

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com

Article: 30161
Subject: RAM read?
From: tider <tiderhuang@yahoo.com>
Date: Mon, 26 Mar 2001 13:12:18 -0800
Links: << >>  << T >>  << A >>
Hi, I have a question about Vertex II ram(distributed or block) synchronous read: if the read address does not change for many clock cycles, whether the data out is stable all the time, i.e., not change at the clock edge? Thanx.

Article: 30162
Subject: Logic trimmed (XCS40 F3.1)
From: "Marc Battyani" <Marc.Battyani@fractalconcept.com>
Date: Mon, 26 Mar 2001 23:19:38 +0200
Links: << >>  << T >>  << A >>
Help!

Almost all my logic is trimmed from my design. Where could I look to see
what is the pb ?
Even the clock are removed! When I look at the map report, it is full of
removed logic so I don't know what and where to look for the pb.

Thanks,

Marc Battyani



Article: 30163
Subject: Re: hybrid design entry
From: "catherina" <floreq10@hotmail.com>
Date: Mon, 26 Mar 2001 22:23:08 +0100
Links: << >>  << T >>  << A >>
HOW??


"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
news:3ABF784C.40CC2A6@gmx.de...
> catherina schrieb:
> >
> > Hi all,
> >
> > Does F3.1 accepts  hybrid design top level entry ?
> >
> > I want to instantiate in my top level entry, some modules based on :
> > 1- schematic
> > 2- Edif
> > 3- Structural Vhdl
> > 5- logicore
> > any help (or reference) on how to proceed?
>
> Iam not sure about 2), but the others work.
>
> --
> MFG
> Falk



Article: 30164
Subject: Xilinx FPGA Config file sizes.
From: "Dave Brown" <dbrown@novatel.ca>
Date: Mon, 26 Mar 2001 14:32:39 -0700
Links: << >>  << T >>  << A >>
I'm failry new to FPGA's and I just noticed that an example I synthesized
had a .bit file size that was 166KB and the coresponding .hex file I made
with PROM File Formatter was 329KB. The 166KB I can undersatnd, this is just
the 1335840 configuration bits for the Spartan II S200 device. Why is the
.hex file so much bigger? Is it always bigger? Is it always the same size
for a given device? And finally, how big would a hex file be for an
XCV1000E?
Thanks
Dave




Article: 30165
Subject: Re: RAM read?
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Mon, 26 Mar 2001 13:37:12 -0800
Links: << >>  << T >>  << A >>
Distributed RAM has combinatorial read ( not clocked )
But BlockRAM has clocked synchronous read.

In both cases, the output will *not* glitch if the input read address is stable ( of course assuming that the other port is not writing something different to this same location...)
Same for Virtex and Virtex-E

Peter A
==================
tider wrote:

> Hi, I have a question about Vertex II ram(distributed or block) synchronous read: if the read address does not change for many clock cycles, whether the data out is stable all the time, i.e., not change at the clock edge? Thanx.


Article: 30166
Subject: Re: Xilinx FPGA Config file sizes.
From: cyber_spook <pjc@cyberspook.freeserve.co.uk>
Date: Mon, 26 Mar 2001 23:42:18 +0100
Links: << >>  << T >>  << A >>
Hi,
 I don't known the full working of Spartan or the data in the .bit file... But I
can guess at your answer

I would say that your bit file is just raw data to be loaded into the FPGA,
However the .hex files are commom in programming devices like ROM's EPROMS etc,
and have a fixed format.

Basicly its a text file that details your .bit file

Example:

.bit file = (raw 8 bit hex values) {12}{04}{09}

.hex file would look somting like this (from memory so don't quote me on it)

2{address}{BCD hex data}{check digit}

ie. 2000000120409F

therefor .hex files are always bigger and it may be that Spartan allways
generates a fixed length file - maybe buffered out with zeros

Hope this helps.

Paul.

> Dave Brown wrote:

> I'm failry new to FPGA's and I just noticed that an example I synthesized
> had a .bit file size that was 166KB and the coresponding .hex file I made
> with PROM File Formatter was 329KB. The 166KB I can undersatnd, this is just
> the 1335840 configuration bits for the Spartan II S200 device. Why is the
> .hex file so much bigger? Is it always bigger? Is it always the same size
> for a given device? And finally, how big would a hex file be for an
> XCV1000E?
> Thanks
> Dave


Article: 30167
Subject: Alternatives for Xilinx Spartan-II configuration PROM
From: "Wade D. Peterson" <wadep@silicore.net>
Date: Mon, 26 Mar 2001 22:44:37 GMT
Links: << >>  << T >>  << A >>
Hi All:

I need to find a configuration PROM for a Spartan-II device from Xilinx.  Xilinx
has a new series of parts called the 'XC17S00A series (specifically, the
XC17S150APD8C) that are intended for the Spartan-II.  However, these appear to
be hard to find, plus my programmer doesn't support them yet.  Does anybody know
of any alternatives?

Also, does anybody know if the older Spartan PROMs work with the Spartan-II?

--
Wade D. Peterson
Silicore Corporation
URL: www.silicore.net



Article: 30168
Subject: Re: Logic trimmed (XCS40 F3.1)
From: name <name@company.com>
Date: Mon, 26 Mar 2001 15:56:03 -0700
Links: << >>  << T >>  << A >>
Marc Battyani wrote:
> 
> Help!
> 
> Almost all my logic is trimmed from my design. Where could I look to see
> what is the pb ?
> Even the clock are removed! When I look at the map report, it is full of
> removed logic so I don't know what and where to look for the pb.
> 
> Thanks,
> 
> Marc Battyani


It sound like your logic was either unsynthesizable or the compiler
thought it was unused. Check your source code for inconsistencies like
unused outputs.

-Mike

Article: 30169
Subject: Re: Alternatives for Xilinx Spartan-II configuration PROM
From: John Grider <jgrider@umr.edu>
Date: Mon, 26 Mar 2001 17:12:55 -0600
Links: << >>  << T >>  << A >>
"Wade D. Peterson" wrote:
> 
> Hi All:
> 
> I need to find a configuration PROM for a Spartan-II device from Xilinx.  Xilinx
> has a new series of parts called the 'XC17S00A series (specifically, the
> XC17S150APD8C) that are intended for the Spartan-II.  However, these appear to
> be hard to find, plus my programmer doesn't support them yet.  Does anybody know
> of any alternatives?

Yeah, I'm using some Atmel devices quite effectively.  Look for the
AT24Cxxx parts... An app note on their site describes the connection to
a Spartan-II...
-- john
___________________________________________________________
N recursive algorithms on the wall,
N recursive algorithms,
You take one down, pass it around.
N-1 recursive algorithms on the wall.
-----------------------------------------------------------
John Grider  REMOVEjgrider@umr.edu	(573) 308 - 3409
Electrical Engineering			1301 N. Oak St. #9
University of Missouri - Rolla  	Rolla, MO 65401
-----------------------------------------------------------

Article: 30170
Subject: Re: Logic trimmed (XCS40 F3.1)
From: "Marc Battyani" <Marc.Battyani@fractalconcept.com>
Date: Tue, 27 Mar 2001 01:27:35 +0200
Links: << >>  << T >>  << A >>

"name" <name@company.com> wrote
>Marc Battyani wrote:
> >
> > Almost all my logic is trimmed from my design. Where could I look to see
> > what is the pb ?
> > Even the clock are removed! When I look at the map report, it is full of
> > removed logic so I don't know what and where to look for the pb.
> >
> It sound like your logic was either unsynthesizable or the compiler
> thought it was unused. Check your source code for inconsistencies like
> unused outputs.

I checked but couldn't find any pb.
So I restored the last known good version which was quite ok with Foundation
2.1
The pb is that I when I compile it with F3.1 It optimizes away 99% of the
design!

It's getting worse.

In the map.mrp I get :
Optimized Block(s):
TYPE   BLOCK
VCC   C6640
GND   C6641

Does this means that it has removed VCC and GND ?!?!

Marc



Article: 30171
Subject: Virtex II RLOC
From: tider <tiderhuang@yahoo.com>
Date: Mon, 26 Mar 2001 16:10:47 -0800
Links: << >>  << T >>  << A >>
Hi,
What is the syntax in UCF file for Virtex II RLOC? For example, I have 2 "tap" module instances, each "tap" includes :one "mem1" module, one "mult", and one "out", I want these 3 have RLOC attribute: X0Y0, X1Y0, X2Y1. How do I edit UCF file manually to realize this?
Thank you very much.

Article: 30172
Subject: Re: Alternatives for Xilinx Spartan-II configuration PROM
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 27 Mar 2001 09:48:18 +0900
Links: << >>  << T >>  << A >>


> "Wade D. Peterson" wrote:
> > I need to find a configuration PROM for a Spartan-II device from Xilinx.  Xilinx
> > has a new series of parts called the 'XC17S00A series (specifically, the
> > XC17S150APD8C) that are intended for the Spartan-II.  However, these appear to
> > be hard to find, plus my programmer doesn't support them yet.  Does anybody know
> > of any alternatives?

John Grider <jgrider@umr.edu> writes:
> Yeah, I'm using some Atmel devices quite effectively.  Look for the
> AT24Cxxx parts... An app note on their site describes the connection to
> a Spartan-II...
> -- john

Also, ,the spartan-II-150, and the Virtex-150 bitstream sizes are the same, so 
you can use the Virtex PROM (XC1701, I think.)

HTH,
-Kent

Article: 30173
Subject: Re: Asynchronus Mashine States
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 27 Mar 2001 01:55:50 +0100
Links: << >>  << T >>  << A >>


Mike Treseler wrote:

> Marcin Michalak wrote:
>
> > Anybody know something about modeling Asynchronus Machine States in
> > FPGA?
> > I need some information about that. If anyone knows pages about that or have
> > some
> > information please write to me.
>
> A D-type flip flop is an asynchronous state machine.
> Many digital textbooks show models.
>
> If you design anything more complex, reserve time
> for eliminating races and the resulting
> state transition errors and output glitches.
>
>  -Mike Treseler

and then reserve that amount of time again x4 (min) to get it working after
power-up.



Article: 30174
Subject: a newbie question
From: "Minh Nguyen" <minh@ee.latrobe.edu.au>
Date: Tue, 27 Mar 2001 11:39:21 +1000
Links: << >>  << T >>  << A >>
HI,
I'm new to FPGA. would like to ask where to find some source codes about DSP
filter implementation on FPGA.
Thanx






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