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Messages from 30525

Article: 30525
Subject: Re: Changing Xilinx ROM contents without recompiling
From: Victor the Cleaner <jonathan@the-gimp.canuck.com>
Date: Thu, 12 Apr 2001 13:44:22 +0000 (UTC)
Links: << >>  << T >>  << A >>
Paul Urbanus <urb@ti.com> wrote:
: How can I change the contents of a block ROM or select ROM in the bitstream
: without recompiling the code.

: I'd like to embed a small micro + program memory in an FPGA and I don't want to
: have to go through the compile/place/route process just to change some memory
: initializations.

: TIA,
: Urb

There are supposedly a bunch of ways to get the block ram initialization into
the bitstream, but the only one we've been able to make work is by adding it 
to the UCF, with the attendant *bizarre* convolution of the data. 

This gets you halfway there - you still have to feed the UCF into the PAR, but
you won't have to recompile.

Jonathan


Article: 30526
Subject: Re: fpga from linux/hc11
From: "Pericles" <xantipo@teleline.es>
Date: Thu, 12 Apr 2001 14:24:13 GMT
Links: << >>  << T >>  << A >>
Hola.

Yo también estoy empezando a aprender el diseño de circuitos con FPGAs.
Estoy interesado en las de Xilinx Foundation. Me gustaría tener algunos
ejemplos de diseños ya hechos para poder aprender mejor. ¿Tú tienes alguno
que puedas mandarme, o sabes de algún sitio donde vengan ejemplos ya hechos?
Necesitaría algunos esquemáticos.

Saludos y gracias.


"Gonzalo Arana" <gonzaloa@sinectis.com.ar> escribió en el mensaje
news:3AC617D7.D10598F6@sinectis.com.ar...
> Hi,
>
> First of all, excuse my limited english (and spelling mistakes).
>
> Reinoud wrote:
> >
> > Hi Jean-Michel,
> >
> > > I've wanted to start playing with FPGAs for a long time, but never got
> > > to start a real project with these due to home-computers limitations :
> > > none of my computer have the resources/hard disk space to get win9x
> > > running (ie I do not want to dedicate one of my higher grade computers
> > > to fpga development by installing win9x on it as I would have no other
> > > use for that OS).
> >
> > Well, you can run Xilinx back-end tools under WINE on Linux, if that is
> > what you are running, see http://www.polybus.com/xilinx_on_linux.html.
>
> WINE is in alpha state.  It takes quite a lot of work to make a WinX
> program
> to behave (and even start) properly.  I whouln't try that alternative
> (unless
> you have the time).
> If I were you, I whould try the dual boot alternative Reinoud suggests.
> If you got WebPACK working propperly over WINE, please tell me how you
> did it
> (garana@sinectis.com.ar or gonzaloa@sinectis.com.ar).
>
> > Xilinx has fairly hefty tools, WEBPack, available for free (somewhere at
> > http://www.xilinx.com/). I'm not sure the HDL synthesis works under
WINE;
> > you could try hacking Icarus Verilog (http://icarus.com/eda/verilog/) to
> > target Virtex/Spartan-II for synthesis instead (it targets XC4k now).
>
> I did use WEBPack.  It's excellent (as deep as I used it), free and
> available.
> Lately Xilinx seems to have some problems on its web site: I tried
> lately to
> download the Device Programmer Tools -a "module" of WebPACK ISE-).
> You should try it.
> You may get it on following the links: www.xilinx.com -> products ->
> Design Tools -> Free WebPOWERED Software.
>
> >
> > Somehow, getting a bigger disk (that's cheap nowadays), installing
> > Windows, and dual-booting to run WEBPack seems less work (even though it
> > s*cks)...
> >
> > > 1/ how does one get from a VHDL document to a "binary" (or whatever
> > > it is called in the FPGA world) file ? With the altera tool, one had
> > > part AHDL subroutines, part graphical interface for connecting these
> > > subroutines tougether, click on "build" and there you get your
compiled
> > > file. Is there anything similar in the open-source world ? I seem to
> > > understand alliance will compile early Xilinx 4000 series EPLD, but I
> > > don't even know if these are still available.
> >
> > I don't really follow you here.  You need a HDL synthesis tool to turn
> > your HDL xource into a netlist, and a place&route back-end to map it
onto
> > the physical device.  The final device programming data goes into some
> > bitstream file, your 'binary' if you like.
> >
> > Note that Altera's (free) tools also run on Windows.  Alliance runs on
> > Solaris (SPARC) and HP-UX, last time I checked; no synthesis front-ends
> > included.
>
> As far as I know, you may program you design in VHDL and/or Verilog
> (that
> depends on the software tool), and then get the misterious "bit stream".
> You need to get that to a serial EEPROM.  That bit stream gets loaded
> into
> the FPGA when power is supplied.
>
> >
> > > 2/ once I get by "binary" file, I used to send it to the EPLD via the
> > > JTAG port. I suppose I could program an HC11 to get the files sent
from
> > > the PC through RS232 and send whatever signal is required by the JTAG
> > > protocol
> >
> > Xilinx FPGAs support a dead simple serial protocol. I'll post a download
> > utility for Linux tomorrow or so.
>
> Is there a download utility for Linux?.  Please, I would need that!!
>
> >
> > Have fun,
> >
> > - Reinoud
> >
> > ----
> >
> > Spam goes to wanabe, mail to wanadoo.
>
> Hope it helps,
>
> Gonzalo Arana



Article: 30527
Subject: Re: *help* how to count clock cycles in a design? how can i know its
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Thu, 12 Apr 2001 08:54:01 -0700
Links: << >>  << T >>  << A >>
JianYong Niu wrote:
> 
> Hi, all. I am learning FPGA design. I got an example writen in verilog, but
> I dont know how to count the clock cycles of it? and How can I know its
> execution speed? how to specify the clock frequency in verilog?


HDL synthesis code describes hardware behavior for 
each clock event, without regard to event rate.
The clock period is defined in the simulation testbench
and is limited only by the delay model from the 
device-specific place+route tool. 

Once you have a synthesized model of
your design, the quickest way to find the maximum
clock frequency is with the static timer in
your place+route tools.

To speed up your clock rate you can use a faster
device and/or pipeline your logic.


 -Mike Treseler

Article: 30528
Subject: Re: How to use clock generator in Vertex-e?
From: Tim Jaynes <tim.jaynes@xilinx.com>
Date: Thu, 12 Apr 2001 10:23:19 -0700
Links: << >>  << T >>  << A >>
Hwi-sung,
There is no clock generator in the Virtex-E part.
You'll have to get yourself an oscillator.
Regards,
Tim Jaynes
CAE


hwi-sung jung wrote:

> Hi, dear
>
> I'm a novice in Xilinx Vertex-e device.
> I'd like to know how to use clock generator in Vertex-e?
> In XC4000XL, I could use OSC4 module in library in order to
> generate clock inside the device.
> I looked through the data book, but I could not find out
> the usage of clock generator.
> I only could find about CLKDLL, but I think CLKIN signal should
> be necessary to generate clock with CLKDLL.
>
> Is it right?
> I hope your answer.
>
> Thanks


Article: 30529
Subject: Re: Is this realistic?
From: Tim Jaynes <tim.jaynes@xilinx.com>
Date: Thu, 12 Apr 2001 10:37:14 -0700
Links: << >>  << T >>  << A >>
Hi Dave,
In CPLD design the limiting factor is usually register count.
In this case you appear to need (2*16 + 3*8 + 1) = 57 regs., which should fit
fine in a 64 macrocell part.
The BCD Time-of-Day clock will add a lot more, but even then the design should
be able to fit in one of the higher density parts.
Regards,
Tim Jaynes
CAE


"Dave R." wrote:

> I am trying to duplicate an existing chip using VHDL.  My target platform
> is a Xilinx Coldfire CPLD, but the design just doesn't want to fit no
> matter how I tweak it.
>
> It consists of:
>
> Two 16-bit down counters
> One 8-bit serial I/O register
> Two 8-bit tristateable I/O ports
> One interrupt register
> Some handshaking logic
>
> The actual chip's design includes a Time-Of-Day clock in BCD format, but I
> haven't put that in yet.
>
> Is it realistic to expect all of this to fit in a CPLD, or should I change
> my target to an FPGA?
>
> --
>   :::::      Dave Ross / Dr. Watson          "Yesterday's technology
> ::    ===  watson@enteract.com              today...for a better
> ::    ===                                    tomorrow!"
>   :::::      http://www.enteract.com/~watson


Article: 30530
Subject: Re: Is this realistic?
From: Kolja Sulimma <kolja@prowokulta.org>
Date: Thu, 12 Apr 2001 19:54:16 +0200
Links: << >>  << T >>  << A >>
This should fit into 42 + epsilon macrocells if you are careful. Epsilon
depending largely on your handshake.

Many - but not all - cplds take just as many macrocells as flip-flops are used
in the  design.
This means for example, that a 16-Bit counter reset register will add another
16 Macrocells.
If you hold the last 8-Bit value from the shift register in another register
while shifting new values in,
you need another 8 macrocells.
If you can tristate the I/O ports per bit, you need 14 cells extra.
If you have seperate input and output registers, you need 16 cells extra.
Stopping the shift register after 8-cycles (counting to 8) costs another 3
cells (There is a trick to do it with 1)

It really should fit into a XC9572XL if you do not implement many of the above
extras at once.
A XC95144XL should be a save. I do not know about coldfire.

Kolja Sulimma


"Dave R." wrote:

> I am trying to duplicate an existing chip using VHDL.  My target platform
> is a Xilinx Coldfire CPLD, but the design just doesn't want to fit no
> matter how I tweak it.
>
> It consists of:
>
> Two 16-bit down counters
> One 8-bit serial I/O register
> Two 8-bit tristateable I/O ports
> One interrupt register
> Some handshaking logic
>
> The actual chip's design includes a Time-Of-Day clock in BCD format, but I
> haven't put that in yet.
>
> Is it realistic to expect all of this to fit in a CPLD, or should I change
> my target to an FPGA?
>
> --
>   :::::      Dave Ross / Dr. Watson          "Yesterday's technology
> ::    ===  watson@enteract.com              today...for a better
> ::    ===                                    tomorrow!"
>   :::::      http://www.enteract.com/~watson


Article: 30531
Subject: Re: Is this realistic?
From: Kolja Sulimma <kolja@prowokulta.org>
Date: Thu, 12 Apr 2001 22:16:00 +0200
Links: << >>  << T >>  << A >>
Oops. You want two 16-Bit counters. I only included one.
Here are the updatet estimates :-)

Kolja Sulimma wrote:

This should fit into 58 + epsilon macrocells if you are careful.

> Epsilon
> depending largely on your handshake.
>
> Many - but not all - cplds take just as many macrocells as flip-flops are used
> in the  design.

This means for example, that adding  registers with reset values for the counters
will add another
32 Macrocells.

> If you hold the last 8-Bit value from the shift register in another register
> while shifting new values in,
> you need another 8 macrocells.
> If you can tristate the I/O ports per bit, you need 14 cells extra.
> If you have seperate input and output registers, you need 16 cells extra.
> Stopping the shift register after 8-cycles (counting to 8) costs another 3
> cells (There is a trick to do it with 1)
>
> It really should fit into a XC9572XL if you do not implement the above
> extras.
> A XC95144XL should be a save. I do not know about coldfire.
>
> Kolja Sulimma
>
> "Dave R." wrote:
>
> > I am trying to duplicate an existing chip using VHDL.  My target platform
> > is a Xilinx Coldfire CPLD, but the design just doesn't want to fit no
> > matter how I tweak it.
> >
> > It consists of:
> >
> > Two 16-bit down counters
> > One 8-bit serial I/O register
> > Two 8-bit tristateable I/O ports
> > One interrupt register
> > Some handshaking logic
> >
> > The actual chip's design includes a Time-Of-Day clock in BCD format, but I
> > haven't put that in yet.
> >
> > Is it realistic to expect all of this to fit in a CPLD, or should I change
> > my target to an FPGA?
> >
> > --
> >   :::::      Dave Ross / Dr. Watson          "Yesterday's technology
> > ::    ===  watson@enteract.com              today...for a better
> > ::    ===                                    tomorrow!"
> >   :::::      http://www.enteract.com/~watson


Article: 30532
Subject: Re: Modlesim5.5
From: cyber_spook <pjc@cyberspook.freeserve.co.uk>
Date: Thu, 12 Apr 2001 22:01:28 +0100
Links: << >>  << T >>  << A >>
Were you getting a 'out of memory error' ?

As that was what I was getting...

Cyber_Spook

Leonid Shvarzberg wrote:

> I had similar problem and contacted modelsim support.
> They replied today and said that this bug had been fixed in release 5.5a
> which is ready for download.
> I have not tried it yet.
> LS.
>
> "W.Turk" <kgut@dotuy.com> wrote in message news:ee70257.-1@WebX.sUN8CHnE...
> > Hi Gang:
> >    Now ,i use Modelsim5.5.When i load or run a large design,it will
> > always close automatic.
> >    Why?


Article: 30533
Subject: Re: Handel-C
From: cyber_spook <pjc@cyberspook.freeserve.co.uk>
Date: Thu, 12 Apr 2001 22:10:56 +0100
Links: << >>  << T >>  << A >>
Read my lips!!!

Handle-C *IS* not C it a VHDL type language written in a 'C' style but that
it.

I have see software eng's try to do this - yes they have a foot on the ladder
knowing C but they don't know Handle-C and they don't know Hardware.

One chap said to me... "whats the differance between a MAX7096 and a FLEX20K?
as this will not complie to an MAX7096!!"

I say - go get a demo vertion and lean it! it will be a great tool that will
help you. Think about it... you go for an interview and you are a *hardware*
eng that fully understands VHDL and you have a basic knowlage of Handle-C. I
don't think I'd interview the chap above that asked that question - would you?

For the softy's out there they will see the simularities between C and VHDL as
it stands today - as a hard/software engineer I found VHDL very quick to pick
up and can even see bits of pascal in Verilog - VHDL and AHDL!? I don't see
every one getting worried about all them out of work pascal programmers
getting top paid hardware jobs.

Cyber_Spook

Brendan Lynskey wrote:

> So considering all that's been said, what a VHDLer to do?
>
> Is anyone else out there slightly worried about this whole thing? Maybe we
> should all accept the inevitable and take a course in programming?


Article: 30534
Subject: Re: Handel-C
From: "niki" <guest@my.net>
Date: Thu, 12 Apr 2001 22:56:30 GMT
Links: << >>  << T >>  << A >>
Amzaing! I thought this news group is for hardware guys. However, poeple
here seem to worry about their jobs because of fancy "Handel-C". ;-) (For
your reference, I talked with at least 5 years experienced engineering
colleagues in my consulting firm. Surprise! Nobody heard Handel-C. Me,
either.)

If you really worry about your hardware job, go to Synopsys education
sessions and learn theier C++ aproach synthesis. Youl will find there is no
difference between C++ and HDL approach synthesis. Folks, basically it is a
matter of real hardware, not an abstract language. 



Article: 30535
Subject: Re: RC4/ARC4 on an FPGA.
From: "james.rowland1" <james.rowland1@ntlworld.com>
Date: Fri, 13 Apr 2001 02:00:26 +0100
Links: << >>  << T >>  << A >>
Dear Matt,

have a lovely time in Sweden!

Cheers

James

Matt Hayes <matthewhayes9000@hotmail.com> wrote in message
news:3ac9ba09$1@news.star.co.uk...
> I'm aware that quite a number of people believe that the RC4 algorithm
isn't
> particularly suited to hardware but the idea interests me nonetheless.
>
> I have performed a few websearches but can't really find the answers I am
> looking for.
>
> In particular, I would like to know:
> a) what rates of data throughput have been achieved by RC4 implementations
> on an FPGA? what is the fastest ever?
> b) if it is possible to purchase a fast RC4/ARC4 IP Core and what
throughput
> rates can be expected.
>
> Thanks,
>
>    Matt.
>
>



Article: 30536
Subject: Is there any free processor core for vertex series?
From: "Jae-cheol Lee" <jchlee@lgic.co.kr>
Date: Fri, 13 Apr 2001 01:43:06 GMT
Links: << >>  << T >>  << A >>
I've ever heard that there exist free processor cores for FPGAs.

Where can I find one for Xilinx vertex series ?

I think XCV2000E could emulate 4MHz Z80 or 6502 including other peripherals.




Article: 30537
Subject: Re: Is there any free processor core for vertex series?
From: "Jan Gray" <jsgray@acm.org>
Date: Thu, 12 Apr 2001 19:03:33 -0700
Links: << >>  << T >>  << A >>
The pipelined xr16, originally designed for XC4000E-derivatives, can be
ported to Virtex with little effort (www.fpgacpu.org/xsoc/).  I've done so,
but not yet refreshed the online XSOC Kit with my (small) Virtex
optimizations.

The non-pipelined gr0040 is designed for Virtex/Spartan-II
(www.fpgapcu.org/gr/).

Both are licensed under the XSOC License Agreement
(www.fpgacpu.org/xsoc/LICENSE.html), which in part grants certain uses
without fee for non-commercial applications.

Mike Butts has a nice independent reimplementation of the xr16 instruction
set architecture, for Virtex, named xr16vx.  (Mike, is it out yet?)

There are also links to many other FPGA CPU cores at
www.fpgacpu.org/links.html.  (If anyone knows of *other* FPGA CPUs, I'd
appreciate an email pointer to them so I can update the list.)

Jan Gray, Gray Research LLC
FPGA CPU News: www.fpgacpu.org




Article: 30538
Subject: Thank you very much.
From: "Jae-cheol Lee" <jchlee@lgic.co.kr>
Date: Fri, 13 Apr 2001 02:42:53 GMT
Links: << >>  << T >>  << A >>
Thank you very much.
It will be of great help for my study.
Take care~~

"Jan Gray" <jsgray@acm.org> wrote in message
news:9b5mva$vep$1@slb1.atl.mindspring.net...
> The pipelined xr16, originally designed for XC4000E-derivatives, can be
> ported to Virtex with little effort (www.fpgacpu.org/xsoc/).  I've done
so,
> but not yet refreshed the online XSOC Kit with my (small) Virtex
> optimizations.
>
> The non-pipelined gr0040 is designed for Virtex/Spartan-II
> (www.fpgapcu.org/gr/).
>
> Both are licensed under the XSOC License Agreement
> (www.fpgacpu.org/xsoc/LICENSE.html), which in part grants certain uses
> without fee for non-commercial applications.
>
> Mike Butts has a nice independent reimplementation of the xr16 instruction
> set architecture, for Virtex, named xr16vx.  (Mike, is it out yet?)
>
> There are also links to many other FPGA CPU cores at
> www.fpgacpu.org/links.html.  (If anyone knows of *other* FPGA CPUs, I'd
> appreciate an email pointer to them so I can update the list.)
>
> Jan Gray, Gray Research LLC
> FPGA CPU News: www.fpgacpu.org
>
>
>



Article: 30539
Subject: Re: Thank you very much.
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Thu, 12 Apr 2001 20:31:07 -0700
Links: << >>  << T >>  << A >>
Jae,

For something simple:

 http://www.support.xilinx.com/apps/virtexapp.htm

and look at app note 213.

Austin


Jae-cheol Lee wrote:

> Thank you very much.
> It will be of great help for my study.
> Take care~~
>
> "Jan Gray" <jsgray@acm.org> wrote in message
> news:9b5mva$vep$1@slb1.atl.mindspring.net...
> > The pipelined xr16, originally designed for XC4000E-derivatives, can be
> > ported to Virtex with little effort (www.fpgacpu.org/xsoc/).  I've done
> so,
> > but not yet refreshed the online XSOC Kit with my (small) Virtex
> > optimizations.
> >
> > The non-pipelined gr0040 is designed for Virtex/Spartan-II
> > (www.fpgapcu.org/gr/).
> >
> > Both are licensed under the XSOC License Agreement
> > (www.fpgacpu.org/xsoc/LICENSE.html), which in part grants certain uses
> > without fee for non-commercial applications.
> >
> > Mike Butts has a nice independent reimplementation of the xr16 instruction
> > set architecture, for Virtex, named xr16vx.  (Mike, is it out yet?)
> >
> > There are also links to many other FPGA CPU cores at
> > www.fpgacpu.org/links.html.  (If anyone knows of *other* FPGA CPUs, I'd
> > appreciate an email pointer to them so I can update the list.)
> >
> > Jan Gray, Gray Research LLC
> > FPGA CPU News: www.fpgacpu.org
> >
> >
> >


Article: 30540
Subject: not IOB
From: yose@wam.umd.edu (Joe Wetstein)
Date: 13 Apr 2001 02:06:34 -0400
Links: << >>  << T >>  << A >>
How do I get FFs to instantiate in the CORE as opposed to the 
IOB, even if they are output FFs, using verilog and design manager
for a xilinx virtexe?



Article: 30541
Subject: Re: not IOB
From: Nicolas Matringe <nicolas.matringe@IPricot.com>
Date: Fri, 13 Apr 2001 10:10:19 +0200
Links: << >>  << T >>  << A >>
Joe Wetstein wrote:
> 
> How do I get FFs to instantiate in the CORE as opposed to the
> IOB, even if they are output FFs, using verilog and design
> manager for a xilinx virtexe?

You can edit the .ucf file and add a line like this:

INST "*" IOB = FALSE;

This will prevent the placer from putting anything in the IOBs (except
the I/OBUFs I hope :o)

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 30542
Subject: Re: Is there any free processor core for vertex series?
From: "Keith Jasinski, Jr." <cartracin@nospam.yahoo.com>
Date: Fri, 13 Apr 2001 08:17:18 -0500
Links: << >>  << T >>  << A >>
http://www.opencores.org

Good starters to play with

--
Keith Jasinski, Jr.

*The opinions expressed herein are those of the author and not his
employer...
"Jae-cheol Lee" <jchlee@lgic.co.kr> wrote in message
news:KQsB6.2112$2b5.22213@news2.bora.net...
> I've ever heard that there exist free processor cores for FPGAs.
>
> Where can I find one for Xilinx vertex series ?
>
> I think XCV2000E could emulate 4MHz Z80 or 6502 including other
peripherals.
>
>
>



Article: 30543
Subject: Re: Modlesim5.5
From: Filip Gielen <filip.gielen@smartmove-eu.com>
Date: Fri, 13 Apr 2001 14:30:22 GMT
Links: << >>  << T >>  << A >>
Dit is een multi-gedeelten-bericht in MIME-formaat.
--------------4506B11A26F74CCF95BDCCD0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

I just tried it and it looks more stable than the 5.5
So I thinks they solved the problem.

Flippo

Leonid Shvarzberg schreef:

> I had similar problem and contacted modelsim support.
> They replied today and said that this bug had been fixed in release 5.5a
> which is ready for download.
> I have not tried it yet.
> LS.
>
> "W.Turk" <kgut@dotuy.com> wrote in message news:ee70257.-1@WebX.sUN8CHnE...
> > Hi Gang:
> >    Now ,i use Modelsim5.5.When i load or run a large design,it will
> > always close automatic.
> >    Why?

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Article: 30544
Subject: Re: Modlesim5.5
From: Nicolas Matringe <nicolas.matringe@IPricot.com>
Date: Fri, 13 Apr 2001 16:45:31 +0200
Links: << >>  << T >>  << A >>
Filip Gielen wrote:
> 
> I just tried it and it looks more stable than the 5.5
> So I thinks they solved the problem.

I have downloaded it and encountered a problem with textio (I've
reported it but have no news yet): ModelSim crashes just after reading
the last character of a line.

Anyone else got the problem?

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 30545
Subject: ad: Spartan II Prototyping boards.
From: Richard Meester <rme@quest-innovations.com>
Date: Fri, 13 Apr 2001 16:59:37 +0200
Links: << >>  << T >>  << A >>
Hello All,

Please ignore if inaproptiate, but i thought it might be usefull
information since the question about Prototyping boards regularly comes
by.

We just released our  Xilinx SPARTAN II XCIIS150 based prototyping board
with a programmable clock from 10 to 133 MHz, on board memory for the
bitfile and an onboard microcontroller. Secondly we released software to
program the board. This software is written in 100% pure Java, so must
run both on Windows and Linux.

We uploaded our website with the latest information, and should thus be
available today or tomorrow from the internet.

Sorry if this email caused any inconvenience, but i think for most
people who read the newsgroup it is usefull information.



Richard.


Ps. We offer the first 50 buyers of a kit a 6 month "licence to use" to
our Java to Hardware compiler.

--
Quest Innovations
tel: +31 (0) 227 604046
http://www.quest-innovations.com



Article: 30546
Subject: Re: Pinout tables
From: "Vikram Pasham" <vikram.pasham@xilinx.com>
Date: Fri, 13 Apr 2001 12:33:10 -0800
Links: << >>  << T >>  << A >>
On popular demand, we posted all the
Virtex-E/Virtex-EM and Virtex-II pinout
tables in text format on the web. 

These pinout table are more elaborate and organized in the format

Physical Row/Col-RAM Package VCCO IO Output LVDS <br>
Name Location Name Bank Type Asynchronous <br>

These package files can be found at
http://www.xilinx.com/products/virtex/vepackages.htm

http://www.xilinx.com/products/virtex/v2packages.htm

Vikram <br>
Xilinx Applications

Article: 30547
Subject: Xilinx LUT's and Synopsys DC
From: Patatralla <rhuerta_rivera@student.ei.uni-stuttgart.de>
Date: Sat, 14 Apr 2001 03:42:07 +0200
Links: << >>  << T >>  << A >>
Hi,
  Is there a way to know which are the INIT values of each LUT instance
in the output netlist from Synopsys DC
after synthesis ?  They are present in the edif file but not in the
verilog one.

Thanks,
Ramon



Article: 30548
Subject: Re: pseudo random numbers
From: Marc D Bumble <bumble@isd.net>
Date: 13 Apr 2001 23:29:17 -0400
Links: << >>  << T >>  << A >>

For a simple pseudo random number generator implementation for an
FPGA, see the following references:

@Article{hoogland83,
  author = 	 {A. Hoogland and J. Spaa and B. Selman and A. Compagner},
  title = 	 {A special-purpose processor for the monte carlo simulation for ising spin systems},
  journal = 	 {Journal of Computational Physics},
  year = 	 1983,
  volume =	 51,
  pages =	 {250-260}
}

@Article{pearson83,
  author = 	 {Robert B Pearson and John L. Richardson and Doug Toussant},
  title = 	 {A Fast Processor for Monte-Carlo Simulation},
  journal = 	 {Journal of Computational Physics},
  year = 	 1983,
  volume =	 51,
  pages =	 {241-249}
}


>> "Jörg" == Jörg Ritter <ritter@informatik.uni-halle.de> writes:

  > Hi Ray, I've a more general question concerning the app notes.  In
  > those app notes tricky circuits are presented , which fits into a
  > few CLB's.  Mostly a schematic describes the circuit.

  > If the circuit isn't available in Coregen/Logiblox what is your
  > favorite way to create a module (as netlist)?  Do you implement
  > the design structurally in VHDL, synthesize and floorplan the
  > result manually?  Or do you prefer a schematic entry tool, where
  > you can instantiate basic XC4000 elements, e.g. like RAM16x1S?

  > Thanks Joerg

  >> There are no random sources inherent in the FPGA, although you
  >> could conceivably use the phase difference between the internal
  >> oscillator in the 4Kparts and an external clock.  I'd prefer to
  >> use the linear feedback shift register (LFSR) with a long enough
  >> sequence to make it random over a long interval.  That can be
  >> done very compactly in the 4K using CLB ram (see the xilinx app
  >> note on LFSRs, I think it is XAPP152).


-- 


Article: 30549
Subject: VHDL FFT core: where?
From: "llandre" <andmars@tin.it>
Date: Sat, 14 Apr 2001 11:46:11 GMT
Links: << >>  << T >>  << A >>
I'm looking for a free FFT core written in VHDL for a graduating
thesis. Where ca I find it?

Thanks a lot in advance.

--
llandre
 e-mail : andmarsNOSPAM@tin.it
 web    : http://www.dei.unipd.it/~patch






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