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Messages from 30975

Article: 30975
Subject: Re: ccd imaging with fpga
From: Jonas Thor <thor.NO@SPAM.sm.luth.se>
Date: Mon, 07 May 2001 11:44:33 +0200
Links: << >>  << T >>  << A >>
Here is another link...

http://www.beyondlogic.org/imaging/camera.htm

/ Jonas

On Wed, 02 May 2001 08:38:23 +0200, Kolja Sulimma
<kolja@prowokulta.org> wrote:

>The OV7620 evaluation module by omnivision is about 25% less expensive.
>
>Jonas Thor wrote:
>
>> Here is a small digital CMOS camera that you could interface to a
>> FPGA:
>>
>> http://www.quasarelectronics.com/cmos_cameras.htm#cdc
>>


Article: 30976
Subject: Licensing PB in Synplify_pro 6.2
From: "Christian Illinger" <illinger@lepsi.in2p3.fr>
Date: Mon, 7 May 2001 16:01:54 +0200
Links: << >>  << T >>  << A >>
  Hello,
  We have a Unix Network license for Synplify_pro.
  and I have installed Synplify 6.2 on a WinNT4-SP5 machine
  Unfortunaly the date on this machine was 2 months in future !
  I modified to the correct date and now
  when I want to start Synplify_pro a get the following message :

  --> The date on this machine has been set back !
  --> Unable to get license.

  My date is ok.
  My license is ok. (tested on a other WinNT machine).
  But Synplify_pro doesn't work.

  I have ununstalled and reinstalled Synplify_pro, but nothing
  helps.

  Has somebody a solution for me ?

  Thanks.

  Christian Illinger







Article: 30977
Subject: Re: Shannon Capacity
From: Jamie Lokier <spamfilter.may2001@tantalophile.demon.co.uk>
Date: 07 May 2001 16:58:47 +0200
Links: << >>  << T >>  << A >>
Steve Rencontre writes:
>> C refers the the capacity of a physical band-limited 
>> channel.  By definition, C includes *all* the data carried by the
>> channel. This includes the payload data and any overhead (parity bytes,
>> etc) needed for the FEC layer if used.

> Sorry, but that doesn't add up. Shannon's Theorem says that you can carry 
> C bps /without/ error. In that case, why have you included error detection 
> and correction bits with the payload data?!

As you use progressively more sophisticated coding schemes, the relative
number of error correction bits you need _for a given error rate_
decreases... towards zero.

Note, you cannot guarantee zero errors, you can merely implement schemes
which reduce the probability of errors arbitrarily close to zero.  This
only works when the data rate is below the channel capacity.

The hard part is finding and implementing suitable coding schemes.
Also, the coding/decoding delay increases as you approach the limit.

(take with pinch of salt; this is what I understand intuitively, and I
haven't properly studied the theory).

-- Jamie

Article: 30978
Subject: Re: Licensing PB in Synplify_pro 6.2
From: "Erik Widding" <widding@birger.com>
Date: Mon, 07 May 2001 21:31:52 GMT
Links: << >>  << T >>  << A >>
"Christian Illinger" <illinger@lepsi.in2p3.fr> wrote in message
news:9d69pv$nj6$1@ccpntc8.in2p3.fr...
>   Hello,
>   We have a Unix Network license for Synplify_pro.
>   and I have installed Synplify 6.2 on a WinNT4-SP5 machine
>   Unfortunaly the date on this machine was 2 months in future !
>   I modified to the correct date and now
>   when I want to start Synplify_pro a get the following message :
>
>   --> The date on this machine has been set back !
>   --> Unable to get license.
>
>   My date is ok.
>   My license is ok. (tested on a other WinNT machine).
>   But Synplify_pro doesn't work.
>
>   I have ununstalled and reinstalled Synplify_pro, but nothing
>   helps.
>
>   Has somebody a solution for me ?

Don't use the software for two months.

Or set ahead the time on the computer by two months.  The major caveat: the
license will now expire two months earlier, or worse yet, have already
expired.

Seriously, call Synplicity to fix it.  They will likely need to reset the
date that your key thinks it is.  And, this unfortunately means that you
will have to send them the key.


Regards,
Erik Widding.

--
Birger Engineering, Inc.  --------------------------------  781.481.9233
38 Montvale Ave #260; Stoneham, MA 02180  -------  http://www.birger.com




Article: 30979
Subject: Xilinx Virtex Libraries for Synopsys Behav. Compil
From: "Pedro Diniz" <pedro@isi.edu>
Date: Mon, 7 May 2001 16:30:22 -0700
Links: << >>  << T >>  << A >>
All,

I cannot find the Xilinx Virtex Libraries for Synopsys 
Behavioral Compiler. Anybody knows where to downloaded from?

Many thanks

Pedro

Article: 30980
Subject: Re: Internal Error of routing in iSE3.3i
From: Bret Wade <bret.wade@xilinx.com>
Date: Mon, 07 May 2001 17:52:54 -0600
Links: << >>  << T >>  << A >>
Hello Huang,

This is a known problem and a router patch is being developed. An Answer record with more information
will soon be available  at support.xilinx.com/techdocs/11130.htm.

Regards,
Bret Wade
Xilinx Product Applications

Huang wrote:

> Hi,
>
> When I started routing my design, PAR terminated abnormally, with the following error information.
>
> Routing active signals.
> INTERNAL_ERROR:SpeedCalc:basndtiming.c:887:1.6 - Getnodeparms for node not on
>    signal
> EXEWRAP detected a return code of '-1073741819' from program 'par'
>
> Done: failed with exit code: 0005.
>
> Can someone help me?
>
> Thanks in advance!


Article: 30981
Subject: Re: Internal Error of routing in iSE3.3i
From: Bret Wade <bret.wade@xilinx.com>
Date: Mon, 07 May 2001 17:53:33 -0600
Links: << >>  << T >>  << A >>
Hello Huang,

This is a known problem and a router patch is being developed. An Answer record with more information
will soon be available  at support.xilinx.com/techdocs/11130.htm.

Regards,
Bret Wade
Xilinx Product Applications

Huang wrote:

> Hi,
>
> When I started routing my design, PAR terminated abnormally, with the following error information.
>
> Routing active signals.
> INTERNAL_ERROR:SpeedCalc:basndtiming.c:887:1.6 - Getnodeparms for node not on
>    signal
> EXEWRAP detected a return code of '-1073741819' from program 'par'
>
> Done: failed with exit code: 0005.
>
> Can someone help me?
>
> Thanks in advance!


Article: 30982
Subject: Re: Shannon Capacity
From: Vikram Pasham <Vikram.Pasham@xilinx.com>
Date: Mon, 07 May 2001 18:46:20 -0700
Links: << >>  << T >>  << A >>
Berni & all,

One of Shannon's paper "A Mathematical Theory of Communication" can be found on
the web at
http://cm.bell-labs.com/cm/ms/what/shannonday/shannon1948.pdf

As per my understanding, "C" in Shanon's equation includes information +
parity.

-Vikram
Xilinx

Berni Joss wrote:

> "Austin Lesea" <austin.lesea@xilinx.com> wrote in message
> news:3AF027BD.50AFA29B@xilinx.com...
> > Wrong.
> >
> > Go back and re-read his paper.
>
> Austin, I do not agree with your interpretation of Shannon's theorem ...
> but I'm convinced that you're right about the value of reading his paper.
> Any hints on where I could find a copy?
> I don't live close to a library, so an web link would be much appreciated.
>
> Berni.
>
> >
> > This is really funny, and sad.
> >
> > Austin
> >
> > Steve Rencontre wrote:
> >
> > > In article <3AEF11CD.CEA6992D@xilinx.com>, austin.lesea@xilinx.com
> (Austin
> > > Lesea) wrote:
> > >
> > > > See what I mean?
> > > >
> > > > Still confused after all these years.
> > > >
> > > > If the CRC is not information, then you don't need it.
> > > >
> > > > If the CRC is information, then you need to send it.
> > > >
> > > > I rest my case.
> > > >
> > > > Austin
> > >
> > > I disagree. The CRC (or whatever) is not information, but you do need
> to
> > > send it! The total message of N+CRC physical bit symbols only carries
> > > N bits of /information/, and it's that which Shannon's theorem applies
> to.
> > >
> > > I think the confusion arises because we automatically think that a 1 or
> 0
> > > in the digital domain is a 'bit' in the Shannon sense, but it's not -
> it's
> > > just a symbol which can be used to encode bits. Adding a CRC increases
> the
> > > predictability of lost symbols, which means each 0/1 symbol carries
> less
> > > than one actual bit.
> > >
> > > Shannon tells us how many bits of genuine information we can transmit,
> but
> > > we're free to send as many
> > > symbols-which-superficially-look-like-bits-but-aren't as we like :-)
> > >
> > > --
> > > Steve Rencontre         http://www.rsn-tech.co.uk
> > > //#include <disclaimer.h>
> >


Article: 30983
Subject: Xilinx compressed .bit file format
From: Alan Nishioka <alann@accom.com>
Date: Mon, 07 May 2001 19:16:52 -0700
Links: << >>  << T >>  << A >>
Does anyone know the file format for a Xilinx *compressed* .bit file?

Alan Nishioka
alan@nishioka.com



Article: 30984
Subject: Re: Licensing PB in Synplify_pro 6.2
From: Muzaffer Kal <muzaffer@dspia.com>
Date: Tue, 08 May 2001 03:34:55 GMT
Links: << >>  << T >>  << A >>
On Mon, 7 May 2001 16:01:54 +0200, "Christian Illinger"
<illinger@lepsi.in2p3.fr> wrote:

>  Hello,
>  We have a Unix Network license for Synplify_pro.
>  and I have installed Synplify 6.2 on a WinNT4-SP5 machine
>  Unfortunaly the date on this machine was 2 months in future !
>  I modified to the correct date and now
>  when I want to start Synplify_pro a get the following message :
>
>  --> The date on this machine has been set back !
>  --> Unable to get license.
>
>  My date is ok.
>  My license is ok. (tested on a other WinNT machine).

but your file dates are not OK and this is causing the problem. One
thing you can do is to do a touch on all files which are forward
dated. Sometimes this is not possible because the files are in use by
the OS. In this case rebooting after the date change sometimes helps.
The worst case solution is an OS reinstall.

Muzaffer

FPGA DSP Consulting
http://www.dspia.com

Article: 30985
Subject: analog and digital?
From: "Tomasz Brychcy" <T.Brychcy@ime.pz.zgora.pl>
Date: Tue, 8 May 2001 07:11:40 +0200
Links: << >>  << T >>  << A >>
Hello,

What is a difference between analog design and digital design?

Best regards

Tomek



Article: 30986
Subject: Re: Licensing PB in Synplify_pro 6.2
From: "Markus Sponsel" <msponsel@profichip.com>
Date: Tue, 8 May 2001 08:39:56 +0200
Links: << >>  << T >>  << A >>
Hi there,

unfortunately (or thank god) synplify pro has a very heavy protection. We
had the same problem in our company some time ago where a trainee
manipulated the date 6 (!) month in the future to test another program.
"Only" reformating the harddrive end putting the OS new to it wonn't work.
it seems that the license manager writes the date somewhere to the
bootsector. So the easiest way is to contact synplicity to get this problem
solved. Otherwise you have to format your harddrive (also clean the
bootsector, but be careful !! this may destroy your harddrive) and put the
OS new to it and reinstall synplify pro. So we (the trainee) did and it
worked again. Next time we will contact synplicity, because it was a pain to
do the procedure.

c.u. Markus


>   Hello,
>   We have a Unix Network license for Synplify_pro.
>   and I have installed Synplify 6.2 on a WinNT4-SP5 machine
>   Unfortunaly the date on this machine was 2 months in future !
>   I modified to the correct date and now
>   when I want to start Synplify_pro a get the following message :
>
>   --> The date on this machine has been set back !
>   --> Unable to get license.
>
>   My date is ok.
>   My license is ok. (tested on a other WinNT machine).
>   But Synplify_pro doesn't work.
>
>   I have ununstalled and reinstalled Synplify_pro, but nothing
>   helps.
>
>   Has somebody a solution for me ?
>
>   Thanks.
>
>   Christian Illinger



Article: 30987
Subject: Re: Shannon Capacity
From: asuihkon@beta.hut.fi (Aki M Suihkonen)
Date: 8 May 2001 06:53:43 GMT
Links: << >>  << T >>  << A >>
In article <3AF74FEC.9CE2C870@xilinx.com> Vikram.Pasham@xilinx.com writes:
>Berni & all,
>
>One of Shannon's paper "A Mathematical Theory of Communication" can be found on
>the web at
>http://cm.bell-labs.com/cm/ms/what/shannonday/shannon1948.pdf
>
>As per my understanding, "C" in Shanon's equation includes information +
>parity.
>
Did you bother to read it?

The discrete noiseless channel section contains an example of
a 'perfect code' Hamming (7,4) under a restricted noise model.
In this case, C = 4/7 - not including the parity.

Progressively more complex coding will at N -> inf, correct N*H bits
where H is the entropy of the noise channel. 

-- 
Problems      1) do NOT write a virus or a worm program
"A.K.Dewdney, The New Turing Omnibus; Chapter 60: Computer viruses"

Article: 30988
Subject: Re: analog and digital?
From: "Dziadek" <dziales@poczta.onet.pl>
Date: Tue, 8 May 2001 09:48:06 +0200
Links: << >>  << T >>  << A >>
Analog design includes analog signals that change continously between
extremes.
Digital design includes digital signals that can have only a few
distinguishable states.

HC

Tomasz Brychcy wrote in message <3af77f8d$1@news.vogel.pl>...
>Hello,
>
>What is a difference between analog design and digital design?
>
>Best regards
>
>Tomek
>
>



Article: 30989
Subject: Routing: Completed - errors found.
From: Roger.chen <chenx@263.net>
Date: Tue, 8 May 2001 01:09:18 -0700
Links: << >>  << T >>  << A >>
I use VirtexII in my design,the following is the device utilization summary:
   Number of External OBs           114 out of 324    35%
   Number of RAMB16s                  20 out of 40     50%
   Number of SLICEs                 2552 out of 5120   49%
   Number of BUFGMUXs                  5 out of 16     31%
  Number of DCMs                      3 out of 8      37%
the following is part of the place and route report: 

Dumping design to file fpga_ixbus_to_swc.ncd.

Starting Optimizing Placer.  REAL time: 1 hrs 42 mins 49 secs 
Optimizing  .
Swapped 44 comps.
Xilinx Placer [1]   799611   REAL time: 1 hrs 43 mins 10 secs 
Optimizing  .
Swapped 12 comps.
Xilinx Placer [2]   799428   REAL time: 1 hrs 43 mins 28 secs 
Finished Optimizing Placer.  REAL time: 1 hrs 43 mins 28 secs 

Starting Leveraged Guide Placer Termination.  REAL time: 1 hrs 43 mins 29 secs 
Successfully maintained guided placement of 78 out of 2694 comps (mapped
physical logic cells).
Finished Leveraged Guide Placer Termination.  REAL time: 1 hrs 43 mins 31 secs 

Dumping design to file fpga_ixbus_to_swc.ncd.

Total REAL time to Placer completion: 1 hrs 43 mins 34 secs 
Total CPU time to Placer completion: 1 hrs 41 mins 3 secs 

Total REAL time: 1 hrs 43 mins 42 secs 
Total CPU  time: 1 hrs 41 mins 11 secs 
End of route.  0 routed (0.00%); 20904 unrouted active,
   896 unrouted PWR/GND.
No errors found. 
WARNING:Route:53 - 7186 signals are not completely routed. 

This design was not fully routed.  To help fully route the design, you may try
the following:
  * Retarget the design to the next larger device in this family.

The design submitted for place and route did not meet the specified timing
requirements.  Please use the static timing analysis tools (TRCE or Timing
Analyzer) to report which constraints were not met.  To obtain a better result,
you may try the following:
  * Use the Re-entrant routing feature to run more router iterations on the
design.
  * Check the timing constraints to make sure the design is not
over-constrained.
  * Specify a higher placer effort level, if possible.
  * Use the Multi-Pass PAR (MPPR) feature.  This generates multiple placement
trials from which the best (i.e., lowest design score) placement can be used
with re-entrant routing to obtain a better result.

Please consult the Development System Reference Guide for more detailed
information about the usage options pertaining to these features.

Total REAL time to Router completion: 1 hrs 43 mins 43 secs 
Total CPU time to Router completion: 1 hrs 41 mins 12 secs 

Generating PAR statistics.

   The Delay Summary Report

   The Score for this design is: 495000

The Number of signals not completely routed for this design is: 7186

   The Average Connection Delay for this design is:        0.000 ns
   The Maximum Pin Delay is:                               0.000 ns
   The Average Connection Delay on the 10 Worst Nets is:   0.000 ns

   Listing Pin Delays by value: (ns)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
           0           0           0           0           0           0

Timing Score: 0

Please may I ask why there are so many unrouted nets and how to deal with them?
 Thank you!

Article: 30990
Subject: Re: timing simulation on Modelsim
From: Alan Fitch <alan.fitch@doulos.com>
Date: Tue, 8 May 2001 09:51:51 +0100
Links: << >>  << T >>  << A >>
In article <ee707c4.-1@WebX.sUN8CHnE>, tiderh <tiderhuang@yahoo.com>
writes
>Hi,
>I use xilinx foudation ISE timing analyzer( I set timing constraint, CLK=360MHz 
>and turn on the option:perform hold/race checks(skew analysis) ) for my virtex 
>II design, and the timing requirement can be met, but when I use the latest 
>modelsim to do timing simulation, and I set the setup time and output delay the 
>same as timing analyzer, i.e., 0.23ns and 0.4ns respectively, the outputs are 
>wrong(red sign)( the function simultation is correct ). What is the reason? 
>Which one should I trust, the timing analyzer or the modelsim?
>Thank you very much.
>
>Sincerely yours,
>
>tiderh

There's a couple of things you could look at

1) have you set the time resolution of Modelsim to a small enough value?
When you elaborate the design (Load Design) you can specify the time
resolution. If you don't, values that are smaller than the time
resolution will get "rounded".

2) There's a Xilinx application note explaining how you may see timing
violations when doing VITAL simulation due to differences in the way
Xilinx specify time delays, and the way VITAL specifies time delays,
search for answer record #782 "How can hold time violations occur when
the data book states 0ns hold times?"

kind regards

Alan

-- 
Alan Fitch
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223                        Email: alan.fitch@doulos.com
Fax: +44 1425 471573                             Web: http://www.doulos.com

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                   **  Developing design know-how  **
                   **********************************

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from  your  system, any  use, disclosure, or copying  of this  document  is
unauthorised. The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.









Article: 30991
Subject: Re: Shannon Capacity
From: nemo@dtgnet.com (Nemo)
Date: Tue, 08 May 2001 12:59:14 GMT
Links: << >>  << T >>  << A >>
asuihkon@beta.hut.fi (Aki M Suihkonen) wrote:

>In article <3AF74FEC.9CE2C870@xilinx.com> Vikram.Pasham@xilinx.com writes:
>>Berni & all,
>>
>>One of Shannon's paper "A Mathematical Theory of Communication" can be found on
>>the web at
>>http://cm.bell-labs.com/cm/ms/what/shannonday/shannon1948.pdf
>>
>>As per my understanding, "C" in Shanon's equation includes information +
>>parity.
>>
>Did you bother to read it?
>
>The discrete noiseless channel section contains an example of
>a 'perfect code' Hamming (7,4) under a restricted noise model.
>In this case, C = 4/7 - not including the parity.

Funny, the only reference to Hamming that I see in the paper is in
PART II: THE DISCRETE CHANNEL WITH NOISE subsection...
17. AN EXAMPLE OF EFFICIENT CODING  on page 27.

In the equation you refer to, Shannon is setting up an (unrealistic) example
where a block of seven binary symbols can either be unerrored, or have exactly
one errored symbol.  The equation shows that this (non-AWGN) noise condition
creates a channel with 4/7 bits/symbol capacity (this has nothing to do with
parity, he hasn't even discussed the Hamming block code yet!)  He then at the
top of page 28 shows how a seven symbol Hamming block code can identify the
errored symbol in the above example.  Did *you* read the paper?  Did you read
the original post? BTW -  This thread has been discussing the Shannon-Hartley
theorem and the equation for channel capacity of a band-limited channel in the
presence of AWGN (bits-per-second).  


>
>Progressively more complex coding will at N -> inf, correct N*H bits
>where H is the entropy of the noise channel. 


Article: 30992
Subject: xplaopt.exe - Application error
From: Alan Glynne Jones <nospam@newsranger.com>
Date: Tue, 08 May 2001 14:02:13 GMT
Links: << >>  << T >>  << A >>
The problem that is making my life a misery at the moment is an application
error message generated by Windows NT.
-----------------------------------------------------------------------------------------------------------------------------
xplaopt.exe - Application error

The instruction at "0x004fbe7c" referenced memory at "0x00000010".  The memory
could not be "read"

Click on OK to terminate the application
Click on CANCEL to debug the application
-----------------------------------------------------------------------------------------------------------------------------
After closing this window, another comes,
-----------------------------------------------------------------------------------------------------------------------------
Dr Watson for Windows NT

An application error has occurred
and an application error log is being generated.

xplaopt.exe
Exception: access violation (0xc0000005), Address: 0x004fbe7c
-----------------------------------------------------------------------------------------------------------------------------

I was basically trying to synthesise and implement a smallish design using the
WebPack VHDL project Navigator, this error came up intermittently to begin with
but now occurs every time.  I can still successfully synthesise and implement
other code.  I have tried fiddling with the process options, I have tried
deleting and re-installing the WebPack software, this had no effect.  I have now
had a new HDD image installed to start from scratch and installed the WebPack
design entry and WebPack XPLA fitter once more and I get the same problem when
attempting to implement my VHDL code.

This problem does not occur when the same files are implemented on a colleagues
machine, it successfully completes the process generating a file for the device
programmer.  My collegue uses a custom installation of NT.
I have 128MB RAM, 10GB HDD, Intel 730MHz running NT version 4 (build 1381:
service pack 6)

It looks like there is some basic incompatibility problem between NT and the
WebPack application.  Have you come across this problem before?  Can anybody
help?

regards,

Alan

PS I have attached the VHDL code I have been trying to synthesise.



Article: 30993
Subject: Re: PCI bridge core
From: "Dave Feustel" <dfeustel@mindspring.com>
Date: Tue, 8 May 2001 09:26:47 -0500
Links: << >>  << T >>  << A >>
What version of Verilog and VHDL do you use?

"Miha Dolenc" <mihad@opencores.org> wrote in message news:988899220.834152@pacman.amis.net...
> Hi!
>
>     I'm a member of OpenCores group and we are designing a free PCI bridge
> IP core that would target FPGA and ASICs. If anyone is interested in helping
> us out in our effort is very welcome.
> You can read more about it on our website
>
> www.opencores.org
>
> where you can also subscribe to our mailing lists.
> Any kind of help is welcome - advices, HDL design, verification,
> documentation.
> Languages we use for our cores are Verilog and VHDL.
>
> We already have a part of specification ready and are still working on it,
> so anyone interested can download it from our site (
> http://www.opencores.org/cgi-bin/cvsget.cgi/pci/docs/pci_specification.pdf )
> . Comments, feedback, advice are welcome.
>
> Regards,
>     Miha Dolenc
>
>



Article: 30994
Subject: Re: Routing: Completed - errors found.
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 08 May 2001 18:08:30 +0100
Links: << >>  << T >>  << A >>


"Roger.chen" wrote:

> I use VirtexII in my design,the following is the device utilization summary:
>    Number of External OBs           114 out of 324    35%
>    Number of RAMB16s                  20 out of 40     50%
>    Number of SLICEs                 2552 out of 5120   49%
>    Number of BUFGMUXs                  5 out of 16     31%
>   Number of DCMs                      3 out of 8      37%
> the following is part of the place and route report:
>
> Dumping design to file fpga_ixbus_to_swc.ncd.
>
> Starting Optimizing Placer.  REAL time: 1 hrs 42 mins 49 secs
> Optimizing  .
> Swapped 44 comps.
> Xilinx Placer [1]   799611   REAL time: 1 hrs 43 mins 10 secs
> Optimizing  .
> Swapped 12 comps.
> Xilinx Placer [2]   799428   REAL time: 1 hrs 43 mins 28 secs
> Finished Optimizing Placer.  REAL time: 1 hrs 43 mins 28 secs
>
> Starting Leveraged Guide Placer Termination.  REAL time: 1 hrs 43 mins 29 secs
> Successfully maintained guided placement of 78 out of 2694 comps (mapped
> physical logic cells).
> Finished Leveraged Guide Placer Termination.  REAL time: 1 hrs 43 mins 31 secs
>
> Dumping design to file fpga_ixbus_to_swc.ncd.
>
> Total REAL time to Placer completion: 1 hrs 43 mins 34 secs
> Total CPU time to Placer completion: 1 hrs 41 mins 3 secs
>
> Total REAL time: 1 hrs 43 mins 42 secs
> Total CPU  time: 1 hrs 41 mins 11 secs
> End of route.  0 routed (0.00%); 20904 unrouted active,
>    896 unrouted PWR/GND.
> No errors found.
> WARNING:Route:53 - 7186 signals are not completely routed.
>
> This design was not fully routed.  To help fully route the design, you may try
> the following:
>   * Retarget the design to the next larger device in this family.
>
> The design submitted for place and route did not meet the specified timing
> requirements.  Please use the static timing analysis tools (TRCE or Timing
> Analyzer) to report which constraints were not met.  To obtain a better result,
> you may try the following:
>   * Use the Re-entrant routing feature to run more router iterations on the
> design.
>   * Check the timing constraints to make sure the design is not
> over-constrained.
>   * Specify a higher placer effort level, if possible.
>   * Use the Multi-Pass PAR (MPPR) feature.  This generates multiple placement
> trials from which the best (i.e., lowest design score) placement can be used
> with re-entrant routing to obtain a better result.
>
> Please consult the Development System Reference Guide for more detailed
> information about the usage options pertaining to these features.
>
> Total REAL time to Router completion: 1 hrs 43 mins 43 secs
> Total CPU time to Router completion: 1 hrs 41 mins 12 secs
>
> Generating PAR statistics.
>
>    The Delay Summary Report
>
>    The Score for this design is: 495000
>
> The Number of signals not completely routed for this design is: 7186
>
>    The Average Connection Delay for this design is:        0.000 ns
>    The Maximum Pin Delay is:                               0.000 ns
>    The Average Connection Delay on the 10 Worst Nets is:   0.000 ns
>
>    Listing Pin Delays by value: (ns)
>
>     d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
>    ---------   ---------   ---------   ---------   ---------   ---------
>            0           0           0           0           0           0
>
> Timing Score: 0
>
> Please may I ask why there are so many unrouted nets and how to deal with them?
>  Thank you!

Looks like what you get with the PAR ``-r'' [no route] flag set. I think you should
also be concerned that it took so long just to do the placement. For an 85% used
XCV400E I get worried if the placer takes > 10 min.




Article: 30995
Subject: SYnopsys Library Compiler and LUT synthesis
From: "Venkatesh Akella" <akella@ece.ucdavis.edu>
Date: Tue, 8 May 2001 10:11:22 -0700
Links: << >>  << T >>  << A >>
Hi,

    Recently I've been playing around with Synopsis Library Compiler trying
to develop a LUT based FPGA synthesis library. From what I have read from
the Reference Manuals and User Guides (as sketchy as they are) it seems I
have been able to develop a library that compiles, but not one I can perform
synthesis with.

    In essense I'm trying to get FPGA_compiler to technology map to LUTs
rather than gate primities during synthesis, but appear not to be having any
luck. My synthesis library only contains a LUT definition and registers. The
LUT definition is as follows:

library ( lut ) {
   technology ( fpga );

 ..... etc.....

   cell (lut4) {
      area : 0.5 ;
      pin ( A B C D) {
          direction : input;
      }
      lut(L) {
         input_pins : "A B C D" ;
      }
      pin (Z) {
         direction : output;
         function : "(L)" ;
      }
   }
}

    This compiles fine with Library compiler and produces the library file
lut.db.

    However, when I try to compile a small design with very simple
combinatorial logic, FPGA_compiler gives the following error message:

compile -map_effort medium

  Loading target library 'lut'
Error: The target library does not contain all required gates.
Either a NOR, or an AND and an OR gate (two-input) is required for mapping.
(OPT-102)
Information: Compile terminated abnormally. (OPT-100)

   It appears that FPGA_compiler requires at least a NOR or and AND and an
OR gate to technology map. However, I would like to direct it to map to LUT
technology as decribed by my synthesis library.

   Is there something that I am missing here? I've tried many different
times but with no success. Can anyone help me in trying to resolve this
problem.

Thanks in advance,

Mathew

mwojko@yahoo.com





Article: 30996
Subject: Re: SYnopsys Library Compiler and LUT synthesis
From: Srinivasan Venkataramanan <srini@realchip.co.in>
Date: Tue, 08 May 2001 22:53:51 +0530
Links: << >>  << T >>  << A >>
Hi,

Venkatesh Akella wrote:
> 
> Hi,
> 
<SNIP>
> combinatorial logic, FPGA_compiler gives the following error message:
> 
> compile -map_effort medium
> 
>   Loading target library 'lut'
> Error: The target library does not contain all required gates.
> Either a NOR, or an AND and an OR gate (two-input) is required for mapping.
> (OPT-102)

I haven't used this tool, neither I am a FPGA Designer.

  In general Logic synthesis rests on the fact that NAND & NOR are
basic gates and we could implement any complex combinatorial logic
with either of them (or both). So I think what FPGA express trying to
do is to do this simple check before proceeding further. So to make
the tool happy, just add a NOR gate to your library and set a
"dont_use" attribute on that cell.

  Not sure whether this will solve your problem (:-

Good Luck,
Srini

> Information: Compile terminated abnormally. (OPT-100)
> 

-- 
Srinivasan Venkataramanan (Srini)
ASIC Design Engineer,
Chennai (Madras), India

Article: 30997
Subject: Re: Routing: Completed - errors found.
From: Scott Campbell <scott.campbell@xilinx.com>
Date: Tue, 08 May 2001 11:56:18 -0600
Links: << >>  << T >>  << A >>
Hello Roger, the reason the nets are not routed in this case is because to do so
would not allow your device to meet timing. I say this because the resource
utilization in your part is not near full, and no nets were routed. I think the
best place to start is where the tools suggest you do so. Try the following ...

1.) Effort level: What effort level are you running the tools at ? Try effort level
5. It takes more time, but gives better results.

2.) Run the tools without timing constraints. See what your critical path is,
optimize it, and set your timing constraints accordingly. Having constraints set to
tight - meaning asking for a 200 MHz frequency when 25 MHz is the theoretical limit
- will cuase the tools to fail. See what the tools can do without constraints, then
interatively tighten the requirements from there.

3.) When you are close to your desired operational frequency, run multi-pass place
and route to get the final bit of performance out of the design.

Ok, I hope these suggestions help.

Best regrards,
Scott

"Roger.chen" wrote:

> I use VirtexII in my design,the following is the device utilization summary:
>    Number of External OBs           114 out of 324    35%
>    Number of RAMB16s                  20 out of 40     50%
>    Number of SLICEs                 2552 out of 5120   49%
>    Number of BUFGMUXs                  5 out of 16     31%
>   Number of DCMs                      3 out of 8      37%
> the following is part of the place and route report:
>
> Dumping design to file fpga_ixbus_to_swc.ncd.
>
> Starting Optimizing Placer.  REAL time: 1 hrs 42 mins 49 secs
> Optimizing  .
> Swapped 44 comps.
> Xilinx Placer [1]   799611   REAL time: 1 hrs 43 mins 10 secs
> Optimizing  .
> Swapped 12 comps.
> Xilinx Placer [2]   799428   REAL time: 1 hrs 43 mins 28 secs
> Finished Optimizing Placer.  REAL time: 1 hrs 43 mins 28 secs
>
> Starting Leveraged Guide Placer Termination.  REAL time: 1 hrs 43 mins 29 secs
> Successfully maintained guided placement of 78 out of 2694 comps (mapped
> physical logic cells).
> Finished Leveraged Guide Placer Termination.  REAL time: 1 hrs 43 mins 31 secs
>
> Dumping design to file fpga_ixbus_to_swc.ncd.
>
> Total REAL time to Placer completion: 1 hrs 43 mins 34 secs
> Total CPU time to Placer completion: 1 hrs 41 mins 3 secs
>
> Total REAL time: 1 hrs 43 mins 42 secs
> Total CPU  time: 1 hrs 41 mins 11 secs
> End of route.  0 routed (0.00%); 20904 unrouted active,
>    896 unrouted PWR/GND.
> No errors found.
> WARNING:Route:53 - 7186 signals are not completely routed.
>
> This design was not fully routed.  To help fully route the design, you may try
> the following:
>   * Retarget the design to the next larger device in this family.
>
> The design submitted for place and route did not meet the specified timing
> requirements.  Please use the static timing analysis tools (TRCE or Timing
> Analyzer) to report which constraints were not met.  To obtain a better result,
> you may try the following:
>   * Use the Re-entrant routing feature to run more router iterations on the
> design.
>   * Check the timing constraints to make sure the design is not
> over-constrained.
>   * Specify a higher placer effort level, if possible.
>   * Use the Multi-Pass PAR (MPPR) feature.  This generates multiple placement
> trials from which the best (i.e., lowest design score) placement can be used
> with re-entrant routing to obtain a better result.
>
> Please consult the Development System Reference Guide for more detailed
> information about the usage options pertaining to these features.
>
> Total REAL time to Router completion: 1 hrs 43 mins 43 secs
> Total CPU time to Router completion: 1 hrs 41 mins 12 secs
>
> Generating PAR statistics.
>
>    The Delay Summary Report
>
>    The Score for this design is: 495000
>
> The Number of signals not completely routed for this design is: 7186
>
>    The Average Connection Delay for this design is:        0.000 ns
>    The Maximum Pin Delay is:                               0.000 ns
>    The Average Connection Delay on the 10 Worst Nets is:   0.000 ns
>
>    Listing Pin Delays by value: (ns)
>
>     d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
>    ---------   ---------   ---------   ---------   ---------   ---------
>            0           0           0           0           0           0
>
> Timing Score: 0
>
> Please may I ask why there are so many unrouted nets and how to deal with them?
>  Thank you!


Article: 30998
Subject: Re: Routing: Completed - errors found.
From: Kevin Smith <xkevinsm@ti.com>
Date: Tue, 08 May 2001 16:33:10 -0500
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------6F8D6591A36C16AAB0B7AB7B
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Try it without a "guide file", or, if you are using "exact" mode, set it to
"leverage" instead.  If you are using an *.NCD file that is many design iterations
old, it's possible that your design has simply changed too much to meet the
requirements that the guide file is imposing.  This happens to me, so I change my
"guide" file every couple revisions or so.

Good luck,
---
Keb'm

"Roger.chen" wrote:

> I use VirtexII in my design,the following is the device utilization summary:
>    Number of External OBs           114 out of 324    35%
>    Number of RAMB16s                  20 out of 40     50%
>    Number of SLICEs                 2552 out of 5120   49%
>    Number of BUFGMUXs                  5 out of 16     31%
>   Number of DCMs                      3 out of 8      37%
> the following is part of the place and route report:
>
> Dumping design to file fpga_ixbus_to_swc.ncd.
>
> Starting Optimizing Placer.  REAL time: 1 hrs 42 mins 49 secs
> Optimizing  .
> Swapped 44 comps.
> Xilinx Placer [1]   799611   REAL time: 1 hrs 43 mins 10 secs
> Optimizing  .
> Swapped 12 comps.
> Xilinx Placer [2]   799428   REAL time: 1 hrs 43 mins 28 secs
> Finished Optimizing Placer.  REAL time: 1 hrs 43 mins 28 secs
>
> Starting Leveraged Guide Placer Termination.  REAL time: 1 hrs 43 mins 29 secs
> Successfully maintained guided placement of 78 out of 2694 comps (mapped
> physical logic cells).
> Finished Leveraged Guide Placer Termination.  REAL time: 1 hrs 43 mins 31 secs
>
> Dumping design to file fpga_ixbus_to_swc.ncd.
>
> Total REAL time to Placer completion: 1 hrs 43 mins 34 secs
> Total CPU time to Placer completion: 1 hrs 41 mins 3 secs
>
> Total REAL time: 1 hrs 43 mins 42 secs
> Total CPU  time: 1 hrs 41 mins 11 secs
> End of route.  0 routed (0.00%); 20904 unrouted active,
>    896 unrouted PWR/GND.
> No errors found.
> WARNING:Route:53 - 7186 signals are not completely routed.
>
> This design was not fully routed.  To help fully route the design, you may try
> the following:
>   * Retarget the design to the next larger device in this family.
>
> The design submitted for place and route did not meet the specified timing
> requirements.  Please use the static timing analysis tools (TRCE or Timing
> Analyzer) to report which constraints were not met.  To obtain a better result,
> you may try the following:
>   * Use the Re-entrant routing feature to run more router iterations on the
> design.
>   * Check the timing constraints to make sure the design is not
> over-constrained.
>   * Specify a higher placer effort level, if possible.
>   * Use the Multi-Pass PAR (MPPR) feature.  This generates multiple placement
> trials from which the best (i.e., lowest design score) placement can be used
> with re-entrant routing to obtain a better result.
>
> Please consult the Development System Reference Guide for more detailed
> information about the usage options pertaining to these features.
>
> Total REAL time to Router completion: 1 hrs 43 mins 43 secs
> Total CPU time to Router completion: 1 hrs 41 mins 12 secs
>
> Generating PAR statistics.
>
>    The Delay Summary Report
>
>    The Score for this design is: 495000
>
> The Number of signals not completely routed for this design is: 7186
>
>    The Average Connection Delay for this design is:        0.000 ns
>    The Maximum Pin Delay is:                               0.000 ns
>    The Average Connection Delay on the 10 Worst Nets is:   0.000 ns
>
>    Listing Pin Delays by value: (ns)
>
>     d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
>    ---------   ---------   ---------   ---------   ---------   ---------
>            0           0           0           0           0           0
>
> Timing Score: 0
>
> Please may I ask why there are so many unrouted nets and how to deal with them?
>  Thank you!

--
A democracy is three wolves and a sheep voting on what's for dinner.
A republic is where the sheep get to vote for which wolves vote on what's for
dinner.
And a constitutional republic is where voting on dinner is expressly forbidden, and
the sheep are armed.


--------------6F8D6591A36C16AAB0B7AB7B
Content-Type: text/x-vcard; charset=us-ascii;
 name="xkevinsm.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Kevin Smith
Content-Disposition: attachment;
 filename="xkevinsm.vcf"

begin:vcard 
n:Smith;Kevin
tel;fax:(972) 222-0855
tel;home:(972) 222-2395
tel;work:(972) 222-0808
x-mozilla-html:TRUE
org:Texas Instruments
adr:;;3332 High Meadow drive;Mesquite;TX;75181;US
version:2.1
email;internet:xkevinsm@ti.com
title:Contract Logic Designer
note;quoted-printable:What would John Galt do? -- Ayn Rand=0D=0AJazz isn't dead, it just smells funny. --Frank Zappa=0D=0AGive a skeptic an inch, and he'll measure it.  --Unknown
x-mozilla-cpt:;-23552
fn:Kevin Smith
end:vcard

--------------6F8D6591A36C16AAB0B7AB7B--


Article: 30999
Subject: Re: Xilinx Constraints Editor ?
From: Kevin Smith <xkevinsm@ti.com>
Date: Tue, 08 May 2001 16:39:51 -0500
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------40F4E444352D0E868141E55A
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Why not use OFFSET=IN BEFORE and OFFSET=OUT AFTER so the P&R tool does
the arithemetic for you?  If you use these options it takes into account both
the clock period
(assuming you use a PERIOD constraint), as well as the clock input buffer
delay.
---
Keb'm

"Keith R. Williams" wrote:

> Is there a way of specifying OFFSET = IN AFTER and OFFSET = OUT BEFORE
> from the constraints editor (Alliance 3.1i)?  I would rather have the
> tool do the arithmetic (clock cycle isn't fixed).
>
> ----
>   Keith

--
A democracy is three wolves and a sheep voting on what's for dinner.
A republic is where the sheep get to vote for which wolves vote on what's for
dinner.
And a constitutional republic is where voting on dinner is expressly forbidden,
and the sheep are armed.


--------------40F4E444352D0E868141E55A
Content-Type: text/x-vcard; charset=us-ascii;
 name="xkevinsm.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Kevin Smith
Content-Disposition: attachment;
 filename="xkevinsm.vcf"

begin:vcard 
n:Smith;Kevin
tel;fax:(972) 222-0855
tel;home:(972) 222-2395
tel;work:(972) 222-0808
x-mozilla-html:TRUE
org:Texas Instruments
adr:;;3332 High Meadow drive;Mesquite;TX;75181;US
version:2.1
email;internet:xkevinsm@ti.com
title:Contract Logic Designer
note;quoted-printable:What would John Galt do? -- Ayn Rand=0D=0AJazz isn't dead, it just smells funny. --Frank Zappa=0D=0AGive a skeptic an inch, and he'll measure it.  --Unknown
x-mozilla-cpt:;-23552
fn:Kevin Smith
end:vcard

--------------40F4E444352D0E868141E55A--




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