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Messages from 30625

Article: 30625
Subject: Re: looking for comment on implementation
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Thu, 19 Apr 2001 10:07:02 -0700
Links: << >>  << T >>  << A >>


Paul Teagle wrote:

> Maybe some complication to put the angle into an (a+b) format first, but how
> hard can it be :-)
>
> Obviously, we'll need a couple more multipliers & adders, but from the sound
> of it, the Virtex-II multipliers will cope with the speed (?)
>
>

Don't forget that you really need table-look-up only for one quadrant. You can
get the other quadrants by XORing the inputs and the outputs of the look-up
tables.
If you are conservative and go for the 2-stroke method, using the two ports
alternatingly, you may be able to combine each XOR with the mux into one LUT,
essentially at no cost in area and time. Just a thought...

Peter Alfke



Article: 30626
Subject: Digital Design Positions Available
From: Kristen_G_Kosar <kristen_g_kosar@raytheon.com>
Date: Thu, 19 Apr 2001 14:35:53 -0400
Links: << >>  << T >>  << A >>
Raytheon- Towson, Maryland

COMPANY BACKGROUND
Throughout its 75- year history, the Raytheon Company has been a leader
in developing defense technologies and converting those technologies for
use in commercial markets. Today, Raytheon is focused on its core
businesses: defense and commercial electronics and business aviation and
special mission aircraft. Each provides the company with the
capabilities it needs to build on, its strength as an innovator and to
prosper in a highly competitive global economy. As one of the largest
industrial corporations in the United States, Raytheon had 19.8 Billion
in 1999 revenues.  Raytheon has over 100,000 employees worldwide serving
customers in more than 70 countries.


JOB DESCRIPTION
Due to recent wins including the PRM contract for San Francisco and
SIFF, we have a number of employment opportunities for Electrical
Engineers.  We are looking for at least 10 new EEs, especially those
who have experience with Digital Design.  We will entertain permanent
and contract employees.

We have the following positions available:
Electrical Engineer I
Electrical Engineer II
Sr. Electrical Engineer I
Sr. Electrical Engineer II


 Type: Full-Time
 Class: Direct Charge
 Salary: E01, E02, E03, E04
 EEO: Professionals


Brief statement of mission/purpose of work groups:
The groups supports the design, installation and integration of air
traffic
control secondary surveillance systems for the FAA and development of
IFF Interrogator systems for military aircraft, ships and ground-based
applications.

Job Description:
Digital design using CAD tools. Implementation may include PWB or FPGA.
Hardware design, development, and integration of PRM systems.

Required Skills:

Design of Digital systems and Microprocessor based system VHDL, VME bus,
Mentor Graphics.  Analog/Digital interfacing.
Demonstrated capabilities in requirements/functional analysis and
validation, functional/physical verification, synthesis and systems
analysis.  Experience should include some familiarity with VHDL, digital
design using CAD tools, simulation, digital test and integration.

Desired Skills:
Knowledge of military standards.  Design basics for EMI/EMC.

Degree Required: Bachelors
Major Required: Electrical Engineering
Certification Required? N







Article: 30627
Subject: Re: clocking on both edges
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Fri, 20 Apr 2001 08:25:30 +1200
Links: << >>  << T >>  << A >>
Hal Murray wrote:
> 
> >Yes it's a dirty trick, and the pulse length is ill-defined. And you
> >should not do this at multiple 100 MHz. But when there is no other
> >solution, this works just fine. It gets you dirty comments from the
> >synchronous purists though. It's your choice.
> 
> OK, I'll keep the discussion going.
> 
> Why doesn't that work at "multiple 100 MHz"?
> 
> Is there some scaling property that I'm missing?

 As Peter has mentioned this has Tco+(Multiple Tpd) widths on the clock
stub,
and these tend to track process, Vcc and Temp.

 Things to watch out for, as freq is pushed, are 
 The LOW time of the stub reducing below Tclmin, at highest Freq, and
worst case corner

 You can add a second FF, that clocks on CPin, and D or J samples
(delayed) 
Clock stub, which will check that the stub has gone low early enough.
 This can be use for margin testing, as can varying the delay in the
Q-XOR path

-jg.

Article: 30628
Subject: some general questions about FPGA design
From: "Yu, Wenjiang [BVW:KCK2:EXCH]" <wenjyu@americasm01.nt.com>
Date: Thu, 19 Apr 2001 16:28:29 -0400
Links: << >>  << T >>  << A >>
Hi,

Is there any one who would like give some ideas about my questions?

1. What are the advantage and disadvantage of using multiple clocks in
   FPGA design?

2. What are the advantage and disadvantage of using asynchronous logic
   in a FPGA design?

I will really appreciate your response.

Wenjiang Yu
e-mail: wenjyu@nortelnetworks.com

Article: 30629
Subject: Re: clocking on both edges
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Thu, 19 Apr 2001 14:26:42 -0700
Links: << >>  << T >>  << A >>
Proud as I am of this clever (?) circuit, I also must mention that you don't
need it at all when get frequency multiplication for free in any of the
Virtex-class devices, i.e. Spartan-II, Virtex, Virtex-E and Virtex-II. In the
latter you even have a built-in frequency synthesizer as well as precision phase
control.

I am in the process of designing a pulse generator that can generate 1024
different frequencies between 100 and 200 MHz and then also divide them down in
30 binaries, down to below 1 Hz. Always with a resolution of 1 part per 1000,
and crystal stability.
"30,000 frequencies at your fingertip".
Takes about a third of the tiny XC2V40, leaving plenty of room for a 1 GHz
8-digit frequency counter. A real fun project.

Peter Alfke
=========================
Jim Granville wrote:

>  As Peter has mentioned this has Tco+(Multiple Tpd) widths on the clock
> stub,
> and these tend to track process, Vcc and Temp.
>
>  Things to watch out for, as freq is pushed, are
>  The LOW time of the stub reducing below Tclmin, at highest Freq, and
> worst case corner
>
>  You can add a second FF, that clocks on CPin, and D or J samples
> (delayed)
> Clock stub, which will check that the stub has gone low early enough.
>  This can be use for margin testing, as can varying the delay in the
> Q-XOR path
>
> -jg.


Article: 30630
Subject: Re: some general questions about FPGA design
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Thu, 19 Apr 2001 14:42:20 -0700
Links: << >>  << T >>  << A >>


"Yu, Wenjiang [BVW:KCK2:EXCH]" wrote:

> Hi,
>
> Is there any one who would like give some ideas about my questions?
>
> 1. What are the advantage and disadvantage of using multiple clocks in
>    FPGA design?

In most cases, the number of different clocks is dictated by the systems design.

The only advantage of multiple clocks inside a chip is that it might reduce
clock power consumption under particular circumstances. Otherwise it is
undesirable because it causes metastability issues whenever data has to cross
clock boundaries.

>
>
> 2. What are the advantage and disadvantage of using asynchronous logic
>    in a FPGA design?

Asynchronous designs can be faster and sometimes even smaller, but they require
very careful worst-case analysis, and should only be used by experienced
designers. Synchronous may be slower, but is generally much safer.

Peter Alfke, Xilinx Applications



Article: 30631
Subject: Re: PAR single pass vs multi-pass differences
From: "Chris G. Schneider" <chris@cgschneider.com>
Date: 19 Apr 2001 23:43:40 +0200
Links: << >>  << T >>  << A >>

I have made the experience that the results are identical if I
delete all files of the previous run. I think that one of the programs
recognize that there is already an intermediate result on the system
and use it then. 

I do not use MPPR I use a loop instead that tries all costtables until
the constraints are met. I've made the experience that if you've found
a "good" costtable, the you can just use it for the next run using the
-t option. It is very likely the meet the constrains faster, if you
just make small changes.

Best Regards, 

Chris


Utku Ozcan <ozcan@netas.com.tr> writes:

> > I have run 2 SPPRs on the same computer.  This resulted in identical
> > download files, so I can rule out transient computer problems.
> >
> > I have also run an additional SPPR on a different computer, with the
> > same EDIF and command line arguments.
> > It produced a result that was different to both the SPPR and MPPR
> > results from the first computer.
> > It also worked ok in the lab, whereas the SPPR download from the first
> > computer had functional problems.
> >
> > This implied to me that the installation of the Xilinx programs had been
> > corrupted on one of the computers, so I compared all the executable
> > files and speed files, etc. on the two computers, and they were
> > identical.
> >
> > So why should two computers produce different results if they are
> > running identical programs with identical input?
> > I don't think that PAR uses the machine ID to seed the random number
> > generator.
> > I might have missed comparing one of the files though, or it could be a
> > difference in a system DLL.
> 
> Very tight observation, thank you very much for your comments.
> 
> Then machine time might be different? Maybe tools use machine time for
> seed to obtain "random" behavior. Ok, you are using PC, probably it is
> similar under UNIX. Well, anyway, these things will be unanswered questions
> for a while then!
> 
> > Regards,
> > Allan.
> 
> Utku
> 

-- 
Chris

Article: 30632
Subject: Re: some general questions about FPGA design
From: eteam <eteam@aracnet.com>
Date: Thu, 19 Apr 2001 16:45:35 -0700
Links: << >>  << T >>  << A >>
It should also be mentioned that in a classic fully synchronous design, the
system clock/bandwidth estimator/analyser tools bundled with the backend tool
packages (e.g. "timing verifier") will give you a reasonably reliable estimate
of timing margin, etc.  With asynchronous design, the timing verifiers are useless.

Part of the design "problem" is verifying that your design will work at the target
frequency, with the specified speed grade device.  If you cannot assure yourself
(or the production folks) that your design is reliable at XX MHz, then you
(as a designer) have a problem!

So... synchronous design is safe, AND it is more verifiable with the readily
available tools.  If you ever have to support someone else's design (or vice
versa), this is a *really* important consideration.

-- Bob Elkind, eteam@aracnet.com

Peter Alfke wrote:
> 
> "Yu, Wenjiang [BVW:KCK2:EXCH]" wrote:
> 
> > Hi,
> >
> > Is there any one who would like give some ideas about my questions?
> >
> > 1. What are the advantage and disadvantage of using multiple clocks in
> >    FPGA design?
> 
> In most cases, the number of different clocks is dictated by the systems design.
> 
> The only advantage of multiple clocks inside a chip is that it might reduce
> clock power consumption under particular circumstances. Otherwise it is
> undesirable because it causes metastability issues whenever data has to cross
> clock boundaries.
> 
> >
> >
> > 2. What are the advantage and disadvantage of using asynchronous logic
> >    in a FPGA design?
> 
> Asynchronous designs can be faster and sometimes even smaller, but they require
> very careful worst-case analysis, and should only be used by experienced
> designers. Synchronous may be slower, but is generally much safer.
> 
> Peter Alfke, Xilinx Applications

Article: 30633
Subject: Chief Technical Engineer Position, Maryland
From: rk <stellare@nospamplease.erols.com>
Date: Fri, 20 Apr 2001 00:01:45 -0400
Links: << >>  << T >>  << A >>
Hi,

I ran into this on the Internet and thought someone here might be
interested.

-- 
rk                               We had dodged bullets before, but
stellar engineering, ltd.        this time we caught one in midair and
stellare@erols.com.NOSPAM        spit it out.
Hi-Rel Digital Systems Design    -- Gene Kranz after Apollo 5

=============================================================================

http://www.usajobs.opm.gov/wfjic/jobs/IT0564.HTM

Vacancy Announcement Number:
01-480-LM                                        
Closing Date: 
04/25/2001                                                     
                                                                                      
Position:  ELECTRONICS ENGINEER - INSTRUMENTATION
SYSTEMS                     
Salary: $87864 per year - $114224 per
year                                    
Duty Location: 1 vacancy at GREENBELT,
MD                                     

Open to all qualified
persons.                                                
                                                                                      
Major Duties:  As an Aerospace Technologist (AST)/Chief Technical
Engineer    
serves as an authority and expert to management within and outside NASA
in the
field of spaceflight microelectronics.  Evaluates the effects of
technological
changes on Very Large Scale Integration (VLSI) devices and on
current         
approaches with regard to microelectronics design, development, and
testing   
processes.  Utilizes state-of-the-art Computer Aided Design and
Engineering   
tools for design, simulation, synthesis, and analysis of VLSI
devices;        
evaluates and implements new tools as technology evolves.  Reviews
analyses of
spaceflight microelectronics conducted by others, evaluates their
technical   
value, and recommends appropriate courses of action.  Prepares and
implements 
training plans, mentors new engineers, and ensures that
microelectronics      
design engineers are equipped with the latest tools and processes to do
their 
work.

-- end excerpt

Article: 30634
Subject: Re: wanted: dig. board with FPGA and processor
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Fri, 20 Apr 2001 00:09:25 -0400
Links: << >>  << T >>  << A >>
Steven Sanders wrote:
> 
> Hello masters of the digital universe!
> 
> I`m looking for a development board with following specs:
> 
> 1) FPGA: Xilinx Virtex100 and beyond
> 2) processor:   Speed: min. 40MHz
>                 ROM: the bigger the better
>                 RAM: min. 2Mbit
>                 Tools: ANSI C compiler
> 3) if possible: ethernet controller (only PHY needed)
> 
> Thanx in advance!
> 
> Steven

Steven,

Arius, Inc has a board that comes pretty close to meeting your
requirements. It is a DSP board which uses a Lucent FPGA as the board
controller. The processor is a TI DSP chip, TMS320C31 running at up to
80 MHz. The board has 256K x 32 single cycle SRAM and 2 MByte of 16 bit
flash. The main FPGA is either a OR3T30 or an OR3T55. There are also
three other OR2T04A devices which are used to interface to optional IO
modules such as an Ethernet MAC/PHY. Although we are considering
building an Ethernet interface, we do not have an Ethernet module
available at this time. 

If you are interested, please contact me or check out our web pages at
http://www.arius.com/pc104c31.html


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 30635
Subject: Re: small, fast, w/ PECL?
From: William Lenihan <lenihan3we@earthlink.net>
Date: Fri, 20 Apr 2001 05:15:13 GMT
Links: << >>  << T >>  << A >>
Results:

The clock frequency and board space got increased, so I'm abandoning any PLD
solution and going with ECLiPS MSI logic. Had it stayed at 200 Mhz, I'd
replace the 95108 CPLD for slow-speed logic, and gone w/ a Virtex-E for both
slow speed and high speed PECL, which could run at 275 Mhz for the function
I wanted, easy. Hate going with MSI in this day & age, but it's the right
tool for the job (I don't want to fall into the category of "To every
hammer, all problems look like nails.").



"Geoffrey G. Rochat" wrote:

> >> Any suggestions for an FPGA or CPLD that can do the following?
> >>
> >> slow I/O: 10 Mhz TTL/LVTTL inputs (4), clock (1), and outputs(18).
> >> fast I/O: 200 Mhz PECL clock (1) producing 100 Mhz output (1). [I
> want
> >> plenty of margin on this, not just squeeking by at 200 Mhz.]
> >>
> >> Basically, a small PLD that can do fast PECL as well as traditional
> >> slower TTL.
> >>
> >> Any ideas?
> >
> >Do you also need PECL output?
> >I am experimenting with PECL input to Spartan-II FPGA by configuring
> the
> >input as GTL and using a higher VREF.
> >I have no results yet, but it should work.
> >
> >There are also affordable CMOS level clock synthesizers available at
> 200
> >MHz.
>
> Here's something you might try if you to want your non-LVPECL 3.3V PLD
> to drive LVPECL without having to go through level converter chips.
> IIRC, LVPECL inputs can swing from ground to a diode drop below the 3.3V
> rail.  Start with a non-LVPECL 3.3V PLD, such as something in the
> Lattice 5K-series, Altera 7K-series, Xilinx CoolRunner, etc. - whatever
> is fast enough and properly sized to your needs.  Make the non-LVPECL
> output of your PLD open-drain and connect it to your LVPECL load along
> with the following odd pullup:  Take a silicon diode and attach its
> anode to the 3.3V rail.  From its cathode add a resistor (330 Ohms or so
> as a guess) paralleled by a 0.1uF bypass cap to ground.  Call the
> cathode side of the diode V_HIGH.  The resistor to ground makes sure the
> diode is always on, and the cap minimizes noise on V_HIGH by making
> V_HIGH appear to be a low-impedance source at your clocking frequency.
> Add a resistor of the characteristic impedance of the LVPECL signal line
> you're dealing with (to minimize ringing and reflections) from V_HIGH to
> your LVPECL load.  With this setup your non-LVPECL PLD, along with the
> odd pullup, will drive the LVPECL load within "legal" bounds, although
> those bounds will be outside the normal LVPECL operating range on the
> low side.  The devil is in the details, of course, and it would be
> interesting to see if this odd passive pullup is sufficient to work at
> the speed you have in mind.  A further refinement might be to cut the
> voltage swing seen at the LVPECL load by adding a series resistor
> between the PLD open-drain output and the LVPECL load, and putting the
> odd pullup at the LVPECL load side of the series resistor.  This way the
> diode sets the high LVPECL voltage, and the resistor divider made up of
> the resistor from V_HIGH to the LVPECL load and the series resistor sets
> the low LVPECL voltage.  Some experimentation is called for.
>
> You might want to grab Motorola Application Notes AN1404, AN1406 and
> AN1672 off the On Semiconductor (formerly a division of Mot.,
> www.onsemi.com ) website for interesting thoughts on PECL.
>
> As for getting an LVPECL clock into your non-LVPECL PLD..., well, no
> clever ideas come to mind.  It may be that the output swing of an LVPECL
> gate with a resistor to ground is sufficient to clock a non-LVPECL PLD,
> but that is "an exercise left for the reader."  <grin>  On Semiconductor
> recommends you use their MC100EPT21 chip, or some other member of that
> family.
>
> Good luck and please e-mail or post your results, whatever you end up
> doing.

--
==============================
William Lenihan
lenihan3weNOSPAM@earthlink.net
.... remove "NOSPAM" when replying
==============================



Article: 30636
Subject: Re: Wanted: ISA bus implementation for Xilinx
From: "Victor Schutte" <victors@mweb.co.za>
Date: Fri, 20 Apr 2001 08:41:51 +0200
Links: << >>  << T >>  << A >>
I agree that it is a simple design. Most of my earlier designs use to fit on
one or two 10 cell Lattice 22V10 GALs and a 74LS245(or 2) for the data
lines. The price of CPLDs have dropped over the last few years so it might
me cheaper to do it in one IC.

The only problem I see with such a design is that it will become redundant
pretty soon.  My newest motherboard came out without any ISA connectors. The
only places I see ISA to survive in the next couple of years will be PC104
and AT96 systems.



"luigi funes" <fuzzy8888@hotmail.com> wrote in message
news:Y9yD6.52130$s93.4618412@news.infostrada.it...
>
> Ernst Rattenhuber ha scritto nel messaggio
> <4C01A18846D8F834.C53AD3E6B1E5410F.A773BB20C2D12EDB@lp.airnews.net>...
> >I need some kind of IP module that implements an ISA bus interface. It
> could be
> >in the form of a "black box" or in the form of synthesizable VHDL code. I
> >believe Xilinx used to have something along those lines, but it seems to
> have
> >been discontinued. Now they only offer a "PCI Development Kit" for the
PCI
> bus,
> >and it's rather expensive too (~9000 US dollars).
> >
> >My needs are not so great in terms of performance, and I'm not prepared
to
> fork
> >out that kind of money. So if someone could suggest an ISA solution that
> could
> >be purchased for 1000 dollars or less, I'd be grateful.
> >
> >I need it for the design of a PC/104 board that is to be the interface
> between
> >measurement devices and an embedded PC. The measurement devices use a
> >proprietary, synchronous serial protocol. I'm planning to implement the
> whole
> >thing in a single FPGA, preferably a Spartan-II device.
> >
> >TIA,
> >
> >Ernst Rattenhuber
> >
> >
> >P.S. Email replies can be sent to the address in my header minus the
> obvious
> >spam deterrent parts.
> >
>
> Ernst,
> I think you don't need really to buy a IP module for your purpose.
> The ISA bus is very easy to interface. I did a complete 16 bit interface
> with a 44 pins, 32 cells CPLD.
> You have only to decode the addresses, the memory R/W and the IO R/W
> signals and buffering the data bus (8 or 16 bits).
> The interrupt also is easy to handle. Perhaps the DMA transfer mode is
> more complex, I never used it because it seems me to have no benefits
> with a CPU > 386.
> If you miss the ISA bus specifications, you can find easily on the web,
for
> example in http://www.epanorama.net
>
> Luigi
>
>
>
>
>



Article: 30637
Subject: Re: wanted: dig. board with FPGA and processor
From: "Dziadek" <dziales@poczta.onet.pl>
Date: Fri, 20 Apr 2001 08:46:52 +0200
Links: << >>  << T >>  << A >>

Steven Sanders wrote in message <3ADE9CD1.F503EDCF@imec.be>...
>Hello masters of the digital universe!
>
>I`m looking for a development board with following specs:
>
>1) FPGA: Xilinx Virtex100 and beyond
>2) processor: Speed: min. 40MHz
> ROM: the bigger the better
> RAM: min. 2Mbit
> Tools: ANSI C compiler
>3) if possible: ethernet controller (only PHY needed)
>
>Thanx in advance!
>
>Steven

Have a look at www.techmil.com.pl
The SPP board includes 1 or 2 ADSP21160 and one XCV400 .. XCV1000.
Now prototype, available Q4.

Dziadek




Article: 30638
Subject: Re: Voltage supply reduction for low power in FPGAs.
From: "Victor Schutte" <victors@mweb.co.za>
Date: Fri, 20 Apr 2001 08:49:47 +0200
Links: << >>  << T >>  << A >>
You can stop the clock, drop Vccint by 5%(or minimum spec.) and try and cut
Vccio, but what will you gain?  Altera's CPLD has a TurboBit to halve the
speed and power. I don't know if that exists for the FPGAs.

Must the FPGA still be operational? Sleep mode?




"Austin Lesea" <austin.lesea@xilinx.com> wrote in message
news:3ADF0C40.6FDDBD93@xilinx.com...
> Steven,
>
> If you lower the voltage to the FPGA, it will either trip the power on
reset
> theshold voltage, and start over, or it will just slow down until it trips
> and resets.
>
> You can always choose to operate anywhere inside the recommended operating
> conditions limits, and expect the device to perform to specifications.
>
> You may also operate anywhere inside the absolute maximum ratings and
expect
> thge device to function, but it may not meet timing, or some other
> specification.
>
> The smaller Spartan II devices XC2S15 and XC2S30 parts are measuring
around
> 20 mA for turning on at room temperature, typical, and the quiescent
current
> is a little less (2.5 V Vccint, 3.3 V Vcco's).  We will have much better
> data once we see some process corners.
>
> Virtex II 2V40 is at about 24 mA to turn on, and about 8 mA in the power
> down mode at room temperature, typical (1.5 V Vccint, 3.3 V Vcco's).
>
> What do you feel is "low" power?
>
> Austin
>
> Steven Derrien wrote:
>
> > Hi,
> >
> > As most people familiar with low power designs already know, there exist
> > a
> > technique based on voltage supply reduction for  ASICS which allow
> > (at the price of increased logic and routing delays) to reduce the
> > overall circuit power dissipation.
> >
> > I was wondering if these thechniques could be applied to modern FPGAs
> > such a SPARTANII or Virtex ? Does anyone knows about this ?
> >
> > Thanks
> >
> > Steven
>



Article: 30639
Subject: Re: PAR single pass vs multi-pass differences
From: Allan Herriman <allan_herriman.hates.spam@agilent.com>
Date: Fri, 20 Apr 2001 20:02:22 +1000
Links: << >>  << T >>  << A >>
Utku Ozcan wrote:
> 
> > I have run 2 SPPRs on the same computer.  This resulted in identical
> > download files, so I can rule out transient computer problems.
> >
> > I have also run an additional SPPR on a different computer, with the
> > same EDIF and command line arguments.
> > It produced a result that was different to both the SPPR and MPPR
> > results from the first computer.
> > It also worked ok in the lab, whereas the SPPR download from the first
> > computer had functional problems.
> >
> > This implied to me that the installation of the Xilinx programs had been
> > corrupted on one of the computers, so I compared all the executable
> > files and speed files, etc. on the two computers, and they were
> > identical.
> >
> > So why should two computers produce different results if they are
> > running identical programs with identical input?
> > I don't think that PAR uses the machine ID to seed the random number
> > generator.
> > I might have missed comparing one of the files though, or it could be a
> > difference in a system DLL.
> 
> Very tight observation, thank you very much for your comments.
> 
> Then machine time might be different? Maybe tools use machine time for
> seed to obtain "random" behavior.

I don't think that applies here, as I did two routes (at different
times!) on the same machine and got results that were identical.

> Ok, you are using PC, probably it is
> similar under UNIX. Well, anyway, these things will be unanswered questions
> for a while then!

Our local Xilinx rep said that this seems to be a bug that they've
already identified, and it'll be fixed in service pack 8.
I couldn't find it in the Answers database though.

Regards,
Allan.

Article: 30640
Subject: Free timing diagram editor
From: "Chaffey, Paul" <paul_chaffey@yahoo.com>
Date: 20 Apr 2001 03:35:46 -0800
Links: << >>  << T >>  << A >>

Hi all,

TimingTool has been launched - Visit http://www.timingtool.com

TimingTool allows engineers to graphically edit timing diagrams and then
save the diagram in TDML format. The saved TDML can then be translated
into verilog / VHDL. This is all free of charge !!

For Best results use Internet Explorer 5.5 or Netscape 6.

Regards,
Paul Chaffey

Article: 30641
Subject: FREE SDRAM-controller core
From: "jeung joon ee" <cmosexod@ix.netcom.com>
Date: Fri, 20 Apr 2001 08:23:14 -0400
Links: << >>  << T >>  << A >>
Free SDRAM-Controller core, free UART core, and more at www.cmosexod.com
(not inappropriate).

Also, for only $50 get a CPLD development board called Post-It.   It is the
best FIFTY bucks you've ever spent.





Article: 30642
Subject: Re: FPGAs & Combinatorial Chew
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Fri, 20 Apr 2001 09:40:31 -0400
Links: << >>  << T >>  << A >>
V R wrote:
> 
> Hello.
> 
> I am working on a project that targets an Altera 10K10LC84-4. My design
> consists of a many simple blocks; each block has three 8-bit registers
> which drive the D-inputs of three 8-bit counters. Also in the small block
> is a 2x4 decoder that drives enables for each 8-bit register. So the block
> =~ three 8-bit counters + three 8-bit registers + one 2x4 decoder.
> 
> When I compiled my sub-block for an Altera CPLD, it ate 50 LCELLs. When
> this same design was targeted for the above stated FPGA, 80 LCELLs were
> eaten. After looking at the synthesis + P&R results from Max+Plus II, I
> saw that each gate(AND2, OR2, etc) of the decoder structure chewed up one
> LCELL each, thus accounting for more LCELLs.
> 
> The bad part is that this sub-block was replicated 6 times in a higher
> level design -- that means what would have chewed up 300 LCELLs in a CPLD
> took up 480 LCELLs in the 10K10. The reality is that the 10K10 has 576
> LCELLs, so my part was pretty full with a relatively "simple" design.
> 
> The question is then what techniques can I use to avoid the penalty of a
> simple 2x4 decoder/basic asynchronous logic(eating LCELLs)? Should I
> instantiate a ROM or a LUT and load my 2x4 data there? The 10K10 has three
> EABs which each have 2048 bits of RAM, should I make use of these?
> 
> I would like to try this design in a Xilinx part too, but I did my design
> in Altera schematics, so I doubt without a lot of effort I could make a
> similar comparison(i.e. schematics to EDIF, etc). Yes, I do know VHDL, but
> my development time for this was relatively small compared to what it
> would have taken with(me) VHDL so(please no VHDL would have been better
> comments)...
> 
> Thanks!
> VR.

If I understand your design, you are have three similar blocks, each
using an 8 bit counter which is loaded from an 8 bit register. Each
block also has a 2 input, 4 output decoder. Is that right?

It is not likely that the decoder is taking more than 4 LUTs in your
design. A decoder uses a single N input AND gate for each output. So
your dedoder should be using 4 LUTs in nearly any technology. However,
there are some quirks with counters in the Altera 10K family. I checked
the data sheet and they do support a loadable counter mode, but this
will only work if you are counting by 1. If you are counting by any
larger increment, it is likely that you are getting an extra LUT per
bit. Could this be what you are seeing in the P&R results? 

I have not worked with schematic entry for Altera parts, but if you
would like me to take a further look, perhaps you could send me PDF
files of your schematics? 

If you do want to take the time to implement this design in a Xilinx
FPGA, you will likely find that you don't have the same problem. The
Xilinx parts do a little bit better job with counters and adders. Or if
you want to do this in VHDL, I may be able to help you.


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 30643
Subject: XSV boards memory addressing
From: "M.S.Gaur" <msg00r@ecs.soton.ac.uk>
Date: Fri, 20 Apr 2001 16:28:49 +0100
Links: << >>  << T >>  << A >>
Hi,
Can somebody may please tell me how to increase the word length of the
two memory banks provided on the xsv board i.e. using 32 bit word in
place of 16 bit word.
2. How to access both the banks (512 K words left and right) of this
board ?
Regards
Gaur



Article: 30644
Subject: what does it mean in fe.log?
From: Jun <junciu@yahoo.com>
Date: Fri, 20 Apr 2001 07:53:23 -0800
Links: << >>  << T >>  << A >>
Hi

I have tried to implement a
schematic in Xilinx Foundation 3.li
My target frequency is 50Mhz, when
the software finishes implementation,
the log file fe.log says
Maxium frequency is 10.5 Mhz

What does it mean? Does it mean that
the maxium frequency of this bit file
after downloading to FPGA could only
be 10.5Mhz?

Thanks a lot!

Article: 30645
Subject: Re: Wanted: ISA bus implementation for Xilinx
From: ernstegon.NO@SPAM.freeze.com (Ernst Rattenhuber)
Date: 20 Apr 2001 17:02:59 GMT
Links: << >>  << T >>  << A >>
In article <3ADE9C69.AA9F1A1B@sqf.hp.com>, nials@sqf.hp.com says...
>
>Ernst Rattenhuber wrote:
>> 
>> I need some kind of IP module that implements an ISA bus interface. It could 
be
>> in the form of a "black box" or in the form of synthesizable VHDL code. I
>> believe Xilinx used to have something along those lines, but it seems to 
have
>> been discontinued. Now they only offer a "PCI Development Kit" for the PCI 
bus,
>> and it's rather expensive too (~9000 US dollars).
>> 
>> My needs are not so great in terms of performance, and I'm not prepared to 
fork
>> out that kind of money. So if someone could suggest an ISA solution that 
could
>> be purchased for 1000 dollars or less, I'd be grateful.
>> 
>> I need it for the design of a PC/104 board that is to be the interface 
between
>> measurement devices and an embedded PC. The measurement devices use a
>> proprietary, synchronous serial protocol. I'm planning to implement the 
whole
>> thing in a single FPGA, preferably a Spartan-II device.
>> 
>> TIA,
>> 
>> Ernst Rattenhuber
>
>
>Ernst,
>
>The ISA bus is very simple, you could probably implement one yourself
>in a couple of days. It'd probably take as long to understand the operation
>of any IP you can get hold of.
>
>As far as I know it's _VERY_ slow, so you've no tight timing 
>reuirements (like the PCI bus) to worry about.
>
>Nial.


Thanks, Nial. I guess you're probably right. I'll look into the ISA bus 
specification (if I can get hold of it; it seems the IEEE specification has 
been withdrawn).

Ernst Rattenhuber


Article: 30646
Subject: Re: clocking on both edges
From: gah@ugcs.caltech.edu (glen herrmannsfeldt)
Date: 20 Apr 2001 18:43:40 GMT
Links: << >>  << T >>  << A >>
"Hans Summers" <HansSummers@HotMail.Com> writes:

>"Peter Alfke" <palfke@earthlink.net> wrote in message
>>
>> Incoming clock drives XOR gate, output of XOR is double-frequency
>> output signal.
>> XOR output also clocks flip-flop. Flip-flop Q drives inverter.
>> Inverter output drives flip-flop D, and also the other input to the
>> XOR.
>>
>I see how this works.

>To double a clock pulse I have previously used a similar circuit where a
>74LS86 (Quad XOR gate) was clocked at 5.333MHz. (snip)

The neat thing about Peter's circuit is that the pulse is guaranteed to
be long enough to clock a FF, independent of almost anything else.
There is the assumption that all FF's clock with the same pulse width,
which should be pretty good on a single IC.  It has one inverter and
one XOR gate delay more than a CLK-Q flip-flop delay.  

One should be sure that the inverter delay is longer than the hold time
of the FF (well, the FF delay count, too).  I still remember the 7474
with a non-zero hold time, and 74LS74 with 0 hold time.

-- glen

Article: 30647
Subject: Who make Xilinx Proto PCBs ? Spartan II on PCI bus.
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Fri, 20 Apr 2001 19:55:43 GMT
Links: << >>  << T >>  << A >>
Hi ,

I need a Spartan II on a PCI bus.

Who manufactures such boards ?

Sincerely
Daniel DeConinck
High Res Technologies, Inc.





Article: 30648
Subject: What is a FPGA ?
From: Dirk Munk <munk@home.nl>
Date: Fri, 20 Apr 2001 20:27:10 GMT
Links: << >>  << T >>  << A >>
Hi,

In a computer system that was used as a software RIP (EFI Fiery) to
drive a very big XEROX printer, we found a "mxv convertor board" with a
Altera Flex  epf10k20rc208-4  chip.

We already found out that it is a FPGA chip, but we have no idea what a
FPGA chip is suppose to do.

Would someone please be so kind to enlighten us ?

regards,

Dirk


Article: 30649
Subject: Re: What is a FPGA ?
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Fri, 20 Apr 2001 14:04:36 -0700
Links: << >>  << T >>  << A >>
FPGA stands for Field Programmable Gate Array, so it is a logic circuit where
the user, not the manufacturer, has defined the logic content.
That means in your case, the chip manufacturer (Altera in this case) has no idea
what this circuit really does. You have to ask the board manufacturer.

Peter Alfke, Xilinx Applications
======================
Dirk Munk wrote:

> Hi,
>
> In a computer system that was used as a software RIP (EFI Fiery) to
> drive a very big XEROX printer, we found a "mxv convertor board" with a
> Altera Flex  epf10k20rc208-4  chip.
>
> We already found out that it is a FPGA chip, but we have no idea what a
> FPGA chip is suppose to do.
>
> Would someone please be so kind to enlighten us ?
>
> regards,
>
> Dirk




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