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Messages from 30700

Article: 30700
Subject: Re: Something about the counter
From: "Richard D. Mohlere" <rmohlere@knology.net>
Date: Tue, 24 Apr 2001 12:16:08 -0800
Links: << >>  << T >>  << A >>
I need a good divide-by circuit to scale down clocks.  Is there a good general purpose design in the Core generator?  Or should I just use a down counter and preload to achieve my divide-by function?

Article: 30701
Subject: SPARTAN vs VERTEX
From: Shawki Areibi <sareibi@uoguelph.ca>
Date: Tue, 24 Apr 2001 17:51:30 -0400
Links: << >>  << T >>  << A >>
hi, I was just wondering if someone could tell me the MAIN differences
between
the XILINX Spartan and Vertex FPGAs, and is there an article out there
(pdf)
that will give me some insight about these products (basically the main
advantages
and disadvantages of each product)
Hope to hear from you soon
You can reach me at sareibi@uoguelph.ca
Shawki

--
Shawki Areibi
Assistant Professor
School of Engineering
University of Guelph
Guelph, Ont, Canada N1G 2W1
Tel: (519) 824-4120
Fax: (519) 836-0227



Article: 30702
Subject: Re: what does it mean in fe.log?
From: "Helen Long" <madisonfff@usa.net>
Date: Tue, 24 Apr 2001 19:30:03 -0500
Links: << >>  << T >>  << A >>
Hi

Thank you for your suggestion, here is my PAR report
However I did not have many ideas about the maxium frequency of my design,
could you give me a favor?
Thanks a lot!

----------------------------------------------------------------------------
----


Release 3.3.06i - Par D.25

Wed Apr 18 22:42:44 2001

par -w -ol 2 -d 0 map.ncd pwmreg.ncd pwmreg.pcf


Constraints file: pwmreg.pcf

Loading design for application par from file map.ncd.
   "pwmreg" is an NCD, version 2.35, device xcs40, package pq240, speed -4
Loading device for application par from file '4020e.nph' in environment
G:/WIN32/Xilinx1.
Device speed data version:  x1_0.14.2.2 1.7 PRELIMINARY.


Resolved that IOB <$Net00121_> must be placed at site P173.
Resolved that IOB <$Net00122_> must be placed at site P172.
Resolved that IOB <$Net00123_> must be placed at site P171.
Resolved that IOB <$Net00124_> must be placed at site P167.
Resolved that IOB <$Net00125_> must be placed at site P165.
Resolved that IOB <$Net00126_> must be placed at site P164.
Resolved that IOB <$Net00127_> must be placed at site P160.
Resolved that IOB <$Net00128_> must be placed at site P157.
Resolved that IOB <$Net00129_> must be placed at site P156.
Resolved that IOB <$Net00130_> must be placed at site P154.
Resolved that IOB <$Net00131_> must be placed at site P148.
Resolved that IOB <$Net00132_> must be placed at site P147.
Resolved that IOB <$Net00133_> must be placed at site P145.
Resolved that IOB <$Net00134_> must be placed at site P144.
Resolved that IOB <$Net00135_> must be placed at site P139.
Resolved that IOB <$Net00136_> must be placed at site P138.
Resolved that IOB <$Net00137_> must be placed at site P136.
Resolved that IOB <$Net00138_> must be placed at site P134.
Resolved that IOB <$Net00139_> must be placed at site P133.
Resolved that IOB <$Net00140_> must be placed at site P131.
Resolved that IOB <$Net00141_> must be placed at site P130.
Resolved that IOB <$Net00142_> must be placed at site P126.
Resolved that IOB <$Net00143_> must be placed at site P125.
Resolved that IOB <$Net00144_> must be placed at site P152.
Resolved that IOB <A0> must be placed at site P88.
Resolved that IOB <A1> must be placed at site P87.
Resolved that IOB <A18> must be placed at site P46.
Resolved that IOB <A2> must be placed at site P86.
Resolved that IOB <A3> must be placed at site P85.
Resolved that IOB <CLEAR> must be placed at site P214.
Resolved that CLKIOB <CLK> must be placed at site P2.
Resolved that IOB <MEMORYRW> must be placed at site P185.
Resolved that IOB <PWM0> must be placed at site P210.
Resolved that IOB <PWM1> must be placed at site P213.
Resolved that IOB <RESET> must be placed at site P215.
Resolved that CLKIOB <STRB> must be placed at site P63.
Resolved that PRI-CLK <$I138> must be placed at site BUFGP_BL.


Device utilization summary:

   Number of External IOBs            36 out of 224    18%
      Flops:                           0
      Latches:                         0
   Number of IOBs driving Global Buffers    2 out of 8      25%

   Number of CLBs                    174 out of 784    22%
      Total CLB Flops:                98 out of 1568    6%
      4 input LUTs:                  309 out of 1568   19%
      3 input LUTs:                   53 out of 784     6%

   Number of PRI-CLKs                  2 out of 4      50%



Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)

Starting initial Placement phase.  REAL time: 4 secs
Finished initial Placement phase.  REAL time: 4 secs

Starting Constructive Placer.  REAL time: 4 secs
Placer score = 334424
Placer score = 295052
Placer score = 262168
Placer score = 245848
Placer score = 228570
Placer score = 212766
Placer score = 205120
Placer score = 189618
Placer score = 186176
Placer score = 184176
Placer score = 172028
Placer score = 169396
Placer score = 158138
Placer score = 153812
Placer score = 147768
Placer score = 144120
Placer score = 134384
Placer score = 131956
Placer score = 130396
Placer score = 129464
Placer score = 128308
Placer score = 127392
Placer score = 125076
Placer score = 122862
Placer score = 121756
Placer score = 121514
Placer score = 121154
Placer score = 120678
Placer score = 120380
Placer score = 119898
Finished Constructive Placer.  REAL time: 23 secs

Dumping design to file pwmreg.ncd.

Starting Optimizing Placer.  REAL time: 23 secs
Optimizing
Swapped 2 comps.
Xilinx Placer [1]   119354   REAL time: 25 secs

Finished Optimizing Placer.  REAL time: 25 secs

Dumping design to file pwmreg.ncd.

Total REAL time to Placer completion: 26 secs
Total CPU time to Placer completion: 24 secs

0 connection(s) routed; 1208 unrouted active, 4 unrouted PWR/GND.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 27 secs
Starting iterative routing.
Routing active signals.
End of iteration 1
1208 successful; 0 unrouted active,
   4 unrouted PWR/GND; (0) REAL time: 29 secs
End of iteration 2
1208 successful; 0 unrouted active,
   4 unrouted PWR/GND; (0) REAL time: 29 secs
Constraints are met.
Routing PWR/GND nets.
Power and ground nets completely routed.
Dumping design to file pwmreg.ncd.
Starting cleanup
Improving routing.
End of cleanup iteration 1
1212 successful; 0 unrouted; (0) REAL time: 42 secs
Dumping design to file pwmreg.ncd.
Total REAL time: 42 secs
Total CPU  time: 40 secs
End of route.  1212 routed (100.00%); 0 unrouted.
No errors found.
Completely routed.

This design was run without timing constraints.  It is likely that much
better
circuit performance can be obtained by trying either or both of the
following:

  - Enabling the Delay Based Cleanup router pass, if not already enabled
  - Supplying timing constraints in the input design


Total REAL time to Router completion: 42 secs
Total CPU time to Router completion: 40 secs

Generating PAR statistics.

   The Delay Summary Report

   The Score for this design is: 627


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        3.896 ns
   The Maximum Pin Delay is:                              13.847 ns
   The Average Connection Delay on the 10 Worst Nets is:  11.872 ns

   Listing Pin Delays by value: (ns)

    d < 3.00   < d < 6.00  < d < 9.00  < d < 12.00  < d < 14.00  d >= 14.00
   ---------   ---------   ---------   ---------   ---------   ---------
         638         217         255          69          33           0

Dumping design to file pwmreg.ncd.


All signals are completely routed.

Total REAL time to PAR completion: 44 secs
Total CPU time to PAR completion: 41 secs

Placement: Completed - No errors found.
Routing: Completed - No errors found.

PAR done.

Utku Ozcan <ozcan@netas.com.tr> wrote in message
news:3AE2C63E.ADAAB5F1@netas.com.tr...
> Jun wrote:
>
> > Hi
> >
> > I have tried to implement a
> > schematic in Xilinx Foundation 3.li
> > My target frequency is 50Mhz, when
> > the software finishes implementation,
> > the log file fe.log says
> > Maxium frequency is 10.5 Mhz
> >
> > What does it mean? Does it mean that
> > the maxium frequency of this bit file
> > after downloading to FPGA could only
> > be 10.5Mhz?
> >
> > Thanks a lot!
>
> fe.log means Flow Engine log file. You will see all the contents in the
> Flow Engine window in this file. I think you are talking about static
> timing analysis tool TRCE's report, which is also in this fe.log.
> 10.5 MHz might not correspond your clock. It can belong to one of
> your TIMESPECs although your clock constraint is satisfied. STA report
> shows the frequency of the slowest timing constraint defined in UCF file.
> You must read your PAR report (*.par file), which in the same directory
> where fe.log is. It gives frequency values of all of your timing
constraints
> defined in your UCF file.
>
> Utku
>
>



Article: 30703
Subject: Re: Something about the counter
From: "Helen Long" <madisonfff@usa.net>
Date: Tue, 24 Apr 2001 19:35:11 -0500
Links: << >>  << T >>  << A >>
I have another question about it
I got the maxium clock frequency from the fe.log file,
There says that maxium frequency is **MHz
Does that mean the real maxium frequency is **Mhz?
I had an empty UCF file
Thanks a lot!

Richard D. Mohlere <rmohlere@knology.net> wrote in message
news:ee7032f.3@WebX.sUN8CHnE...
> I need a good divide-by circuit to scale down clocks.  Is there a good
general purpose design in the Core generator?  Or should I just use a down
counter and preload to achieve my divide-by function?



Article: 30704
Subject: Re: what does it mean in fe.log?
From: Chris Dunlap <chris.dunlap@xilinx.com>
Date: Tue, 24 Apr 2001 20:47:06 -0600
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------DD6AA607FABBABC3D0B890E2
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

In your case you do not have any timing constraints so PAR will not analyze
timing parameters.  If you run trace (Timing Analyzer) this will give you
maximum frequency but keep in mind this is maximum frequency between synchronous
elements.  If your delays coming into or off the chip are greater than the
delays between sychronous elements, this value will not be accurate.

fe.log is just an file which shows everything that is piped out to the screen in
normal run of the flow engine.

Chris

Helen Long wrote:

> Hi
>
> Thank you for your suggestion, here is my PAR report
> However I did not have many ideas about the maxium frequency of my design,
> could you give me a favor?
> Thanks a lot!
>
> ----------------------------------------------------------------------------
> ----
>
> Release 3.3.06i - Par D.25
>
> Wed Apr 18 22:42:44 2001
>
> par -w -ol 2 -d 0 map.ncd pwmreg.ncd pwmreg.pcf
>
> Constraints file: pwmreg.pcf
>
> Loading design for application par from file map.ncd.
>    "pwmreg" is an NCD, version 2.35, device xcs40, package pq240, speed -4
> Loading device for application par from file '4020e.nph' in environment
> G:/WIN32/Xilinx1.
> Device speed data version:  x1_0.14.2.2 1.7 PRELIMINARY.
>
> Resolved that IOB <$Net00121_> must be placed at site P173.
> Resolved that IOB <$Net00122_> must be placed at site P172.
> Resolved that IOB <$Net00123_> must be placed at site P171.
> Resolved that IOB <$Net00124_> must be placed at site P167.
> Resolved that IOB <$Net00125_> must be placed at site P165.
> Resolved that IOB <$Net00126_> must be placed at site P164.
> Resolved that IOB <$Net00127_> must be placed at site P160.
> Resolved that IOB <$Net00128_> must be placed at site P157.
> Resolved that IOB <$Net00129_> must be placed at site P156.
> Resolved that IOB <$Net00130_> must be placed at site P154.
> Resolved that IOB <$Net00131_> must be placed at site P148.
> Resolved that IOB <$Net00132_> must be placed at site P147.
> Resolved that IOB <$Net00133_> must be placed at site P145.
> Resolved that IOB <$Net00134_> must be placed at site P144.
> Resolved that IOB <$Net00135_> must be placed at site P139.
> Resolved that IOB <$Net00136_> must be placed at site P138.
> Resolved that IOB <$Net00137_> must be placed at site P136.
> Resolved that IOB <$Net00138_> must be placed at site P134.
> Resolved that IOB <$Net00139_> must be placed at site P133.
> Resolved that IOB <$Net00140_> must be placed at site P131.
> Resolved that IOB <$Net00141_> must be placed at site P130.
> Resolved that IOB <$Net00142_> must be placed at site P126.
> Resolved that IOB <$Net00143_> must be placed at site P125.
> Resolved that IOB <$Net00144_> must be placed at site P152.
> Resolved that IOB <A0> must be placed at site P88.
> Resolved that IOB <A1> must be placed at site P87.
> Resolved that IOB <A18> must be placed at site P46.
> Resolved that IOB <A2> must be placed at site P86.
> Resolved that IOB <A3> must be placed at site P85.
> Resolved that IOB <CLEAR> must be placed at site P214.
> Resolved that CLKIOB <CLK> must be placed at site P2.
> Resolved that IOB <MEMORYRW> must be placed at site P185.
> Resolved that IOB <PWM0> must be placed at site P210.
> Resolved that IOB <PWM1> must be placed at site P213.
> Resolved that IOB <RESET> must be placed at site P215.
> Resolved that CLKIOB <STRB> must be placed at site P63.
> Resolved that PRI-CLK <$I138> must be placed at site BUFGP_BL.
>
> Device utilization summary:
>
>    Number of External IOBs            36 out of 224    18%
>       Flops:                           0
>       Latches:                         0
>    Number of IOBs driving Global Buffers    2 out of 8      25%
>
>    Number of CLBs                    174 out of 784    22%
>       Total CLB Flops:                98 out of 1568    6%
>       4 input LUTs:                  309 out of 1568   19%
>       3 input LUTs:                   53 out of 784     6%
>
>    Number of PRI-CLKs                  2 out of 4      50%
>
> Overall effort level (-ol):   2 (set by user)
> Placer effort level (-pl):    2 (set by user)
> Placer cost table entry (-t): 1
> Router effort level (-rl):    2 (set by user)
>
> Starting initial Placement phase.  REAL time: 4 secs
> Finished initial Placement phase.  REAL time: 4 secs
>
> Starting Constructive Placer.  REAL time: 4 secs
> Placer score = 334424
> Placer score = 295052
> Placer score = 262168
> Placer score = 245848
> Placer score = 228570
> Placer score = 212766
> Placer score = 205120
> Placer score = 189618
> Placer score = 186176
> Placer score = 184176
> Placer score = 172028
> Placer score = 169396
> Placer score = 158138
> Placer score = 153812
> Placer score = 147768
> Placer score = 144120
> Placer score = 134384
> Placer score = 131956
> Placer score = 130396
> Placer score = 129464
> Placer score = 128308
> Placer score = 127392
> Placer score = 125076
> Placer score = 122862
> Placer score = 121756
> Placer score = 121514
> Placer score = 121154
> Placer score = 120678
> Placer score = 120380
> Placer score = 119898
> Finished Constructive Placer.  REAL time: 23 secs
>
> Dumping design to file pwmreg.ncd.
>
> Starting Optimizing Placer.  REAL time: 23 secs
> Optimizing
> Swapped 2 comps.
> Xilinx Placer [1]   119354   REAL time: 25 secs
>
> Finished Optimizing Placer.  REAL time: 25 secs
>
> Dumping design to file pwmreg.ncd.
>
> Total REAL time to Placer completion: 26 secs
> Total CPU time to Placer completion: 24 secs
>
> 0 connection(s) routed; 1208 unrouted active, 4 unrouted PWR/GND.
> Starting router resource preassignment
> Completed router resource preassignment. REAL time: 27 secs
> Starting iterative routing.
> Routing active signals.
> End of iteration 1
> 1208 successful; 0 unrouted active,
>    4 unrouted PWR/GND; (0) REAL time: 29 secs
> End of iteration 2
> 1208 successful; 0 unrouted active,
>    4 unrouted PWR/GND; (0) REAL time: 29 secs
> Constraints are met.
> Routing PWR/GND nets.
> Power and ground nets completely routed.
> Dumping design to file pwmreg.ncd.
> Starting cleanup
> Improving routing.
> End of cleanup iteration 1
> 1212 successful; 0 unrouted; (0) REAL time: 42 secs
> Dumping design to file pwmreg.ncd.
> Total REAL time: 42 secs
> Total CPU  time: 40 secs
> End of route.  1212 routed (100.00%); 0 unrouted.
> No errors found.
> Completely routed.
>
> This design was run without timing constraints.  It is likely that much
> better
> circuit performance can be obtained by trying either or both of the
> following:
>
>   - Enabling the Delay Based Cleanup router pass, if not already enabled
>   - Supplying timing constraints in the input design
>
> Total REAL time to Router completion: 42 secs
> Total CPU time to Router completion: 40 secs
>
> Generating PAR statistics.
>
>    The Delay Summary Report
>
>    The Score for this design is: 627
>
> The Number of signals not completely routed for this design is: 0
>
>    The Average Connection Delay for this design is:        3.896 ns
>    The Maximum Pin Delay is:                              13.847 ns
>    The Average Connection Delay on the 10 Worst Nets is:  11.872 ns
>
>    Listing Pin Delays by value: (ns)
>
>     d < 3.00   < d < 6.00  < d < 9.00  < d < 12.00  < d < 14.00  d >= 14.00
>    ---------   ---------   ---------   ---------   ---------   ---------
>          638         217         255          69          33           0
>
> Dumping design to file pwmreg.ncd.
>
> All signals are completely routed.
>
> Total REAL time to PAR completion: 44 secs
> Total CPU time to PAR completion: 41 secs
>
> Placement: Completed - No errors found.
> Routing: Completed - No errors found.
>
> PAR done.
>
> Utku Ozcan <ozcan@netas.com.tr> wrote in message
> news:3AE2C63E.ADAAB5F1@netas.com.tr...
> > Jun wrote:
> >
> > > Hi
> > >
> > > I have tried to implement a
> > > schematic in Xilinx Foundation 3.li
> > > My target frequency is 50Mhz, when
> > > the software finishes implementation,
> > > the log file fe.log says
> > > Maxium frequency is 10.5 Mhz
> > >
> > > What does it mean? Does it mean that
> > > the maxium frequency of this bit file
> > > after downloading to FPGA could only
> > > be 10.5Mhz?
> > >
> > > Thanks a lot!
> >
> > fe.log means Flow Engine log file. You will see all the contents in the
> > Flow Engine window in this file. I think you are talking about static
> > timing analysis tool TRCE's report, which is also in this fe.log.
> > 10.5 MHz might not correspond your clock. It can belong to one of
> > your TIMESPECs although your clock constraint is satisfied. STA report
> > shows the frequency of the slowest timing constraint defined in UCF file.
> > You must read your PAR report (*.par file), which in the same directory
> > where fe.log is. It gives frequency values of all of your timing
> constraints
> > defined in your UCF file.
> >
> > Utku
> >
> >

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adr;quoted-printable:;;12600 E Arapahoe Rd=0D=0ASuite C;Englewood;CO;80112;
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--------------DD6AA607FABBABC3D0B890E2--


Article: 30705
Subject: Re: Altera Mercury comments
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Wed, 25 Apr 2001 00:17:32 -0400
Links: << >>  << T >>  << A >>
Nial Stewart wrote:
> 
> martin.j.thompson@trw.com wrote:
> 
> > Also, anyone think we might get more response from Altera
> >  (and less from Xilinx?) is this ng was called comp.arch.pld :-)?
> 
> I've had private emails from Altera support answering questions I've
> asked on this newsgroup.
> 
> Apparently it's company policy not to post which I think is
> bloody ridiculous.
> 
> Nial.

I don't know that it is either good or bad. I talk with a lot of other
FPGA engineers and not many of them even read this newsgroup. So I don't
know that it really matters much if a company does or doesn't post here. 

Although I find this group very helpful and informative, I think that it
is not widely read. 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 30706
Subject: Failed to configure Spartan2
From: Ralf =?iso-8859-1?Q?Oberl=E4nder?= <ralf.oberlaender@emsys.de>
Date: Wed, 25 Apr 2001 13:14:09 +0200
Links: << >>  << T >>  << A >>
Dies ist eine mehrteilige Nachricht im MIME-Format.
--------------DDF3694DE9CF04E4AD69754B
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hi,

I'm wondering about that effect:
there exist designs that can configure my FPGA in slave serial mode. I
do some minor changes, create a new hex file for programming. The result
is, that I cann not configure the FPGA (The done-Pin remaines in the
Programming state). I changed only the design, not any script or control
file in the designflow. What happened ???

I'm completely helpless!

Can anybody help me


Ralf

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begin:vcard 
n:Oberländer;Ralf
tel;fax:++49 3677 6682-59
tel;work:++49 3677 6682-57
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email;internet:ralf.oberlaender@emsys.de
title:Dipl. Ing.
fn:Ralf Oberländer
end:vcard

--------------DDF3694DE9CF04E4AD69754B--


Article: 30707
Subject: Re: Failed to configure Spartan2
From: Wilhelm Heupke <wilhelm@heupke.com>
Date: Wed, 25 Apr 2001 14:00:19 +0200
Links: << >>  << T >>  << A >>


Ralf Oberländer schrieb:

> Hi,
>
> I'm wondering about that effect:
> there exist designs that can configure my FPGA in slave serial mode. I
> do some minor changes, create a new hex file for programming. The result
> is, that I cann not configure the FPGA (The done-Pin remaines in the
> Programming state). I changed only the design, not any script or control
> file in the designflow. What happened ???
>
> I'm completely helpless!
>
> Can anybody help me

Does this problem persist after cycling the power to the FPGA ?
I have seen the FPGA to "hang up" after e.g. static electricity problems
(small pulses).
You can not configure it anymore.
When I switch the power off and on again, everything is fine again.



Article: 30708
Subject: Pin A1 on Spartan2 chips
From: "Carsten Nöding" <carsten.noeding@uni-mainz.de>
Date: Wed, 25 Apr 2001 14:44:35 +0200
Links: << >>  << T >>  << A >>
Hi,

I've some Spartan2 chipe (XC2S150-5-FG456C) and I was wondering where the A1
pin is located. The BGA package has three "sloped" corners and a normal one
which has in addition a golden marking. I expect that A1 is located on this
corner but I 'd like to be absolutely sure... Unfortunately I haven't found
any information on the Xilinx homepage.

Cheers,
Carsten Noeding



Article: 30709
Subject: Accept credit cards online at only 9.1% service charge 8363
From: greg.polk@polkservices.net
Date: Wed, 25 Apr 2001 13:57:06 GMT
Links: << >>  << T >>  << A >>
Easy Pay CC          www.easypaycc.com
The Name Says It All

We provide SSL (Secure Sockets Layer) and other encryption security features that insure your online transactions are processed securely, safely and only once.   
Our competitors should be offering this kind of protection, and sometimes they do, for about two or three times the cost.  
That's where Easy Pay CC is totally different from the rest.  We never charge more than 9.5% on revenues charged during a one-week period.
We offer the LOWEST rates in comparison to our competitors and setup times are about 5 minutes  
Look, the idea was yours, you made the site, you made it successful, now shouldn't you be getting the money?



Article: 30710
Subject: Re: SPARTAN vs VERTEX
From: Les S Brodie <les_brodie@agilent.com>
Date: Wed, 25 Apr 2001 09:35:35 -0700
Links: << >>  << T >>  << A >>
 To start with go to the www.xilinx.com site and click products then click
devices.  There is tons of
more detailed info on this site.



Article: 30711
Subject: Re: SPARTAN vs VERTEX
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 25 Apr 2001 18:43:15 +0200
Links: << >>  << T >>  << A >>
Shawki Areibi schrieb:
> 
> hi, I was just wondering if someone could tell me the MAIN differences
> between
> the XILINX Spartan and Vertex FPGAs, and is there an article out there
> (pdf)

SPARTAN is just a little more improved 4000XL. Run up to 100 MHz and is
designed for ASIC replacement (price)

Virtex was AFAIK the new aera after the 4000 series. And runs up to
200MHz (VirtexE even higher)

SPARTAN 2 !!! is the low cost version of Virtex. Same speed, but smaller
devices (15k-200k gates) Also intendet as ASIC replacement.

-- 
MFG
Falk


Article: 30712
Subject: Re: Pin A1 on Spartan2 chips
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 25 Apr 2001 18:46:41 +0200
Links: << >>  << T >>  << A >>
Carsten Nöding schrieb:
> 
> Hi,
> 
> I've some Spartan2 chipe (XC2S150-5-FG456C) and I was wondering where the A1
> pin is located. The BGA package has three "sloped" corners and a normal one
> which has in addition a golden marking. I expect that A1 is located on this
> corner but I 'd like to be absolutely sure... Unfortunately I haven't found
> any information on the Xilinx homepage.

http://www.xilinx.com/partinfo/pkgs.htm


-- 
MFG
Falk

Article: 30713
Subject: Re: Any good sources for digital rf processing ?
From: Lukose Ninan <lukose@gte.net>
Date: Wed, 25 Apr 2001 17:49:54 GMT
Links: << >>  << T >>  << A >>
Hi Edward,

Two excellent books are
"Theory and Practise of Modem Design   .. by J.C Bingham'
See Chapter 6 for Costas Loop design considerations.

Also look at
"Digital Signal Processing " by Marvin Frerking
That has good descriptions on building  digital mixers, filters, ncos

Also it helps a lot (simpler logic ) if you can sample at 4x the symbol rate.
See page 137 of Frerkings book.

Hope that is helpful,

Lukose




Article: 30714
Subject: Re: Virtex-E HDL -- Possible to clock register directly from ibuf?
From: "Carsten Nöding" <carsten.noeding@uni-mainz.de>
Date: Wed, 25 Apr 2001 23:00:41 +0200
Links: << >>  << T >>  << A >>

"Matt Billenstein" <mbillens@mbillens.yi.org> wrote in message
news:uDOE6.18846$W67.2335278@typhoon.kc.rr.com...
> All,  I have one register in my design that is clocked by a signal not on
a
> GCLK pin...  Right now I run it through and IBUF, then a BUFG and then to
> the register, but it gets routed all over the place in doing this.  Is it
> possible to just run the signal from the IBUF to this one register?  The
> tools don't seem to like it, I get errors during translate saying the
signal
> has an illegal connection...
>
> I'm using foundation 3.1i sp7 and VHDL design entry.
>
> thx
>
> m
>
> --
>
> Matt Billenstein
> mbillens (at) one (dot) net
> http://w3.one.net/~mbillens/

Normally - although not prefered - you can use any signal to clock a
register. So it should work running the signal from the IBUF directly to the
corresponding register. Maybe you can you provide me with your VHDL code?

Carsten




Article: 30715
Subject: Re: Virtex-E & 5V tolerance
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 25 Apr 2001 22:42:57 +0100
Links: << >>  << T >>  << A >>


Austin Lesea wrote:
> 
> Rick,
> 
> The 100 ohms is there because the clamp diodes are left ON at all times to
> protect the output transistors.
> 
> Reducing the value forces more current into the Vcco through the forward
> biased clamp diodes, and may cause the device's Vcco to rise beyond the 3.3
> Vdc it is supposed to be at.
> 
> This assumes your 5 V drives actually drives to 5 V.  I would first look up
> the drive characteristic of the 5 V parts, and model them with their IBIS
> model (hopefully they are so old they don't have that problem).
> 
> Based on the 100 ohms and the voltage drop across it, you may safely reduce
> the 100 ohms if the current is less than the 10 mA that we are looking at in
> the "pull all the way to 5 Vdc" case.
> 
> Austin
> 
> 

Thanks Austin nice answer. Think I'll stick with Xilinx for a while
longer.

Now to go off & do some sums ....

Article: 30716
Subject: Re: SPARTAN vs VERTEX
From: Kolja Sulimma <kolja@prowokulta.org>
Date: Wed, 25 Apr 2001 23:56:33 +0200
Links: << >>  << T >>  << A >>

Shawki Areibi wrote:

> hi, I was just wondering if someone could tell me the MAIN differences
> between
> the XILINX Spartan and Vertex FPGAs, and is there an article out there
> (pdf)
> that will give me some insight about these products (basically the main
> advantages
> and disadvantages of each product)

(The following is a very simplified and rough discription. You should read
the datasheets and
request pricing quotes from a distributor before making a decision, for
example  www.nuhorizons.com)

Forget about Spartan and Virtex for new designs, they are too expensive per
gate count due to
old process technologies.

Spartan-2 and Virtex-E are essentially the same architechture but have
different characteristics with regard
to speed, size, price, supply voltage, IO options, etc.

Spartan is the small low cost version with up to about 4500 LUTs. You can
buy small  parts for less then $14 in small quantities..

Virtex-E offers up to about 70.000 LUTs and very high speed differential
I/O. One of the major drawbacks is that
5V PCI requires a resistor on each pin.

Kolja Sulimma




Article: 30717
Subject: Virtex-II LUT aspect ratio
From: brimdavis@aol.com (BriMDavis)
Date: 26 Apr 2001 02:01:24 GMT
Links: << >>  << T >>  << A >>
 A while back, Jan Gray noted on www.fpgacpu.org news:
>
>  The following table shows some representative Xilinx devices, 
> the device CLB matrix, the number of CLBs, the no. of 4-LUTS/CLB,
> the no. of 4-LUTs, the approximate no. of "ASIC equivalent gates"
> or "system gates" stated at the time those devices were brought 
> out, and the result of dividing stated gates by the number of 4-LUTs. 
>
>  Device   Matrix  CLBs LUTs/CLB 4-LUTs  Gates Gates/LUT
>  XC4010    20x20   400     2       800    10K    12.5
>  XC40150XV 72x72  5184     2     10368   150K    14.4
>  XCS20     20x20   400     2       800    20K    25.0
>  XCV1000   64x96  6514     4     24576 1.124M    45.7
>  XC2V1000  40x32  1280     8     10240     1M    97.6
>  XC2V2000  56x48  2688     8     21504     2M    93.0
>

  I've noticed that there besides there being far fewer 4-LUT's in a
given Virtex-II vs. Virtex part #, they are arranged much differently:
if you define the device "LUT aspect ratio" as the width/height of 
4-LUT's, you see a big change from the Virtex to the Virtex-II:

                                                             LUT
            CLB            LUT's/           LUT      LUT    aspect 
 Device    Matrix    CLBs  CLB    4-LUTs  arrang.   Matrix  ratio  
             HxW                            HxW      HxW     W/H
----------------------------------------------------------------------
 XC4010     20x20     400    2      800     2x1     40x20   0.500 (1:2)
 XC40150XV  72x72    5184    2    10368     2x1    144x72   0.500 (1:2)
                                                                
 XCS20      20x20     400    2      800     2x1     40x20   0.500 (1:2)
                                                                
 XCV50      16x24     384    4     1536     2x2     32x48   1.500 (3:2)
 XCV100     20x30     600    4     2400     2x2     40x60   1.500 (3:2)
 XCV300     32x48    1536    4     6144     2x2     64x96   1.500 (3:2)
 XCV600     48x72    3456    4    13824     2x2     96x144  1.500 (3:2)
 XCV1000    64x96    6144    4    24576     2x2    128x192  1.500 (3:2)
 XCV2000E   80x120   9600    4    38400     2x2    160x240  1.500 (3:2)
 XCV2600E   92x138  12696    4    50784     2x2    184x276  1.500 (3:2)
 XCV3200E  104x156  16224    4    64896     2x2    208x312  1.500 (3:2)

 XC2V40      8x8       64    8      512     4x2     32x16   0.500 (1:2)
 XC2V80     16x8      128    8     1024     4x2     64x16   0.250 (1:4)
 XC2V250    24x16     384    8     3072     4x2     96x32   0.333 (1:3)
 XC2V500    32x24     768    8     6144     4x2    128x48   0.375 (3:8)
 XC2V1000   40x32    1280    8    10240     4x2    160x64   0.400 (2:5)   
 XC2V2000   56x48    2688    8    21504     4x2    224x96   0.429 (3:7)
 XC2V3000   64x56    3584    8    28672     4x2    256x112  0.438 (7:16)
 XC2V4000   80x72    5760    8    46080     4x2    320x144  0.450 (9:20)

  Based on LUT arrangements, the XC4xxx based parts were all twice as 
tall as they are wide; the Virtex parts are all 50% wider than tall;
and the Virtex II parts vary, with the smallest parts being up to four 
times as tall as they are wide.

  When doing H/W DSP with these parts, I generally build heavily pipelined
datapaths, floorplanned and/or RLOC'd, that tend to sprawl horizontally 
across the chip in a fairly orderly fashion, with a height established by 
the carry chain height of the datapath in question.

  Ignoring control logic and scaling, a 32 bit, 48 stage, pipelined adder 
cascade would fit neatly across the smallest Virtex XCV50. If you tried 
the same design with the smallest Virtex-II, the XC2V40, you'd only fit 
16 stages across; in order to fit 48 neatly across the chip, you need to 
go up in size to an XC2V500, where the same design would then leave 3/4 
of the chip empty. Logic capacity-wise, the 48 adders would fit in an 
XC2V250, but the floorplan would need some of the datapath jogged 
vertically to fit.

  Comparing similarly sized parts, I'd generally prefer the organization 
of the XCV300 (6144 LUTs) at 64 bits tall, 96 stages deep, over the 
XC2V500 (also 6144 LUTs), at 128 bits tall and 48 stages deep.

  When relying on automatic placement, which tends to build designs with
"hairball" logic placement, this difference may not be as much of a concern.
    

Brian Davis


Article: 30718
Subject: MAPLD Conference - Call for Papers and Registration Open
From: "Richard B. Katz" <mapld2001@nospamplease.klabs.org>
Date: Wed, 25 Apr 2001 23:13:00 -0400
Links: << >>  << T >>  << A >>

                          Call for Papers

                2001 MAPLD International Conference
                     JHU/APL - Laurel, Maryland

                       September 11-13, 2001

Note new addresses: mapld2001@klabs.org
                    http://www.klabs.org

The 4th annual Military and Aerospace Applications of Programmable
Devices and Technologies International Conference will address devices,
technologies, usage, reliability, fault tolerance, radiation
susceptibility, and applications of programmable devices and adaptive
computing systems in military and aerospace systems. 

This year's Conference will also include papers and an emphasis on
CPU design (both traditional processors as well as those embedded
in ASICs/SoC and programmable devices), logic design, and device 
reliability.   

The program will consist of oral and poster technical presentations
and industrial exhibits.  This conference is open to US and foreign
participation and is unclassified.  Select papers will be published
in the AIAA Journal of Spacecraft and Rockets.

Two tutorials/seminars will be given:

   1. Programmable Logic Devices and Architectures
   2. Advanced Design: Designing for Reliability

Invited Speakers include:

   Arthur F. Obenshain, NASA Goddard Space Flight Center
   Director, Applied Engineering & Technology Directorate
   
   Lieutenant General Ronald T. Kadish, United States Air Force
   Director, Ballistic Missile Defense Organization
   
   Dr. Roger D. Launius, Chief Historian, NASA

   Dr. James E. Tomayko, Carnegie Mellon University

   Dr. David A. Bearden, The Aerospace Corporation

   Dr. Steve Guccione,   Xilinx Corporation

   Dr. Don Bouldin,      University of Tennessee

The conference is sponsored by: 

   NASA Goddard Space Flight Center
   JHU/Applied Physics Laboratory 
   National Security Agency
   Electronics Radiation Characterization Project 
   Digital Engineering Institute 
   Military & Aerospace Programmable Logic Users Group 
   American Institute of Aeronautics and Astronautics 
   IEEE Aerospace & Electronic Systems Society (AESS)
   Air Force Research Labs

For further information, please see the conference www home page at: 

   http://www.klabs.org/richcontent/MAPLDCon01/MAPLDCon01.html
   http://rk.gsfc.nasa.gov

Article: 30719
Subject: What is wrong with Xilinx Foundation Simulator?
From: Jeff <madisonfff@usa.net>
Date: Wed, 25 Apr 2001 20:08:52 -0800
Links: << >>  << T >>  << A >>
I run Xilinx Foundation 3.li functional simulation. Very strange thing happens.
I give a signal D
from menu waveform->Insert Formula
->wizard 
to give D high 10ns,
however after 10ns, D is supposed to
be in unknown state since I did not give any value to it,however when I go on with the simulation, D is still 1, it seems Xilinx go on with it, so strange! It is not that case before, I did not know whether there is some setup which cause this problem or not.
Thanks a lot for it!

Qian

Article: 30720
Subject: Virtex power supplies.
From: William Lenihan <lenihan3we@earthlink.net>
Date: Thu, 26 Apr 2001 06:37:58 GMT
Links: << >>  << T >>  << A >>

I've heard various concerns & comments raised about unusually large
power
supply currents before FPGA configuration is completed. What's the real
story on this issue ....

Are these current surges happening
    ____ during power-up (as Vcc's ramp up) ?
    ____ After Vcc ramp-up, but before configuration ?
    ____ during configuration ?

Are these current surges happening on core Vcc(s) or I/O Vcc(s) or both
?

Are these surge currents occuring with Virtex and/or Virtex-E and/or
Virtex-II parts ?


--
==============================
William Lenihan
lenihan3weNOSPAM@earthlink.net
.... remove "NOSPAM" when replying
==============================



Article: 30721
Subject: Re: What is wrong with Xilinx Foundation Simulator?
From: Ivar <ivar@stantech.dk>
Date: Wed, 25 Apr 2001 23:37:30 -0800
Links: << >>  << T >>  << A >>
Hi Jeff
If You open the Logic simulator and then open the Tools/ScriptEditor/Help/SimulationMacrosHelp there are some notes on the various script commands.
I think that You should try it and make a simulator script.

Article: 30722
Subject: VHDL coding question.
From: "mok" <mok_3001@yahoo.com>
Date: Thu, 26 Apr 2001 12:13:23 +0100
Links: << >>  << T >>  << A >>
Hi Folks,

I would like to describe the following in VHDL:

      -----        -----
     |       |      |       |
-->|  B  |--->|  C   | --->
     |      |       |       |
      -----        -----

where B can be either B1 or B2.
I have VHDL code for C, B1 and B2. B1 and B2 describe two different logic
blocks.
I would like to write one VHDL file which can describe both cases,
and choose between B1 and B2 by testing a 'generic' constant or something
like
that.
In short I do not want to write two seperate file for each case,
but one file which can describe both according to a particular
input data (either B1 or B2).
First, is using a 'generic' the way to go?if yes, How can it be
done? if not, how could i reach my goal then? Is there any other
way?

Cheers.

PS. I have not got much VHDL knowledge.



Article: 30723
Subject: TimingTool and Netscape
From: "Chaffey, Paul" <paul_chaffey@yahoo.com>
Date: 26 Apr 2001 03:35:40 -0800
Links: << >>  << T >>  << A >>

Hi all,

we think we have got the TimingTool applet running under netscapes 4.6 and 4.7.
If you are still experiencing differculties please post some feedback.

Also Netscape 6 and Mozilla are saving correctly (have been broken since Sunday)

Many thanks to everyone who have given feedback, and we will try to solve
your issues quickly. We would like some more feedback regarding the Verilog and 
VHDL output from TimingTool.

Regards Paul.

The latest TimingTool version is 0.8g - http://www.timingtool.com
This Tool is FREE to use.


Article: 30724
Subject: Configuration via PCI JTAG
From: "mike" <m.ramm@fz-juelich.de>
Date: Thu, 26 Apr 2001 13:39:39 +0200
Links: << >>  << T >>  << A >>
hi all,
i want to configure my fpga on a pci card via the jtag pins
on the pci connector, but i dont know how to access these pins.
can you help me?
mike





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