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Messages from 30350

Article: 30350
Subject: Combined Multiplier-Divider in Virtex-E
From: "Domagoj" <domagoj<take_this_out>@rasip.fer.hr>
Date: Wed, 4 Apr 2001 02:34:43 +0200
Links: << >>  << T >>  << A >>
Hello,

 I have to make combined multiplier-divider in
Virtex-E, 32x32 bits. Multiplication shouldn't take
more than 4 clocks. Division latency is not an issue
(I would prefer to be less then 32 clocks). Power
dissipation must be kept at minimum. Here are the
options I've been considering :

multiplier :
* pipelined Booth-Wallace tree multiplier

divider :
* Newton-Raphson algorithm (division by reciprocation)
* division by repeated multiplications and
   complementations
* division using BRAM and multipliers (I think it
   would take at least 4 BRAMs)

Since I have almost no experience with FPGA arithmetic,
could anyone suggest me the best way to implement
combined multiplier-divider ? How fast and how small
can it be made ?

Any suggestions would be appreciated very much.

Thanks.

regards,

 Domagoj Babic
 domagoj(et)rasip.fer.hr



Article: 30351
Subject: Re: pseudo random numbers
From: Ray Andraka <ray@andraka.com>
Date: Wed, 04 Apr 2001 00:43:42 GMT
Links: << >>  << T >>  << A >>
I figured as much.  Just didn't have a reference that would be good.  You have
to be careful, because not all those sequences are orthagonal.  A comms or
crypto book might be the best place for a reference of orthagonal sets of MLS
polynomials.

Austin Lesea wrote:
> 
> Ray,
> 
> Thanks.  As you can see, 14 cubes away, Peter found a book in another cube 6 cubes from
> that....
> 
> Sigh.
> 
> Even so, there are even better books that list every maximal length sequence generator
> polynomial (read feedback taps) for any given length register.  For a 12 bit LFSR, there
> are >500 maximal length sequences that are all different.
> 
> These get used for spread spectrum communications (each transmitter has its own sequence
> so it can be despread at the receiver in the presence of other transmitters and
> interference -- this is how GPS works, for eample).
> 
> I was looking for this having nothing to do with "random" numbers, just to solve the
> spread spectrum code generation issue,
> 
> Thanks,
> 
> Austin
> 
> Ray Andraka wrote:
> 
> > Austin,
> >
> > I haven't looked that hard for such a list (I haven't seen one in my travels).
> > I usually use the one in your App note 052: It has one maximal length sequence
> > for each length to something like 168 bits.  You might ask Peter Alfke (I think
> > he wrote that note) if any of his references has a table like you are looking
> > for.
> >
> > ALso, on this thread someone mentioned using a parallel output LFSR.  Yes, you
> > can do that, reducing the polynomials isn't too bad, you basically wind up with
> > n parallel shift registers with the feedback feeding from other shift register
> > outputs.
> >
> > Austin Lesea wrote:
> > >
> > > Ray,
> > >
> > > On another note altogether, I need to have a reference to a book that has all of the
> > > maximal length sequence ploynomials for all LFSR (PRS) generators up to 32 bits (or
> > > more),
> > >
> > > Austin
> > >
> > > Ray Andraka wrote:
> > >
> > > > There are no random sources inherent in the FPGA, although you could conceivably
> > > > use the phase difference between the internal oscillator in the 4Kparts and an
> > > > external clock.  I'd prefer to use the linear feedback shift register (LFSR)
> > > > with a long enough sequence to make it random over a long interval.  That can be
> > > > done very compactly in the 4K using CLB ram (see the xilinx app note on LFSRs, I
> > > > think it is XAPP152).  Use only one bit at a time from the LFSR though, the
> > > > other bits are time shifted copies of the first bit.  A 129 bit LFSR only takes
> > > > 13 LUTs to implement and at 40 MHz will take thousands of years before it
> > > > repeats.  Of course at start-up it will start out with the same value, so the
> > > > sequence is always the same.  That is good for debug, but may be bad for your
> > > > system.  In that case, you need to seed the 129 bits with a random value on
> > > > startup (if you seed it serially, the LFSR is still the same size).  The random
> > > > seed has to be generated by something external to the FPGA since the FPGA is
> > > > always the same on startup.  One possibility, which I mentioned above is to use
> > > > the random relationship of the internal oscillator and an external clock to seed
> > > > the LFSR.
> > > >
> > > >  I'd use the internal oscillator phase relationship to seed an LFSR rather than
> > > > directly for two reasons: 1) The instantaneous phase relationship will be
> > > > random, but a time series will be periodic, and 2) non-repeatability of the
> > > > phase makes debug difficult.  (The LFSR can be forced to a particular start
> > > > state for debug).
> > > >
> > > > Jörg Ritter wrote:
> > > > >
> > > > > Hello,
> > > > >
> > > > > has someone expierience with generating (pseudo) random numbers in
> > > > > FPGA's (XC4000XLA series) ?
> > > > >
> > > > > My first idea was to use maximal length sequences (shift registers
> > > > > having maximum possible period for an r-stage shift register)
> > > > >
> > > > > Is there another source of randomness of the FPGA istself which can be
> > > > > used ?
> > > > >
> > > > > thanks
> > > > > Joerg
> > > >
> > > > --
> > > > -Ray Andraka, P.E.
> > > > President, the Andraka Consulting Group, Inc.
> > > > 401/884-7930     Fax 401/884-7950
> > > > email ray@andraka.com
> > > > http://www.andraka.com
> >
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com

Article: 30352
Subject: Re: Combined Multiplier-Divider in Virtex-E
From: Peter Alfke <palfke@earthlink.net>
Date: Wed, 04 Apr 2001 02:28:17 GMT
Links: << >>  << T >>  << A >>
Without trying to be pushy commercial, may I suggest
skipping Virtex-E and using Virtex-II instead, where you
have 40 (!) fast ( 7 ns ) combinatorial 18 x 18 signed
multipliers to "play" with. Should make your life much
easier. The XC2V1000 and the much smaller, but perhaps
sufficient (?) XC2V40 (with only four multipliers) are
available in limited quantities, rapidly becoming
available for production.

Call our Central European sales office in Munich for
availability.
Welcome to Central Europe !  :-)

Peter Alfke, Xilinx Applications
====================================================

"Domagoj

> Hello,
>
>  I have to make combined multiplier-divider in
> Virtex-E, 32x32 bits. Multiplication shouldn't take
> more than 4 clocks. Division latency is not an issue
> (I would prefer to be less then 32 clocks). Power
> dissipation must be kept at minimum. Here are the
> options I've been considering :
>
> multiplier :
> * pipelined Booth-Wallace tree multiplier
>
> divider :
> * Newton-Raphson algorithm (division by reciprocation)
> * division by repeated multiplications and
>    complementations
> * division using BRAM and multipliers (I think it
>    would take at least 4 BRAMs)
>
> Since I have almost no experience with FPGA arithmetic,
> could anyone suggest me the best way to implement
> combined multiplier-divider ? How fast and how small
> can it be made ?
>
> Any suggestions would be appreciated very much.
>
> Thanks.
>
> regards,
>
>  Domagoj Babic
>  domagoj(et)rasip.fer.hr


Article: 30353
Subject: Re: Combined Multiplier-Divider in Virtex-E
From: Ray Andraka <ray@andraka.com>
Date: Wed, 04 Apr 2001 03:22:14 GMT
Links: << >>  << T >>  << A >>
For the multiplication, you might refer to my multiplication in FPGAs page on my
website.  Since you have 4 clocks to do the multiplication in, I'd use an 8x32
multiplier which performs 8x32 partial products and then sum those four partials
in a scaling accumulator.  The 8x32 multiplier is made up of an adder tree (3
adders) that add 4 2x32 partial products together.  The 2x32 partial products
are one  slice per pari of bits (see the 2xn bit virtex construction under
computed partial products on the web page).  The multiplier will occupy a 4.5w
by about 20h CLB area, height depending on how many output bits you keep.  

There is also some text on there as to why you don't want to use a wallace tree
in an FPGA.

For the divider, you state that latency is not an issue.  You could use a
restoring or non-restoring division algorithm, which I think can be done in a
single column of 33 clbs.  as you alluded, you can also use the multiplier to
reduce the number of cycles.

"Domagoj
> 
> Hello,
> 
>  I have to make combined multiplier-divider in
> Virtex-E, 32x32 bits. Multiplication shouldn't take
> more than 4 clocks. Division latency is not an issue
> (I would prefer to be less then 32 clocks). Power
> dissipation must be kept at minimum. Here are the
> options I've been considering :
> 
> multiplier :
> * pipelined Booth-Wallace tree multiplier
> 
> divider :
> * Newton-Raphson algorithm (division by reciprocation)
> * division by repeated multiplications and
>    complementations
> * division using BRAM and multipliers (I think it
>    would take at least 4 BRAMs)
> 
> Since I have almost no experience with FPGA arithmetic,
> could anyone suggest me the best way to implement
> combined multiplier-divider ? How fast and how small
> can it be made ?
> 
> Any suggestions would be appreciated very much.
> 
> Thanks.
> 
> regards,
> 
>  Domagoj Babic
>  domagoj(et)rasip.fer.hr

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com

Article: 30354
Subject: Xilinx Foundation 2.1i License
From: "Mark Walter" <maw@nospam.com>
Date: Wed, 04 Apr 2001 05:31:56 GMT
Links: << >>  << T >>  << A >>
Does anyone know if the license they give you for the Student Version is
time limited or does it work forever?

Mark



Article: 30355
Subject: Re: salary info for FPGA/HardwareEng's
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Wed, 04 Apr 2001 01:37:40 -0400
Links: << >>  << T >>  << A >>
salary_guide@hitechsalary.com wrote:
> 
>    Part 1Type: multipart

Anyone know about this? I get a "Part 1" link. When I click it I have to
choose a couple of options, when I select "save file" the file name
defaults to "k5py6.30896%24nR.5567064%40typhoon.nyroc.rr.com". I don't
normally run executables from the web for fear of viruses. 

Anyone know if this if for real? Or is this just another newsgroup
virus?


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 30356
Subject: Re: Combined Multiplier-Divider in Virtex-E
From: "Domagoj" <domagoj<take_this_out>@rasip.fer.hr>
Date: Wed, 4 Apr 2001 07:52:16 +0200
Links: << >>  << T >>  << A >>
Hi Peter !

    Thank you for the answer. Built-in multipliers are a great idea,
but I would like to have the vhdl code as portable as possible. Anyway, does
Alliance 2.1i support Virtex II devices at all ?

    Domagoj Babic
    domagoj(et)rasip.fer.hr

Peter Alfke <palfke@earthlink.net> wrote in message
news:3ACA86BF.5895F8C8@earthlink.net...
> Without trying to be pushy commercial, may I suggest
> skipping Virtex-E and using Virtex-II instead, where you
> have 40 (!) fast ( 7 ns ) combinatorial 18 x 18 signed
> multipliers to "play" with. Should make your life much
> easier. The XC2V1000 and the much smaller, but perhaps
> sufficient (?) XC2V40 (with only four multipliers) are
> available in limited quantities, rapidly becoming
> available for production.
>
> Call our Central European sales office in Munich for
> availability.
> Welcome to Central Europe !  :-)
>
> Peter Alfke, Xilinx Applications
> ====================================================
>
> "Domagoj
>
> > Hello,
> >
> >  I have to make combined multiplier-divider in
> > Virtex-E, 32x32 bits. Multiplication shouldn't take
> > more than 4 clocks. Division latency is not an issue
> > (I would prefer to be less then 32 clocks). Power
> > dissipation must be kept at minimum. Here are the
> > options I've been considering :
> >
> > multiplier :
> > * pipelined Booth-Wallace tree multiplier
> >
> > divider :
> > * Newton-Raphson algorithm (division by reciprocation)
> > * division by repeated multiplications and
> >    complementations
> > * division using BRAM and multipliers (I think it
> >    would take at least 4 BRAMs)
> >
> > Since I have almost no experience with FPGA arithmetic,
> > could anyone suggest me the best way to implement
> > combined multiplier-divider ? How fast and how small
> > can it be made ?
> >
> > Any suggestions would be appreciated very much.
> >
> > Thanks.
> >
> > regards,
> >
> >  Domagoj Babic
> >  domagoj(et)rasip.fer.hr
>



Article: 30357
Subject: Re: Combined Multiplier-Divider in Virtex-E
From: "Domagoj" <domagoj<take_this_out>@rasip.fer.hr>
Date: Wed, 4 Apr 2001 08:00:03 +0200
Links: << >>  << T >>  << A >>
Hi Ray !

    I have also been thinking about combining a few smaller
multipliers that way. Also, have studied your website :) .

    Restoring-Non restoring divider - is it the same as shift
and substract divider found in literature ? (that can also
be used for square roots)

Thanks for an advice !

Kind regards,

            Domagoj Babic
            domagoj(et)rasip.fer.hr

Ray Andraka <ray@andraka.com> wrote in message
news:3ACA94DD.FE1F3D2B@andraka.com...
> For the multiplication, you might refer to my multiplication in FPGAs page
on my
> website.  Since you have 4 clocks to do the multiplication in, I'd use an
8x32
> multiplier which performs 8x32 partial products and then sum those four
partials
> in a scaling accumulator.  The 8x32 multiplier is made up of an adder tree
(3
> adders) that add 4 2x32 partial products together.  The 2x32 partial
products
> are one  slice per pari of bits (see the 2xn bit virtex construction under
> computed partial products on the web page).  The multiplier will occupy a
4.5w
> by about 20h CLB area, height depending on how many output bits you keep.
>
> There is also some text on there as to why you don't want to use a wallace
tree
> in an FPGA.
>
> For the divider, you state that latency is not an issue.  You could use a
> restoring or non-restoring division algorithm, which I think can be done
in a
> single column of 33 clbs.  as you alluded, you can also use the multiplier
to
> reduce the number of cycles.
>
> "Domagoj
> >
> > Hello,
> >
> >  I have to make combined multiplier-divider in
> > Virtex-E, 32x32 bits. Multiplication shouldn't take
> > more than 4 clocks. Division latency is not an issue
> > (I would prefer to be less then 32 clocks). Power
> > dissipation must be kept at minimum. Here are the
> > options I've been considering :
> >
> > multiplier :
> > * pipelined Booth-Wallace tree multiplier
> >
> > divider :
> > * Newton-Raphson algorithm (division by reciprocation)
> > * division by repeated multiplications and
> >    complementations
> > * division using BRAM and multipliers (I think it
> >    would take at least 4 BRAMs)
> >
> > Since I have almost no experience with FPGA arithmetic,
> > could anyone suggest me the best way to implement
> > combined multiplier-divider ? How fast and how small
> > can it be made ?
> >
> > Any suggestions would be appreciated very much.
> >
> > Thanks.
> >
> > regards,
> >
> >  Domagoj Babic
> >  domagoj(et)rasip.fer.hr
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com



Article: 30358
Subject: Verilog FAQ: April 2001
From: "Rajesh Bawankule" <rajesh52@hotmail.com>
Date: Wed, 04 Apr 2001 06:13:14 GMT
Links: << >>  << T >>  << A >>
Greetings
This is semimonthly announcement of Verilog FAQ.

Verilog FAQ is located at
http://www.parmita.com/verilogfaq/

Alternate Verilog FAQ is an attempt to gather the answers
to most Frequently Asked Questions about Verilog HDL in
one place. It also  contains list of publications, services,
and products.

Alternate Verilog FAQ is divided into three logical parts.

Part 1 : Introduction and misc. questions
Part 2 : Technical Topics
Part 3 : Tools and Services

What's New section outlines the changes in different versions
and announcements. Links connects you to related
informative links in internet.

Your suggestions to make this FAQ more informative are
welcome.

Rajesh Bawankule
(Also Visit Chip-Guru : http://www.chip-guru.com/ )



Article: 30359
Subject: Re: Xilinx Foundation 2.1i License
From: Chris Dunlap <cdunlap@xilinx.com>
Date: Wed, 04 Apr 2001 00:57:58 -0600
Links: << >>  << T >>  << A >>
You can find out yourself by looking at the date on the increment line of
your license.  If the date is 1-jan-0 then it will not expire.  If it is
something else, it will expire on that date.

Chris

Mark Walter wrote:

> Does anyone know if the license they give you for the Student Version is
> time limited or does it work forever?
>
> Mark


Article: 30360
Subject: Information about configuraiton time
From: Shigeyuki Takano <d8021103@u-aizu.ac.jp>
Date: Wed, 04 Apr 2001 16:00:26 +0900
Links: << >>  << T >>  << A >>
Hi,

I'm looking for information about configuration time of FPGAs/CPLDs as,
vendor name, product name, configuration cycles, and its clock cycle
time.

Does anyone have information?

Regards,
S. Takano

Article: 30361
Subject: DSP Volume-control in FPGA
From: Kristian Rye Vennesland <kristirv@stud.iet.hist.no>
Date: Wed, 04 Apr 2001 09:24:17 +0200
Links: << >>  << T >>  << A >>
Hello,

I'm currently undertaking a university project where I am supposed to
build a digital amplifier. I'm all done with the amplifying part, and
most of the work is done
in an ACEX 1K FPGA from Altera.

But, I'm not quite sure how to implement a digital volume-control in the
FPGA. I am using
 PCM-code and have been dabbling with the idea to just divide the
PCM-code with a user-defined number
to get a "weaker" signal, but that would change the frequency of the
signal somewhat.

Any ideas?

Thanks in advance for any help

Kristian Rye Vennesland

--
-----------------------------------

Kristian Rye Vennesland

E-mail : Kristirv@stud.iet.hist.no
Cell.phone : +47 97 03 14 94

Mail Address:

Kristian Rye Vennesland
Nonnegata 2B
7014 Trondheim
N-7014
NORWAY

-----------------------------------



Article: 30362
Subject: Re: Reed/Solomon ENcoder
From: Steven Sanders <sanders@imec.be>
Date: Wed, 04 Apr 2001 09:32:24 +0200
Links: << >>  << T >>  << A >>
Thanx for all the pointers and references!

I already managed to code a working rs encoder...

greetz,

Steven

Steven Sanders wrote:
> 
> Hello,
> 
> What I`m looking for is a R/S ENcoder with following fixed
> specifications (VHDL, no IP cores or netlists):
> 
> n=255
> k=239
> GF(256)
> p(x)=1 + x^2 + x^3 + x^4 + x^8 (DVB standard)
> g(x)=(x+alpha^0)...(x+alpha^15)
> 
> Does someone have any VHDL, architecture descriptions, references
> for this coder?
> 
> Thanx in advance!
> 
> Steven

Article: 30363
Subject: Re: DSP Volume-control in FPGA
From: "Ralph Weir" <ralph@hunteng.demon.co.uk>
Date: Wed, 4 Apr 2001 09:05:53 +0100
Links: << >>  << T >>  << A >>
Just multiply the signal by a fraction... you can do this by doing a
full-precision multiply (eg 16bit * 16bit -> 32bit) followed by a shift.
Multiplying by 1 & taking the top 16 bits is equivalent to a 16-bit right
shift, by 2 is a 15-bit right shift and so on, and of course you can
multiply by odd numbers.

It won't affect the frequency of your signal.  It will only affect the
amplitude.  Interesting effects on the noise (divide the signal by 16 and
you've only got  a 12-bit dynamic range...)

All the best,
Ralph Weir
Hunt Engineering
http://www.hunteng.co.uk

"Kristian Rye Vennesland" <kristirv@stud.iet.hist.no> wrote in message
news:3ACACC21.191EA1AF@stud.iet.hist.no...
> Hello,
>
> I'm currently undertaking a university project where I am supposed to
> build a digital amplifier. I'm all done with the amplifying part, and
> most of the work is done
> in an ACEX 1K FPGA from Altera.
>
> But, I'm not quite sure how to implement a digital volume-control in the
> FPGA. I am using
>  PCM-code and have been dabbling with the idea to just divide the
> PCM-code with a user-defined number
> to get a "weaker" signal, but that would change the frequency of the
> signal somewhat.
>
> Any ideas?
>
> Thanks in advance for any help
>
> Kristian Rye Vennesland
>
> --
> -----------------------------------
>
> Kristian Rye Vennesland
>
> E-mail : Kristirv@stud.iet.hist.no
> Cell.phone : +47 97 03 14 94
>
> Mail Address:
>
> Kristian Rye Vennesland
> Nonnegata 2B
> 7014 Trondheim
> N-7014
> NORWAY
>
> -----------------------------------
>
>
>



Article: 30364
Subject: Re: FPGA V CPLD
From: "Compilit" <compilehr@hotmail.com>
Date: Wed, 4 Apr 2001 01:17:39 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

------=_NextPart_000_0074_01C0BCA5.0A737B60
Content-Type: text/plain;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

Thanks Austin, for a good story. :)
  "Austin Lesea" <austin.lesea@xilinx.com> wrote in message =
news:3AC53687.664E3486@xilinx.com...
  Dave,=20


  (snip)
  Numerically yours,=20

  Austin (the zero hero)=20
   =20

  Speedy Zero Two wrote:=20

    All,=20
    I've been told that logic designs implemented within FPGA's are more =

    temperamental than CPLD's.=20

    Any insight ?=20

    Cheers=20
    Dave


------=_NextPart_000_0074_01C0BCA5.0A737B60
Content-Type: text/html;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4611.1300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Thanks Austin, for a good story. =
:)</FONT></DIV>
<BLOCKQUOTE dir=3Dltr=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
  <DIV>"Austin Lesea" &lt;<A=20
  =
href=3D"mailto:austin.lesea@xilinx.com">austin.lesea@xilinx.com</A>&gt; =
wrote in=20
  message <A=20
  =
href=3D"news:3AC53687.664E3486@xilinx.com">news:3AC53687.664E3486@xilinx.=
com</A>...</DIV>
  <DIV>Dave, </DIV>
  <DIV>&nbsp;</DIV>
  <DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
  <DIV><FONT face=3DArial size=3D2>(snip)</FONT></DIV>
  <P>Numerically yours,=20
  <P>Austin (the zero hero) <BR>&nbsp;=20
  <P>Speedy Zero Two wrote:=20
  <BLOCKQUOTE TYPE=3D"CITE">All,=20
    <P>I've been told that logic designs implemented within FPGA's are =
more=20
    <BR>temperamental than CPLD's.=20
    <P>Any insight ?=20
    <P>Cheers <BR>Dave</P></BLOCKQUOTE></BLOCKQUOTE></BODY></HTML>

------=_NextPart_000_0074_01C0BCA5.0A737B60--


Article: 30365
Subject: Re: pseudo random numbers
From: Nicolas Matringe <nicolas.matringe@IPricot.com>
Date: Wed, 04 Apr 2001 11:17:41 +0200
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
> 
> Ray,
> 
> On another note altogether, I need to have a reference to a book
> that has all of the maximal length sequence ploynomials for all
> LFSR (PRS) generators up to 32 bits (or more),

I found this once and I keep it preciously in my bookmarks:
http://www.cs.cmu.edu/People/koopman/lfsr/index.html

It only goes up to 39 bits but it gives ALL the possible feedback terms
for each length.

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 30366
Subject: Re: salary info for FPGA/HardwareEng's
From: Craig from FL <hyarbr01@harris.com>
Date: Wed, 04 Apr 2001 08:14:56 -0400
Links: << >>  << T >>  << A >>
It's ok, just go here: www.hitechsalary.com

- Craig

Rick Collins wrote:
> 
> salary_guide@hitechsalary.com wrote:
> >
> >    Part 1Type: multipart
> 
> Anyone know about this? I get a "Part 1" link. When I click it I have to
> choose a couple of options, when I select "save file" the file name
> defaults to "k5py6.30896%24nR.5567064%40typhoon.nyroc.rr.com". I don't
> normally run executables from the web for fear of viruses.
> 
> Anyone know if this if for real? Or is this just another newsgroup
> virus?
> 
> --
> 
> Rick "rickman" Collins
> 
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
> 
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 30367
Subject: Re: salary info for FPGA/HardwareEng's
From: Ray Andraka <ray@andraka.com>
Date: Wed, 04 Apr 2001 12:45:54 GMT
Links: << >>  << T >>  << A >>
I had the same thoughts.  I didn't risk it.

Rick Collins wrote:
> 
> salary_guide@hitechsalary.com wrote:
> >
> >    Part 1Type: multipart
> 
> Anyone know about this? I get a "Part 1" link. When I click it I have to
> choose a couple of options, when I select "save file" the file name
> defaults to "k5py6.30896%24nR.5567064%40typhoon.nyroc.rr.com". I don't
> normally run executables from the web for fear of viruses.
> 
> Anyone know if this if for real? Or is this just another newsgroup
> virus?
> 
> --
> 
> Rick "rickman" Collins
> 
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
> 
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com

Article: 30368
Subject: Re: Combined Multiplier-Divider in Virtex-E
From: Ray Andraka <ray@andraka.com>
Date: Wed, 04 Apr 2001 12:51:30 GMT
Links: << >>  << T >>  << A >>
Restoring division is that shit-subtract animal.  Non restoring is a minor
refinement on that.  Those will probably give you the smallest circuits.  If you
want to speed up the division there are a number of methods.  I'd recommend
browsing a good computer arithmetic book.  Isreal Koren's book covers a number
of fast division algorithms in detail.  There is a link from my website to his
web page for the book (that one I don't get a commission on, but it is a pretty
good book).

"Domagoj
> 
> Hi Ray !
> 
>     I have also been thinking about combining a few smaller
> multipliers that way. Also, have studied your website :) .
> 
>     Restoring-Non restoring divider - is it the same as shift
> and substract divider found in literature ? (that can also
> be used for square roots)
> 
> Thanks for an advice !
> 
> Kind regards,
> 
>             Domagoj Babic
> 
-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com

Article: 30369
Subject: Re: pseudo random numbers
From: =?iso-8859-1?Q?J=F6rg?= Ritter <ritter@informatik.uni-halle.de>
Date: Wed, 04 Apr 2001 15:49:20 +0200
Links: << >>  << T >>  << A >>
Hi Ray,

I've a more general question concerning the app notes.
In those app notes tricky circuits are presented , which fits into a few CLB's.
Mostly a schematic describes the circuit.

If the circuit isn't available in Coregen/Logiblox what is your favorite way to
create a module (as netlist)?
  Do you implement the design structurally in VHDL, synthesize and floorplan the
result  manually?
  Or do you prefer a schematic entry tool, where you can instantiate basic XC4000
elements, e.g. like RAM16x1S?

Thanks
Joerg

> There are no random sources inherent in the FPGA, although you could conceivably
> use the phase difference between the internal oscillator in the 4Kparts and an
> external clock.  I'd prefer to use the linear feedback shift register (LFSR)
> with a long enough sequence to make it random over a long interval.  That can be
> done very compactly in the 4K using CLB ram (see the xilinx app note on LFSRs, I
> think it is XAPP152).


Article: 30370
Subject: High Speed PLA/FPGA
From: riccardo.zambon@infineon.com (Riccardo Zambon)
Date: Wed, 4 Apr 2001 14:26:20 +0000 (UTC)
Links: << >>  << T >>  << A >>

Hi all,
I have to map a clk phase generator, generating  8 clk phases
@155MHz. The distance between phases is 800ps and high
precision is required.
Does anybody knows about some programmable (very)fast
logic that can allow that? I don't know if there is some ECL
(or PECL) programmable stuff anywhere....

Forgetting ECL, has anybody experienced VirtexII family at very high
system speed?

Thanks for help,
Riccardo


-- 
Posted from david.siemens.it [192.109.0.136] 
via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 30371
Subject: Re: pseudo random numbers
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 04 Apr 2001 08:54:29 -0700
Links: << >>  << T >>  << A >>
Ray,

Some codes are "good", as you note, and I am familiar with those having nice properties being
called "Gold" codes.  I don't know if that is because they are valuable, or if the
mathematician who discovered them was named Gold.

Orthogonality is a buzzword that is mis-used by the CDMA folks -- think about it: if you have
a whole bunch of mobile stations in motion, nothing is "orthogonal" anymore at the receiver!
They are orthogonal leaving the transmitter, but then at the mobile receiver, and with the
multipath, we have just lost orthogonality again.

Austin

Ray Andraka wrote:

> I figured as much.  Just didn't have a reference that would be good.  You have
> to be careful, because not all those sequences are orthagonal.  A comms or
> crypto book might be the best place for a reference of orthagonal sets of MLS
> polynomials.
>
> Austin Lesea wrote:
> >
> > Ray,
> >
> > Thanks.  As you can see, 14 cubes away, Peter found a book in another cube 6 cubes from
> > that....
> >
> > Sigh.
> >
> > Even so, there are even better books that list every maximal length sequence generator
> > polynomial (read feedback taps) for any given length register.  For a 12 bit LFSR, there
> > are >500 maximal length sequences that are all different.
> >
> > These get used for spread spectrum communications (each transmitter has its own sequence
> > so it can be despread at the receiver in the presence of other transmitters and
> > interference -- this is how GPS works, for eample).
> >
> > I was looking for this having nothing to do with "random" numbers, just to solve the
> > spread spectrum code generation issue,
> >
> > Thanks,
> >
> > Austin
> >
> > Ray Andraka wrote:
> >
> > > Austin,
> > >
> > > I haven't looked that hard for such a list (I haven't seen one in my travels).
> > > I usually use the one in your App note 052: It has one maximal length sequence
> > > for each length to something like 168 bits.  You might ask Peter Alfke (I think
> > > he wrote that note) if any of his references has a table like you are looking
> > > for.
> > >
> > > ALso, on this thread someone mentioned using a parallel output LFSR.  Yes, you
> > > can do that, reducing the polynomials isn't too bad, you basically wind up with
> > > n parallel shift registers with the feedback feeding from other shift register
> > > outputs.
> > >
> > > Austin Lesea wrote:
> > > >
> > > > Ray,
> > > >
> > > > On another note altogether, I need to have a reference to a book that has all of the
> > > > maximal length sequence ploynomials for all LFSR (PRS) generators up to 32 bits (or
> > > > more),
> > > >
> > > > Austin
> > > >
> > > > Ray Andraka wrote:
> > > >
> > > > > There are no random sources inherent in the FPGA, although you could conceivably
> > > > > use the phase difference between the internal oscillator in the 4Kparts and an
> > > > > external clock.  I'd prefer to use the linear feedback shift register (LFSR)
> > > > > with a long enough sequence to make it random over a long interval.  That can be
> > > > > done very compactly in the 4K using CLB ram (see the xilinx app note on LFSRs, I
> > > > > think it is XAPP152).  Use only one bit at a time from the LFSR though, the
> > > > > other bits are time shifted copies of the first bit.  A 129 bit LFSR only takes
> > > > > 13 LUTs to implement and at 40 MHz will take thousands of years before it
> > > > > repeats.  Of course at start-up it will start out with the same value, so the
> > > > > sequence is always the same.  That is good for debug, but may be bad for your
> > > > > system.  In that case, you need to seed the 129 bits with a random value on
> > > > > startup (if you seed it serially, the LFSR is still the same size).  The random
> > > > > seed has to be generated by something external to the FPGA since the FPGA is
> > > > > always the same on startup.  One possibility, which I mentioned above is to use
> > > > > the random relationship of the internal oscillator and an external clock to seed
> > > > > the LFSR.
> > > > >
> > > > >  I'd use the internal oscillator phase relationship to seed an LFSR rather than
> > > > > directly for two reasons: 1) The instantaneous phase relationship will be
> > > > > random, but a time series will be periodic, and 2) non-repeatability of the
> > > > > phase makes debug difficult.  (The LFSR can be forced to a particular start
> > > > > state for debug).
> > > > >
> > > > > Jörg Ritter wrote:
> > > > > >
> > > > > > Hello,
> > > > > >
> > > > > > has someone expierience with generating (pseudo) random numbers in
> > > > > > FPGA's (XC4000XLA series) ?
> > > > > >
> > > > > > My first idea was to use maximal length sequences (shift registers
> > > > > > having maximum possible period for an r-stage shift register)
> > > > > >
> > > > > > Is there another source of randomness of the FPGA istself which can be
> > > > > > used ?
> > > > > >
> > > > > > thanks
> > > > > > Joerg
> > > > >
> > > > > --
> > > > > -Ray Andraka, P.E.
> > > > > President, the Andraka Consulting Group, Inc.
> > > > > 401/884-7930     Fax 401/884-7950
> > > > > email ray@andraka.com
> > > > > http://www.andraka.com
> > >
> > > --
> > > -Ray Andraka, P.E.
> > > President, the Andraka Consulting Group, Inc.
> > > 401/884-7930     Fax 401/884-7950
> > > email ray@andraka.com
> > > http://www.andraka.com
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com


Article: 30372
Subject: Re: pseudo random numbers
From: Ray Andraka <ray@andraka.com>
Date: Wed, 04 Apr 2001 17:47:33 GMT
Links: << >>  << T >>  << A >>
I prefer to use set of tools for a design rather than mixing.  I use VHDL
predominantly now, so I use a combination of structural and rtl coding.  In
order to put placement (RLOCs) in the code, you need to code the macro
structurally using the xilinx primitives.  I do that on pieces that I intend to
use frequently, either in a particular design or across many designs.  It takes
longer the first time, but after that, having theplacment included is a big time
saver.  For things that only get used one or two times, I'll code with RTL and
take care of it in the floorplanner.  Note that the floorplanner placement is on
a flat design, so even though you can presetn the design elements
hierarchically, the result is flat.  

I don't generally use the coregen parts because they don't give you the
flexibility of going inside the macro to customize for the application: for
example, the Virtex coregen multiplier can be made faster with a layout change,
and quite a bit faster by adding some extra logic.

Jörg Ritter wrote:
> 
> Hi Ray,
> 
> I've a more general question concerning the app notes.
> In those app notes tricky circuits are presented , which fits into a few CLB's.
> Mostly a schematic describes the circuit.
> 
> If the circuit isn't available in Coregen/Logiblox what is your favorite way to
> create a module (as netlist)?
>   Do you implement the design structurally in VHDL, synthesize and floorplan the
> result  manually?
>   Or do you prefer a schematic entry tool, where you can instantiate basic XC4000
> elements, e.g. like RAM16x1S?
> 
> Thanks
> Joerg
> 
> > There are no random sources inherent in the FPGA, although you could conceivably
> > use the phase difference between the internal oscillator in the 4Kparts and an
> > external clock.  I'd prefer to use the linear feedback shift register (LFSR)
> > with a long enough sequence to make it random over a long interval.  That can be
> > done very compactly in the 4K using CLB ram (see the xilinx app note on LFSRs, I
> > think it is XAPP152).

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com

Article: 30373
Subject: Simulation result shows that
From: Qian <qianz@cae.wisc.edu>
Date: Wed, 4 Apr 2001 10:13:32 -0800
Links: << >>  << T >>  << A >>
Too short LACTH ENABLE HIGH pulse
Missing time 500ps
how to solve that?
Thanks a lot!

Article: 30374
Subject: Re: PCI-X core
From: Richard Iachetta <iachetta@us.ibm.com>
Date: Wed, 4 Apr 2001 15:30:24 -0500
Links: << >>  << T >>  << A >>
In article <99ud6g$2f4$1@slb1.atl.mindspring.net>, austin@darkro98om.com 
says...
> > Could someone enlighten me ? Is PCI-X just a clock speed uprated 66MHz PCI
> > or are there any fundamental differences ? As far as I can see the only
> > significant change is to allow split cycles.
> 
> It's basically registered.  More clock cycles for control, but given it can
> support much higher clock rates, it's faster.

PCIX supports up to 133MHz, 64-bits (about 1 GB per second).
Another big performance improvement is split transactions (which the 
original poster alludes to).  Split tranactions are a nice replacement 
for delayed reads (at the cost of some complexity).  Instead of the 
master polling again and again asking the target for the read data and 
getting retried when its not yet available, the target can simply issue a 
"split response" to the original read and when the target has the read 
data it masters a "split completion" transaction back to the original 
master.  Split completions look like writes as someone else pointed out.  
Reads with immediate data are still allowed but discouraged.  Single beat 
writes can also be split.

Initiator wait states are not allowed in PCIX.  Target wait states can 
only occur before the first TRDY and there are strict limits to their 
number.  Also for performance reasons, initators and targets are only 
allowed to disconnect on 128-byte boundaries except when the byte count 
is fully delivered.  PCIX defines an attribute phase after the address 
phase so the initiator can give more information about the transaction 
including byte count and tag.  Tags are used for split transactions 
because multiple split transactions can be outstanding for the same 
master and partial split completions for the different transactions can 
be returned in any order so the tags are used to keep track of which read 
each partial split completion is associated with.

-- 
Rich Iachetta
iachetta@us.ibm.com
I do not speak for IBM.



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