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Messages from 34375

Article: 34375
Subject: Re: Logic Emulation
From: johne@vcd.hp.com (John Eaton)
Date: 22 Aug 2001 21:08:55 GMT
Links: << >>  << T >>  << A >>
Muzaffer Kal (muzaffer@dspia.com) wrote:
: "Tim" <tim@rockylogic.com.nospam.com> wrote:

: I am not sure what you mean by "No tri-states in ASICs". I guess it is
: possible that one is discouraged to use tri-states in a standard cell
: or gate array targeted design but I have yet to see a cell library
: which doesn't have any internal tri-state buffers or inverters.
: Especially with a standard cell methodology, you can do what ever you
: want, including designing your own cells.


The problem with TS busses is that the control signals during scan test
are somewhat random and may result in multiple buffers driving at the
same time. If you have a TS buss you must have special control of the
buffers during scan. They also make it hard to use tools like static
timing analysis because they create one huge feedback timing loop.


The main advocates of TS busses are usually ex_pcb_designers_now_turned_
logic_designers who somehow think that it gives you a better_faster_cheaper_
smaller route. They usually don't know what they are talking about. 

If the engineer who actually routes your asic tells you that you can do 
better with TS busses then you should use them. All my guys tell me that
with todays tools that there is no advantage to TS.



John Eaton



Article: 34376
Subject: Re: JTAG issue again ...
From: JOo@lbl.gov (Justin Oo)
Date: 22 Aug 2001 14:24:52 -0700
Links: << >>  << T >>  << A >>
JOo@lbl.gov (Justin Oo) wrote in message news:<ad213de0.0108211650.4f99ec73@posting.google.com>...
> hi,
>    i am having trouble using JTAG...i have Virtex XCV300 board (VW-300
> Virtual Workbench from VCC)...and when i try to download my design
> .bit file thru JTAG onto the board...the JTAG PROGRAMMER crashed on
> me.  I put the JTAG chains which i believe for my board is as follow:
>   
>        --------------      ---------------
>  TDI--| XCV300_BG352 |----| XC9536        |-----|
>       | mydesign.bit |    | JED/BIT File? |     |
>       |--------------|    |---------------|     |
>                                                 |
>                                                 |
>  TDO -------------------------------------------|
> 
>   so where "JED/BIT File?", i try to specify the XC9536.bsd file...but
> as soon as i do that...the JTAG Programmer crashes...
> 
>   "The instruction at "0x5f40129c" referenced memory at "0x00000004".
> The memory could not be read."
> 
> any idea how i can get around it? i tried BYPASSING that XC9536 as
> well...but if i do that i get the message that says " The JTAG chain
> has one or more devices that are of an undefined type."  any input is
> very much appreciated! Thanks!


      um...nevermind!  i guess it's caused by the software...i have
downloaded the update from the Xilinx website...now the problem has
been straightened out. Thanx!  But another question is...how do i
READBACK the contents from the Block RAMs or the SELECT RAMs thru
JTAG??

--
" Great minds discuss ideas;
  Average minds discuss events;
  Small minds discuss people. " 
~ Justin

Article: 34377
Subject: Re: How does For Loop works in AHDL
From: John_H <johnhandwork@mail.com>
Date: Wed, 22 Aug 2001 21:41:15 GMT
Links: << >>  << T >>  << A >>
I fear you may be in way over your head and that the best place for help might
not be this group.  Serial data output is pretty basic.  Forgive my pseudo-AHDL
since I've been coding in Verilog for so long now:

if( Count[4..0] == 21 ) then            -- Load
  Count[4..0] = 0;
  ShiftWord[21..0] = InputWord[21..0];
else                                    -- shift
  Count[4..0] = Count[4..0] + 1;
  ShiftWord[21..0] = (0,ShiftWord[21..0]);
endif;

Output = ShiftWord[0];



Abhimanyu Rastogi wrote:

> But how do i do this......    could u give an example of serially outputting
> data.....  ??


Article: 34378
Subject: Re: hardware damage to a Virtex or Spartan-II?
From: Philip Freidin <philip@fliptronics.com>
Date: Wed, 22 Aug 2001 15:32:03 -0700
Links: << >>  << T >>  << A >>
On 22 Aug 2001 18:42:59 GMT, gah@ugcs.caltech.edu (glen herrmannsfeldt) wrote:
>"Philip Freidin" <philip@fliptronics.com> wrote in message
>news:chu5otc4n394qaklkj21e0kisubphc5ng4@4ax.com...
>> On 21 Aug 2001 20:43:17 GMT, gah@ugcs.caltech.edu wrote:
>> >What is the maximum clock speed for Virtex-II, FF, through one LUT,
>> >to another FF?
>>
>> In a V-II , -5 speed grade,  M3.3.08i speed files, with careful placement,
>> about 666MHz .
>>
>
>So, again with careful design, one could have a design with about half
>the gates and FF changing state at 666MHz, or about 333MHz each.
>(That is, assuming random data bits.)  About a factor of two from what
>was claimed for the oscillation modes.
>-- glen

Not really. The average user that has abdicated responsibility for their
design details to a synthesis tool and use typical design styles would be
lucky to get a reasonable sized design (anything over 1000 gates) to
run at more than 200MHz. So random data leads to a data toggle rate
below 100MHz.

In my previous post I wrote "careful placement". You wrote "careful design"
I should have written "extremely detailed placement (multiple weeks for a
few hundred gates)" 

All numbers above pulled out of thin air.

Philip Freidin

Philip Freidin
Fliptronics

Article: 34379
Subject: Re: JTAG issue again ...
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 22 Aug 2001 23:34:45 +0100
Links: << >>  << T >>  << A >>


Justin Oo wrote:

> JOo@lbl.gov (Justin Oo) wrote in message news:<ad213de0.0108211650.4f99ec73@posting.google.com>...
> > hi,
> >    i am having trouble using JTAG...i have Virtex XCV300 board (VW-300
> > Virtual Workbench from VCC)...and when i try to download my design
> > .bit file thru JTAG onto the board...the JTAG PROGRAMMER crashed on
> > me.  I put the JTAG chains which i believe for my board is as follow:
> >
> >        --------------      ---------------
> >  TDI--| XCV300_BG352 |----| XC9536        |-----|
> >       | mydesign.bit |    | JED/BIT File? |     |
> >       |--------------|    |---------------|     |
> >                                                 |
> >                                                 |
> >  TDO -------------------------------------------|
> >
> >   so where "JED/BIT File?", i try to specify the XC9536.bsd file...but
> > as soon as i do that...the JTAG Programmer crashes...
> >
> >   "The instruction at "0x5f40129c" referenced memory at "0x00000004".
> > The memory could not be read."
> >
> > any idea how i can get around it? i tried BYPASSING that XC9536 as
> > well...but if i do that i get the message that says " The JTAG chain
> > has one or more devices that are of an undefined type."  any input is
> > very much appreciated! Thanks!
>
>       um...nevermind!  i guess it's caused by the software...i have
> downloaded the update from the Xilinx website...now the problem has
> been straightened out. Thanx!  But another question is...how do i
> READBACK the contents from the Block RAMs or the SELECT RAMs thru
> JTAG??
>

As fas as I know the answer is you can't do this through the JTAG Programmer. There's an apps note
somewhere that gives the raw information on how to do it but AFAIK no one actually has. The Xilinx
read-back solution is:

o Get a Multilinx cable.

o Drive it through USB [The serial port mode has the reputation of being incredibly slooooow].

o Of course now you have to upgrade your NT system to Win2K so all your other tools may break.



Article: 34380
Subject: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
From: "Dave Feustel" <dfeustel1@home.com>
Date: Wed, 22 Aug 2001 23:21:11 GMT
Links: << >>  << T >>  << A >>
Dave,

Thanks for the info.

As a very longtime system software person, I am fed up with the
Rube Goldberg software licensing schemes that Flexln has come up with.
Every time I did something different during the Modelsim install process
I found a new and unexplained path to licensing failure. In a conversation
with George McFarland I offered to be an install tester since I was obviously
so good at finding  install-related show stoppers. McFarland demurred.

 I solved my Verilog simulation installation problem by just giving up entirely
on  Modelsim, both the eval version I got from Model Technology and the
webpack version. Instead, I have started reading 4-star books on Verilog
(RTL   verifiable) synthesis and testbench writing.The Verilog books are
showing me  a *lot* of synthesis gotcha's (many of which I *still* don't
understand even after reading the explanation!) in Verilog code that I
would not have figured out on my own, so I think the time spent reading
is well spent. I'm now about to start reading Ashendon's 2nd edition VHDL book.

 I have installed Silos3 and will use that for simulation when I actually
get around to trying to simulate some code.I'll use the webpack fpga
tools when I'm ready to try to download code to my Spartan-II
and Virtex-II eval boards.

I also am getting interested in working with Icarus although that is
possibly complicated by my running Windows. I'd rather have a version
I can compile with Visual Studio 6 (either as a project or with a make
file) and run Icarus natively on Windows  than use Cygwin (which I
have tried) although running Icarus in a  Linux box under VMWare is possible.




"Dave Colson" <dscolson@rcn.com> wrote in message news:3B83BA2A.C0299BB4@rcn.com...
> Dave,
>
> I have had problems too. I am using the Xilinx version of Modelsim.
> The problem is with the Flexlm software recognizing the Ethernet card
> MAC
> under windows 2000.




Article: 34381
Subject: Virtex-II place and route : Design doesn't route
From: "Completely Fazed" <ozairusmani@mailcity.com>
Date: Wed, 22 Aug 2001 16:31:53 -0700
Links: << >>  << T >>  << A >>
Hi,

When I pass my design through Place & Route, the tool gives me an error. "125712 signals were not completely routed." I dug into all the log files and reports. Drew a zero. The tool doesn't mention why it could not route the signals.

Any help would be appreciated.

Article: 34382
(removed)


Article: 34383
Subject: Re: Virtex-II place and route : Design doesn't route
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Thu, 23 Aug 2001 01:50:05 +0100
Links: << >>  << T >>  << A >>
May be easier to diagnose with less than 125,000 signals :)
Try P&R on a small part of your design, with a very slack
clock spec.

"Completely Fazed" <ozairusmani@mailcity.com> wrote in message
news:ee72118.-1@WebX.sUN8CHnE...
> Hi,
>
> When I pass my design through Place & Route, the tool gives me an error.
"125712 signals were not completely routed." I dug into all the log files and
reports. Drew a zero. The tool doesn't mention why it could not route the
signals.
>
> Any help would be appreciated.



Article: 34384
Subject: Re: Logic Emulation
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Wed, 22 Aug 2001 18:57:54 -0600
Links: << >>  << T >>  << A >>
Falk Brunner wrote:
>AHHHHH, there it is again, the ugly word.
> 
> GATED CLOCKS!!!
> 

 LATCHES TOO !!!
 
 Ben.
PS. Core Memory!

-- 
Standard Disclaimer : 97% speculation 2% bad grammar 1% facts.
"Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
Now with schematics.

Article: 34385
Subject: Why this mismatches in simulation and sysnthesis results ?
From: "A. I. Khan" <aikhan@chat.carleton.ca>
Date: 23 Aug 2001 02:07:25 GMT
Links: << >>  << T >>  << A >>
Hi All !

If I declare the input or output port (in this example input is
considered) like the following two ways:-

1)

module X (m,..,..,..)
   input m;
   .........
   wire [7:0] m;
            ...............


2)
module X (m,..,..,..)
   input [7:0] m;
            ...............

where "m" is a 8 bit input. Modelsim works fine for both of the cases
and gives same result - it gives a bus of width 8 bit in simulation. Now
my problem is  in Synthesis with Xilinx Foundation Series, for Virtex E,
while I check the signal I find "m" as a one bit input for CASE-1.
CASE-2 works fine i.e it gives 8 bit input. Moreover it increases the
gate count dramatically when the Case-2 is used.

My question is why this mismatches in synthesis since both of the coding
styles are ok ? Any idea/answer would be appreciated.

Thanks in advance,

"Khan"








Article: 34386
Subject: Re: Slowing PCI for FPGA
From: "Austin Franklin" <austin@87darkroom.com>
Date: Thu, 23 Aug 2001 00:10:32 -0400
Links: << >>  << T >>  << A >>
> Its very common for people to emulate ASIC designs in FPGAs and its very
> common that they can only be run at a fraction of the clock speed that
> the ASIC runs at.

I believe most most everyone knows that.  I've done quite a few my self.

> To all the people advocating that he use an off the
> shelf PCI interface in the FPGA or giving advice on how to better code
> the state machines for the FPGA, while being good advice for a "from
> scratch" PCI design in an FPGA, I think you're missing the point.

The original post did not state that an ASIC emulation was what was being
done, so the follow-up suggestions were entirely appropriate.  Here is the
original post:

">I am doing a prototype with a PCI interface and there isn't a prayer of
>making it work at 25mhz bus transfer (my slowest machine available)
>without a lot of effort. What would you do to easily slow things down?"

I'd suggest before telling people that they are "missing the point", you
might want to take a look at exactly what "point" prople were answering.

>  He has
> to keep the FPGA RTL the same as the ASIC RTL or else he is not verifying
> the ASIC design, which is the goal.

As I said, I believe most everyone understands that, now that the
appropriate information has been "divulged".




Article: 34387
Subject: Re: Why this mismatches in simulation and sysnthesis results ?
From: "Kevin Neilson" <kevin_neilson@removethis-yahoo.com>
Date: Thu, 23 Aug 2001 04:14:12 GMT
Links: << >>  << T >>  << A >>
These two cases aren't equivalent.  You still have to specify the input bus
width in case 1.  Since you've specified no width, the input is one bit.
You have an 8-bit bus within the module, but only one bit coming in.  The
reason the gate count is decreased in case 1 is because the synthesizer
pruned all logic connected to the other seven bits of the bus since they
don't connect to anything outside the module.

"A. I. Khan" <aikhan@chat.carleton.ca> wrote in message
news:3B84654D.9B8FFCE9@chat.carleton.ca...
> Hi All !
>
> If I declare the input or output port (in this example input is
> considered) like the following two ways:-
>
> 1)
>
> module X (m,..,..,..)
>    input m;
>    .........
>    wire [7:0] m;
>             ...............
>
>
> 2)
> module X (m,..,..,..)
>    input [7:0] m;
>             ...............
>
> where "m" is a 8 bit input. Modelsim works fine for both of the cases
> and gives same result - it gives a bus of width 8 bit in simulation. Now
> my problem is  in Synthesis with Xilinx Foundation Series, for Virtex E,
> while I check the signal I find "m" as a one bit input for CASE-1.
> CASE-2 works fine i.e it gives 8 bit input. Moreover it increases the
> gate count dramatically when the Case-2 is used.
>
> My question is why this mismatches in synthesis since both of the coding
> styles are ok ? Any idea/answer would be appreciated.
>
> Thanks in advance,
>
> "Khan"
>
>
>
>
>
>
>
>



Article: 34388
Subject: Re: Virtex-II place and route : Design doesn't route
From: Ivar <ivar@stantech.dk>
Date: Wed, 22 Aug 2001 22:47:59 -0700
Links: << >>  << T >>  << A >>
Hi

It seems that you may have a hanging net. If so, all the logic "connected" to that net are "optimized" away.

Best regards

Ivar

Article: 34389
Subject: Re: Logic Emulation
From: Thomas Stanka <Thomas.Stanka@de.bosch.com>
Date: Thu, 23 Aug 2001 08:43:39 +0200
Links: << >>  << T >>  << A >>
Falk Brunner wrote:
> Can someone tell, how common they truely are? Are there special tecnics
> that simpifies verification of gated clocks?

You should never use gated clocks unless you design low power. As
low-power-designs are still increasing I guess, that gated clocks get
more and more state-of-the-art.

bye Thomas

-- 
Thomas Stanka	    
Bosch SatCom GmbH                         BC/EMD4
D-71522 Backnang      	   Tel. +49 7191 930-1690
Gerberstr. 49             Fax. +49 7191 930-21690      
Zi. 10/528             Thomas.Stanka@de.bosch.com

Article: 34390
Subject: Re: Confusion around BUS LVDS in Virtex-II
From: "Hakon Lislebo" <etohliNOSPAM@eto.ericsson.se>
Date: Thu, 23 Aug 2001 09:12:15 +0200
Links: << >>  << T >>  << A >>
I got an answer from Xilinx:

Unfortunately, Bus LVDS is not well documented right now for Virtex-II.
Virtex-II uses true current drivers for the LVDS. This is the 'traditional'
way of implementing LVDS.  However, Bus LVDS cannot be supported this way,
but this has not yet made it's way into the documentation.

So the physical implementation of Bus LVDS is identical to Virtex-E and so
all parameters are the same as Virtex-E as are termination requirements. The
cell to use for Bus LVDS is:

component IBUFDS_BLVDS_25
   port(
      O                              : out   STD_ULOGIC;
      I                              : in    STD_ULOGIC;
      IB                             : in    STD_ULOGIC);
end component;


Thank you you.
Hakon


Hakon Lislebo <etohliNOSPAM@eto.ericsson.se> wrote in message
news:9lvmsi$l5t$1@newstoo.ericsson.se...
> Hi,
> I trying to implement an BUS LVDS interface with Virtex-II, but I am
getting
> a little confused. In the document
> http://www.xilinx.com/products/virtex/handbook/ug002_ch2_lvds.pdf it is
said
> that you still have to use the IOBUF_LVDS primitive (I have used this in
> Virtex-E) for blvds. BUT this is not recognized by ngbuild. I have seen
some
> documentation that points to other primitives like IOBUFDS together with
an
> IOSTANDARD attribute.
>
> My questions is as follows:
> 1. What primitive should I use for buslvds applications?
> 2. Is the voltage swing on the bus still +/- 350mV with 2 x 100 Ohms
> terminations using blvds? (The datasheet confuses me and have spec's on
> LVDS, not BLVDS.)
>
> Thank you for reading!
> Regards Hakon Lislebo
>
>



Article: 34391
Subject: xchecker under Linux
From: <khtsoi@pc90026.cse.cuhk.edu.hk>
Date: 23 Aug 2001 10:42:00 GMT
Links: << >>  << T >>  << A >>
Hi,

I am wondering if there is any Linux/Unix program/sample can
download a bit file to Xilinx FPGA (xcv600) through xchecker
using PC COM port. Source code is prefered. Or any related
documents/standards are also welcome (we will do it ourselves
if need and the product will be under GPL). Thanks in
advance!

---- Brittle

Article: 34392
Subject: SmartMedia
From: "Andrew Gray" <andrew@tuks.co.za>
Date: Thu, 23 Aug 2001 16:25:39 +0200
Links: << >>  << T >>  << A >>
Hi

Does anyone know how to read a file from a SmartMedia card in VHDL?

Andrew



Article: 34393
Subject: XHWIF for XESS boards
From: Lorinc Antoni <Lorinc.Antoni@imag.fr>
Date: Thu, 23 Aug 2001 16:26:28 +0200
Links: << >>  << T >>  << A >>
Hello,

I'd like to ask you if someone among you has used JBits and XHWIF with
XESS boards, like XSV50.
I'm trying to do this, but there's a problem with the XHWIF, although I
created it in the way it is described in the manual. Is anyone who
managed to port the XHWIF (and JBits) to an XESS Virtex board?

Thansk very much for your help!

Regards,
Lorinc

Article: 34394
Subject: Latest Maxim bit serializer-deserializer chip announcements
From: "Dave Feustel" <dfeustel1@home.com>
Date: Thu, 23 Aug 2001 15:01:22 GMT
Links: << >>  << T >>  << A >>

DUAL-RATE, 1Gbps/2Gbps FIBRE CHANNEL QUAD-PORT BYPASS ICs WITH REPEATER

The MAX3754/MAX3755 quad-port bypass circuits (PBCs) are designed for
use in Fibre Channel Arbitrated Loop applications. Each consists of
four serially connected port bypass circuits and a repeater that
provides clock and data recovery. The quad-PBC allows connection of
up to four Fibre Channel L-ports; each can be enabled or bypassed by
individual logic inputs. To reduce the external parts count, all
signal inputs and outputs have internal termination resistors. The
MAX3754/MAX3755 comply with Fibre Channel jitter tolerance
requirements and can recover data signals with up to 0.7 unit
intervals (UIs) of high-frequency jitter. These devices operate from
a single +3.3V supply.
   More: http://dbserv.maxim-ic.com/quick_view2.cfm?qv_pk=3060

----------------------------------------------------------------------

1:2 DIFFERENTIAL LVPECL/LVECL/HSTL CLOCK AND DATA DRIVERS

The MAX9320/MAX9320A are low-skew, 1-to-2 differential drivers
designed for clock and data distribution. The input is reproduced at
two differential outputs. The differential input can be adapted to
accept single-ended inputs by applying an external reference voltage.
   More: http://dbserv.maxim-ic.com/quick_view2.cfm?qv_pk=3052

----------------------------------------------------------------------

1:10 DIFFERENTIAL LVPECL/LVECL/HSTL CLOCK AND DATA DRIVERS

The MAX9311/MAX9313 are low-skew, 1-to-10 differential drivers
designed for clock and data distribution. These devices allow
selection between two inputs. The selected input is reproduced at 10
differential outputs. The differential inputs can be adapted to
accept single-ended inputs by connecting the on-chip VBB supply to
one input as a reference voltage.
   More: http://dbserv.maxim-ic.com/quick_view2.cfm?qv_pk=3050

----------------------------------------------------------------------

10-BIT BUS LVDS DESERIALIZERS

The MAX9206/MAX9208 deserializers transform a high-speed serial bus
low-voltage differential signaling (BLVDS) data stream into
10-bit-wide parallel LVCMOS/ LVTTL data and clock. The deserializers
pair with serializers such as the MAX9205/MAX9207, which generate a
serial BLVDS signal from 10-bit-wide parallel data. The
serializer/deserializer combination reduces interconnect, simplifies
PC board layout, and reduces board size.
   More: http://dbserv.maxim-ic.com/quick_view2.cfm?qv_pk=3055


----------------------------------------------------------------------

LOW-POWER, COMPACT 2.5Gbps/2.7Gbps CLOCK-RECOVERY AND DATA-RETIMING IC

The MAX3873 is a compact, low-power 2.488Gbps/2.67Gbps clock-recovery
and data-retiming IC for SDH/SONET applications. The phase-locked
loop (PLL) recovers a synchronous clock signal from the serial NRZ
data input. The input data is then retimed by this recovered clock,
providing a clean data output. The MAX3873 meets all SDH/SONET jitter
specifications, does not require an external reference clock to aid
in frequency acquisition, and provides excellent tolerance to both
deterministic and sinusoidal jitter. The MAX3873 provides a PLL
loss-of-lock (LOL-bar) output to indicate whether the CDR is in lock.
The recovered data and clock outputs are CML with on-chip 50 back
terminations on each line. The clock output can be powered down if
not used.
   More: http://dbserv.maxim-ic.com/quick_view2.cfm?qv_pk=3064


----------------------------------------------------------------------

DUAL 1:5 DIFFERENTIAL LVPECL/LVECL/HSTL CLOCK AND DATA DRIVERS

The MAX9312/MAX9314 are low skew, dual 1-to-5 differential drivers
designed for clock and data distribution. These devices accept two
inputs. Each input is reproduced at five differential outputs. The
differential inputs can be adapted to accept single-ended inputs by
connecting the on-chip VBB supply to one input as a reference voltage.
   More: http://dbserv.maxim-ic.com/quick_view2.cfm?qv_pk=3051

----------------------------------------------------------------------

http://www.maxim-ic.com.




Article: 34395
Subject: Re: Slowing PCI for FPGA
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Thu, 23 Aug 2001 17:17:47 +0100
Links: << >>  << T >>  << A >>


Austin Franklin wrote:

>

> I'd suggest before telling people that they are "missing the point", you
> might want to take a look at exactly what "point" prople were answering.
>
> >  He has
> > to keep the FPGA RTL the same as the ASIC RTL or else he is not verifying
> > the ASIC design, which is the goal.
>

Even allowing for that I think there's a serious issue underlying this ...

>
> As I said, I believe most everyone understands that, now that the
> appropriate information has been "divulged".

As the poster said he's trying to using some collection of - large - FPGAs to
prototype/verify an ASIC. IMO these two words do not mean the same thing in
this context and I think we can make a kind of distinction:

o verify: As the poster & Richard I. said this means putting the code into an
FPGA exactly as it will be - at least at RTL - in the ASIC. Under these
circumstances some speed degradation maybe acceptable although personally I
would say worse than 2:1 is beyond what I'd accept.

o prototype: Here the biggest issue is probably to allow s/w development to go
ahead on a representative platform and, after sign off, to continue development
while the ASIC process grinds on - possibly even shipping some early FPGA
protos to customers. Here I would say we are in a reversed situation where the
FPGA based system leads development, with all the flexibility that implies, and
the ASIC implements the FPGA code at the point the s/w engineers & marketing
are happy with performance.

IMO (again) under the "prototype" idea FPGA system performance is important and
the answer to the original post would be as I did i.e. design an FPGA PCI i/f
at full 33MHz speed.


Article: 34396
Subject: Re: Logic Emulation
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Thu, 23 Aug 2001 18:25:40 +0200
Links: << >>  << T >>  << A >>
Tim schrieb:
> 
>    Gated clocks in ASICs, less common in FPGAs

AHHHHH, there it is again, the ugly word.

GATED CLOCKS!!!

Jehova, Jehova, Jehova. ;-))

Can someone tell, how common they truely are? Are there special tecnics
that simpifies verification of gated clocks?

-- 
MFG
Falk


Article: 34397
Subject: Actel Pad locations
From: "Patrick Dano" <patrick.dano@esionnetworks.com>
Date: Thu, 23 Aug 2001 16:41:50 GMT
Links: << >>  << T >>  << A >>
Hi All,

Does anyone know how to associate pin location with pad location in Actel
FPGA's (ie, what pins are associated to what pads), specifically the
A500K130-456?  The documents I have are missing some figures, and I cant
find anything on their web page.

Also, is there an FAQ for this group?

Thanks,

Pat



Article: 34398
Subject: DRAM burst mode
From: "Speedy Zero Two" <david@manorsway.freeserve.co.uk>
Date: Thu, 23 Aug 2001 18:17:53 +0100
Links: << >>  << T >>  << A >>
Hi All,

I can read and write data using a fpga and dram but have no information on
how to use the burst mode.
Has anyone got any information that could help me?

I know that I need to change the mode and then assert the burst command but
do not have any of the mode information.

Intel used to have a good page but it has since been removed and I never
downloaded the pdf (DOH)


Cheers in advance
Dave





Article: 34399
Subject: Re: Optical Bay Area Start-up! SW/HW Engs needed
From: "Andy Peters <andy [@] exponentmedia" <".> com">
Date: Thu, 23 Aug 2001 17:25:34 GMT
Links: << >>  << T >>  << A >>
Hey, Mr. Headhunter:

1) Stop posting off-topic ads in this newsgroup -- nowhere in your ad
did you mention the four magic letters "F-P-G-A"

2) Stop posting HTML-formatted crap.  Figure out how to properly
configure your news-posting software.

3) Go away.

> "Todd M. Caplan" wrote:
> 
>           PLEASE REFER TO THE REFERENCE NUMBER WHEN APPLYING
> 
>                          Current as of 8/21/01
> 
> ASIC Verification Engineer - AM101 Responsible for system level
> verification. Develop methodology, design and document verification
> plan, and set up test infrastructure. Write directed and random test
> cases, and analyze results. Requires BSEE/CS or equivalent and 5+
> years experience. Must have experience with Verilog and C programming.
> Experience with ATPG is a plus, as is experience in one or more of the
> following areas: Routing/switching technology, telecom/datacom,
> LAN/WAN networking.
> 
> ASIC Verification Engineer- AM102 Responsible for design verification.
> Specify and write verification tests for complex, high-speed ASIC
> devices. Specify and develop test methods, both at module and system
> levels. Requires BSEE/CS or equivalent, and 3+ years experience.
> Knowledge of Verilog, C/C++ and UNIX is preferred.
> 
> ASIC Design Engineer- AM103 Responsible for digital/ASIC design.
> Micro-architect and design complex, high speed ASICs for networking
> applications. Contribute as a team member to the architecture,
> specification, design, verification, testability, and product
> introduction. Requires experience with Verilog, Synopsys, and UNIX.
> Requires BSEE/CS or equivalent, and 8+ years experience in digital
> design.
> 
> ASIC Design Engineer - AM104 Responsible for digital/ASIC design.
> Contribute to device specification, RTL coding, and functional
> verification. Requires MSEE, and 5+ years experience in SONET/SDH, ATM
> and POS. Other responsibilities may include synthesis and back-end
> support.
> 
> Sr. Analog/Mixed Signal IC Design Engineers - AM106 Responsible for
> design and implementation of analog/mixed signal integrated circuits.
> Candidate must have prior design experience in transceivers, PLLs and
> VCOs and low noise amplifiers in CMOS, BiCMOS or Bipolar technologies.
> Experience with high-speed IO techniques, SONET and opto-electronics a
> plus. Requires BSEE or equivalent and 7+ years experience in
> analog/mixed signal IC design. Knowledge of Cadence Analog Artist,
> Spectre, Verilog A and Matlab is desired.
> 
> Analog/Mixed Signal IC Design Engineers - AM107 Responsible for design
> and implementation of analog/mixed signal integrated circuits.
> Candidate must have prior design experience in transceivers, PLLs and
> VCOs and low noise amplifiers in CMOS, BiCMOS or Bipolar technologies.
> Experience with high-speed IO techniques, SONET and opto-electronics a
> plus. Requires BSEE or equivalent and 3+ years experience in
> analog/mixed signal IC design. Knowledge of Cadence Analog Artist,
> Spectre, Verilog A and Matlab is desired.
> 
> Software IP Routing Engineer -AT003SD Requires implementation
> experience of OSPF, BGP and multicast routing protocols. Embedded
> software development is preferred. Requires at least 10 years relevant
> industry experience. MSCS or equivalent is required. Familiarity with
> MPLS is strongly preferred. Prior experience as a technical lead is
> preferred
> 
> Software Lead Engineer , Multi-Service Access -AT019BC The
> manager/Team Leader will be responsible for the development of
> software for ATM, Frame Relay, TDM interface cards in Optical Router.
> The specific responsibility include:
> 
> Lead and participate in the product definition, design,
> implementation, and testing of ATM, Frame Relay, TDM, and DSL
> interface cards. Recruit and build a software design team. Design and
> implement key software components.
> 
> Qualifications:
> 
>    * 8 years Telecom/networking experiences with BS CS/EE, or 6 years
>      with MS CS/EE.
>    * 2+ years direct team leading/management experiences in the
>      developments of Multi-Service
>    * Access Concentrators, ATM switches, DSLAMs, M13 Mux, or similar
>      products.
>    * Working experiences on ATM signaling, Call Control, Traffic
>      Management, ILMI/LMI, Frame
>    * Relay &ndash; ATM interworking, and FUNI.
>    * Working experiences on DSL, T1/E1, T3/E3, OC-3 interfaces.
>    * Working experiences with RTOS, such as VxWorks, pSOS.
>    * Working experiences with MPC 860, 850, 8260, or MIPS
>    * Working knowledge with networking device drivers.
>    * Working knowledge with chip sets for ATM, Frame Relay, and TDM
>      interfaces.
>    * Working knowledge on protection switching, redundancy, IP, SONET,
>      and DWDM.
> 
> Sr. Software and/or Hardware  Engineer, Fibre Channel - Req No: E5 The
> engineer will be responsible  for the higher level system architecture
> of design, coding and verification of the Fibre Channel protocol stack
> and Fibre  Channel system  on a family of  next generation proprietary
> communication  ICs.  The  engineer  will work  with  the  rest of  the
> software and  hardware engineering  team to design  and implement high
> performance  SOC (System-on-Chip)  ICs  to address  a variety  of high
> bandwidth challenges. The majority  of the implementation will be in C
> with the  potential for  some assembly coding of  critical sections of
> code.
> 
> Job Requirements: The engineer(s) in the position must have complete
> understanding of the applications and use of all framing bytes as well
> as hands-on experience implementing and porting of Fibre Channel
> protocol stacks in an embedded environment. Experience with other
> related protocols and device drivers is strongly desired. Engineers in
> this position will be strong in software fundamentals and strong
> problem solving skills. Strong writing and communication skills are
> necessary to be effective in this position.
> 
> Candidate Requirements: PhD, MS or BS in Computer Science or
> Electrical Engineering with 4-8 years industry experience. Minimum
> requirement of 2 years direct hands-on experience with protocol
> stacks. Project lead experience, Linux or Windows 2000 driver
> experience, other communication protocols and Real Time Operations
> Systems (RTOS) is strongly desired. . Knowledge of TCP/IP, Gigabit
> Ethernet, Fibre Channel, SCSI, Infiniband, POS-PHY architecture is a
> plus. Candidates with less than required experience may be considered
> for junior level positions if available.
> 
> Sr. Design Engineer - Req No: E02 The candidate will be a part of team
> designing next generation of communication ICs. Study the chip
> specification and take part in the partitioning into functional
> modules. Develop RTL coding of the function. Create verification
> environment, run simulation, analyze results. Perform Synthesis,
> formal verification RTL-gates and timing verification. Implement DFT
> strategy and generate production vectors. Provide support during the
> layout process. Active participation in defining new innovations in
> ASIC technology and methodology.
> 
> Candidate  Requirements MS  or BS  in Electrical Engineering  with 4-8
> years industry experience Knowledgeable of the whole digital ASIC flow
> and proven  experience in  the front-end design area.  Exposure to SoC
> design and  low-power design techniques. The  candidate must have very
> good verbal and written  communication skills, a high motivation and a
> good team player. Knowledge  of TCP/IP, Ethernet, Fiber Channel, SCSI,
> Infiniband, POS-PHY architecture is  a plus. Candidates with less than
> required experience  may be  considered for junior  level positions if
> available.
> 
> Sr. Verification Engineer - Req No: E03 Setup environment to verify
> SoC design with embedded processors. Define modular verification
> architecture to test various IPs. Create test-plan and regression
> suites. Provide guidance to other junior verification engineers.
> 
> Candidate Requirements : Knowledgeable of the  whole digital ASIC flow
> and proven experience in  verification of complex ICs. Exposure to SoC
> designs verification  with embedded processors is  a plus. Exposure to
> Verilog-PLI,   code-coverage   tools.,   C-programming,  perl,   shell
> programming is  required. Experience  with VHDL-Verilog co-simulation,
> SCSI,  Fibre Channel,  TCP/IP, Ethernet,  POS-PHY standard would  be a
> plus.  The   candidate  must   have  very  good   verbal  and  written
> communication skills. Looking for  a person having high motivation and
> who is  a good team player. Candidate must  possess a BS/MS EE/CS with
> 4-8  years relevant  experience.  Candidates with  less than  required
> experience may be considered  for junior level positions if available.
> 
> Sr. Software Engineer, SCSI Protocol - Req No: E4 The engineer will be
> responsible for  the design, coding and  verification of SCSI protocol
> stacks on  a family of next  generation proprietary communication ICs.
> The  engineer will  work with  the rest  of the software  and hardware
> engineering  team  to  design   and  implement  high  performance  SOC
> (System-on-Chip)  ICs   to  address   a  variety  of   high  bandwidth
> challenges. The  majority of the implementation will  be in C with the
> potential  for  some assembly  coding  of critical  sections of  code.
> 
> Job Requirements: Software engineers in the position must have
> hands-on experience implementing and porting of SCSI protocol stacks
> in an embedded environment. Experience with other related protocols
> and device drivers is strongly desired. Engineers in this position
> will be strong in software fundamentals and strong problem solving
> skills. Strong writing and communication skills are necessary to be
> effective in this position.
> 
> Candidate Requirements: PhD, MS or BS in Computer Science or
> Electrical Engineering with 4-8 years industry experience. Minimum
> requirement of 2 years direct hands-on experience with protocol
> stacks. Project lead experience, Linux or Windows 2000 driver
> experience, other communication protocols and Real Time Operations
> Systems (RTOS) is strongly desired. . Knowledge of TCP/IP, Gigabit
> Ethernet, Fibre Channel, SCSI, Infiniband, POS-PHY architecture is a
> plus. Candidates with less than required experience may be considered
> for junior level positions if available.
> 
> Sr. Software Engineer, TCP/IP Protocol - Req No: E01 The engineer will
> be responsible for the design, coding and verification of TCP/IP
> protocol stacks on a family of next generation proprietary
> communication ICs. The engineer will work with the rest of the
> software and hardware engineering team to design and implement high
> performance SOC (System-on-Chip) ICs to address a variety of high
> bandwidth challenges. The majority of the implementation will be in C
> with the potential for some assembly coding of critical sections of
> code.
> 
> Job Requirements: Software engineers in the position must have
> hands-on experience implementing and porting of TCP/IP network
> protocol stacks in an embedded environment. Experience with other
> related protocols and device drivers is strongly desired. Engineers in
> this position will be strong in software fundamentals and strong
> problem solving skills. Strong writing and communication skills are
> necessary to be effective in this position.
> 
> Candidate Requirements: PhD, MS or BS in Computer Science or
> Electrical Engineering with 4-8 years industry experience. Minimum
> requirement of 2 years direct hands-on experience with TCP/IP protocol
> stacks. Project lead experience, Linux or Windows 2000 driver
> experience, other communication protocols and Real Time Operations
> Systems (RTOS) is strongly desired. . Knowledge of TCP/IP, Ethernet,
> Fiber Channel, SCSI, Infiniband, POS-PHY architecture is a plus.
> Candidates with less than required experience may be considered for
> junior level positions if available.
> 
> Manager or Lead/Senior Software Engineer MAN/WAN Fiber Channel
> solutions -AT0025BC
> 
> Lead the development effort in the area of storage solutions
> architecture. Responsible for product definition, design,
> implementation of fiber channel and other storage service cards for
> metro optical platforms.
> 
> Job Requirements: BSEE/CS with 8 years software design experiences. 3+
> years experiences in Fiber Channel switch software design. Hands on
> experiences with FC Switch Fabric, Arbitrated Loops, and Generic
> Services.
> 
> Familiar with FC-AL-n, FC-SW-n, and FC-GS-n standards. Team worker.
> 
> Good Communication and Presentation Skills. Knowledge of telecom and
> networking technologies, such as IP, ATM, SONET, DWDM, Ethernet is
> highly desirable. Past experience as a technical team lead would be a
> plus.
> 
> Senior Software Engineer, ATM, Frame Relay- AT020BC The specific
> responsibilities include: Design, implement, and test software for
> ATM, Frame Relay, and DSL cards.
> 
> Qualifications: 5 years industrial experiences with BS CS/EE, or 3
> years experiences with MS CS/EE. 3+ years direct experiences in
> software development ATM and/or Frame Relay. Working experiences with
> ATM/FR Signaling, switch fabric control, device drivers, ILMI/LMI, or
> traffic management. Experiences with RTOS, such as VxWorks, pSOS. Team
> Player with good communication skills. Experiences with ATM/FR
> switches, Multi-service Access Concentrators, or DSLAMs. IP or SONET
> experiences. Automatic Protection Switching and Redundancy
> Experiences. Team Leading experiences
> 
> Senior Product Marketing Manager - ATG003GM This position entails
> product lifecycle management including product requirements planning,
> feature definition and prioritization, strategic sales support, and
> product promotion. Requires prior product management experience in
> carrier-class networking products and a strong technical knowledge in
> some or all of the following areas: IP routing, SONET and DS3, DS1 TDM
> subscriber services. 3-5 years related experience. BSEE a plus.
> 
> *********************************
> Todd M. Caplan
> HiTech Communications Inc.
> Post Office Box 4952
> El Dorado Hills, CA 95762
> Wk: 916-941-8355
> Fax: 916-941-8068
> E-Mail: todd@hitechcomm.com
> WWW: http://hitechcomm.com
> *********************************
> 
> 
> 
>                                        Name: News Groups-Job
>                                              Descriptions.doc
>    News Groups-Job Descriptions.doc    Type: Microsoft Word Document
>                                              (application/msword)
>                                    Encoding: base64



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