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Messages from 29350

Article: 29350
Subject: Re: Configuration of FPGA using SPROM
From: Mark Momcilovich <mark_momcilovich@bose.com>
Date: Thu, 15 Feb 2001 15:36:48 GMT
Links: << >>  << T >>  << A >>
Radhika:
  It is easy to have initial config. problems with the Atmel 17Cxxx parts because of the programmable Reset/OE pin.  Our Data I/O Unisite had a procedure for properly setting the polarity of this pin.
  But, now that you have the LDC and DONE going high it sounds like a possible design problem in your code.  What does your code look like?
Regards,
Mark Momcilovich

radhika wrote:

> hi chris!
>  Thank you for the information.I am sorry to trouble you again - in our configuration we found that INIT signal is initially going low during configuration and when it is switching to high both the LDC and the DONE pins are going high indicating configuration of FPGA.But we find that the output is erroneous.We would appreciate if you could help us.
> sincerely
> radhika


Article: 29351
Subject: Re: Bubble tristate
From: Laurent Gauch <laurent.gauch@amontec.com>
Date: Thu, 15 Feb 2001 17:13:55 +0100
Links: << >>  << T >>  << A >>
Ulises,

"bubble_tristate" is a great option. This option allows you to describe 
your VHDL tristate port everywhere in you design, working with a 
hierarchical VHDL design. :-)

(without this option, you need to make sure your VHDL tristate port is 
described in your top level design, or make sure to work with a flatten 
design (for that , use flatten in Spectrum) :-) )

Regards,

Laurent for Amontec
www.amontec.com
-------------------
Amontec introduces a new low cost PCI Development System
BUILD YOUR OWN PCI CARD IN 2 WEEKS




Ulises Hernandez wrote:

> Hi,
> 
> I would like to know what I can get in a Spartan II if I set the attribute
> "bubble_tristate" to TRUE in Leonardo Spectrum.
> 
> Thank you.


Article: 29352
Subject: Re: Rijndael
From: Andy Peters <"apeters <"@> noao [.] edu>
Date: Thu, 15 Feb 2001 09:46:30 -0700
Links: << >>  << T >>  << A >>
How does one pronounce that word?

I'm originally from New Jersey, and we don't have words like that there!

--a

Article: 29353
Subject: Re: Wired-or on Virtex FPGAs
From: krw@btv.ibm.com (Keith R. Williams)
Date: Thu, 15 Feb 2001 17:26:37 GMT
Links: << >>  << T >>  << A >>
On Sun, 11 Feb 2001 22:00:55 GMT, "Jan Gray" <jsgray@acm.org> wrote:

>There's a nice example of a Virtex-carry-chain-optimized n-bit comparator in
>VHDL from Arrigo Benedetti in the fpga-cpu list archive, at
>http://groups.yahoo.com/group/fpga-cpu/message/73.

Very nice indeed!  Synplify says I cdan do a 12-bit comparitor at just
a hair under 200MHz (Virtex-E -7) with registers around it.  That
might be a bit slow for what I need, but not by much.  I modified it
slightly to do two XORs and an AND in the LUT (I have four inputs, why
waste two :-) before feeding the MUXCY and Synplicity reports 224MHz.
Nice indeed!  If true (and it wires nicely), I can cut a pipeline
stage out of my address compare.

Thanks for pointing this out!

----
  Keith R. Williams



Article: 29354
Subject: Re: Rijndael
From: "Eric Braeden" <braeden@erinet.com>
Date: Thu, 15 Feb 2001 13:09:42 -0500
Links: << >>  << T >>  << A >>
;-) Yea!!

    Try "Rhine Doll"


Andy Peters noao [.] edu> <"apeters <"@> wrote in message
news:96h16d$16h$3@noao.edu...
> How does one pronounce that word?
>
> I'm originally from New Jersey, and we don't have words like that there!
>
> --a



Article: 29355
Subject: Re: Configuration file of SpartanXL
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Thu, 15 Feb 2001 19:14:25 +0100
Links: << >>  << T >>  << A >>
Geert Van Doorselaer schrieb:
> 
> clock the XCLK line (196 * 8 ) times more.
> 
> Why is this? By looking further, I have found in the PROM File Formatter
> program this value 0x583F: File > Prom Properties > Data Streams > End
> Address. Why this value, and not 0x577B ?

Jeah right. After serial downloading your HEX file you have to drive
(toggle) CCLK until DONE goes high (Open drain!!). This is called
startup clock, because the initialization is not finished with just
downloading the HEX file.

-- 
MFG
Falk

Article: 29356
Subject: Re: Configuration file of SpartanXL
From: Philip Freidin <philip@fliptronics.com>
Date: Thu, 15 Feb 2001 12:04:26 -0800
Links: << >>  << T >>  << A >>
Time for me to get started on the FAQ pages. Still calling for
volunteers to help.

Your problems start with the version of the SW you are using. (V1.5)
There have been several releases over the last few years since
1.5. They are now up to 3.3.06i .  I ran a test design for you with
version 3.2.04i and I see several problems with what you have.

On Thu, 15 Feb 2001 11:05:04 +0100, "Geert Van Doorselaer"
<Geert.VanDoorselaer@elis.rug.ac.be> wrote:
>I have trouble understanding the generation of the configuration file of a
>Spartan20XL device.
>As I am using serial slave mode (configuration is not time critical, and
>mastered by a microcontroller), I started from a HEX file, generated by the
>PROM File Formatter (Version 1.5.25). This gives a HEX file of 44790 bytes,

My version is 44792, but close enough for now

>containing the 22395 configuration bytes I expect (as each character in the
>file represents a HEX character, only 4 configuration bits are represented
>in one HEX file byte).

Right.

>So far, no problem.

I agree

>But trying to configure my FPGA failed. However, INIT
>pin did not go down. I found out (but this took me a while) that I had to
>send (22561 * 8) bits (0x583F * 8 in hexadecimal notation) instead of the
>expected (22395 * 8) bits (0x577B * 8 in hexadecimal notation), although all
>the information is already in the first (22395 * 8) bits. I just have to
>clock the XCLK line (196 * 8 ) times more.

Which means the header has the wrong length count in it. Since I am
assuming that after your extra 196*8 clocks, done went high, this means
that all is ok except the length count.

>Why is this?

Length count is wrong. Probably an error in the version of your sw.

>By looking further, I have found in the PROM File Formatter
>program this value 0x583F: File > Prom Properties > Data Streams > End
>Address. Why this value, and not 0x577B ?

In my version, it is 0x577A , which given  the length of my HEX file
as 44792 (div by 2, cvt to hex is 577C) means the PROM will be loaded
with 577B bytes (remember to count byte 0 thru 577A -> 577B bytes),
so the last byte of the HEX file will not end up in the prom, but the last
two bytes are both pad bytes of FF, so it doesnt matter. So yours should
be the same but isnt. The 583F is definitely wrong.


>Also the first 5 bytes of my configuration file look quite strange to me:
>FF 2 02C1F9 F
>where I expect FF 2 00577B F.

I agree.

The value is a bit count, not a byte count, so not 577B, but
2BBD1  ( == 179153 )

Here is what the stuff should look like:

Note there is an option to swap bits in bytes, which you select depending
on whether you shift out bits from the PROM from the LSB or the MSB.
The default is ON, which is what you want if you shift out the LSB first.

If it is OFF, you must shift out the MSB first of each byte. Your FF 2 0...
indicates that you have it off, which is correct for the serial PROMs

SWAP OFF

HEX file start      ff202bbd1f5bfefebf
HEX file end      afebfafebfafe456ffff

PDR file:
# Created 2001/02/15 11:43:38
BeginProm
  Type   Serial
  Format HEX Unswapped
  FillValue FF
  Info MaxAddress 0x0000577A
  Device Auto HexFile
  BeginChain
    StartAddress    0x00000000
    Direction       UP
    Info EndAddress 0x0000577A
    Info Size       0x0000577B
    File "D:\2001\Xilinx_tests\test_S20XL\top.bit"
  EndChain
EndProm




SWAP ON

HEX file start      ff04d4bdf8da7f
HEX file end       5f7ffdf5276affff

PDR file:
# Created 2001/02/15 11:30:20
BeginProm
  Type   Serial
  Format HEX Swapped
  FillValue FF
  Info MaxAddress 0x0000577A
  Device Auto HexFile
  BeginChain
    StartAddress    0x00000000
    Direction       UP
    Info EndAddress 0x0000577A
    Info Size       0x0000577B
    File "D:\2001\Xilinx_tests\test_S20XL\top.bit"
  EndChain
EndProm

>Am I correct?

Yep. Things are bad, and it is the length count, in the HEX
file. But you can probably patch it to make it right !!

The definitive bitstream can always be seen by creating an RBT
file and looking at it. The bit sequence into the FPGA is exactly
the RBT file, read left to right (after skipping the header).

Here it is:

Xilinx ASCII Bitstream
Created by Bitstream D.23
Design name: 	top.ncd
Architecture:	spartanxl
Part:        	s20xltq144
Date:        	Thu Feb 15 11:21:43 2001
Bits:        	179160
1111111100100000001010111011110100011111
10110111111111011111110101111111010111111101 .... etc

As you can see, it is FF FF 20  2B BD 1F


Please take this response, and any additional notes you make,
and turn it into an HTML page for me to add to
the WWW.FPGA-FAQ.COM web site. This is the payment for help.

Mail it to me at philip@fpga-faq.com

Every one else: start writing those HTML pages and send them to me.
Please.


>Kind regards,
>Geert Van Doorselaer


Philip Freidin
Fliptronics

Article: 29357
Subject: Design of a divide by 6.5 counter ?
From: "mark" <markw@fiway.com>
Date: Thu, 15 Feb 2001 20:46:21 -0000
Links: << >>  << T >>  << A >>
Hi ,

    Being new to vhdl I have only ever designed integer counters, so could
someone tell me how you would design a synthesizable divide by 6.5 counter.


Thanks

Mark



Article: 29358
Subject: Xilinx GSR in Verilog simulations
From: Craig McAdam <craig@mysterio.freeserve.co.uk>
Date: Thu, 15 Feb 2001 22:29:32 +0000
Links: << >>  << T >>  << A >>
I'm trying to use the Xilinx global GSR signal in a SpartanII design
(according to Xilinx' own guidelines).

But I cannot get the values assigned to the global GSR signal to take
effect in other Verilog modules. As an example if I have a simple module
(check.v) and testbench (test.v) to try to observe the behaviour -

//testbench.v -
//this testbench is just to look at how the Xilinx global set/reset
works

`timescale  1 ns / 1 ps

module test();

  reg GSR;                //Global Set/Reset
  reg GTS;                //Global Tri-state
  assign glbl.GSR = GSR;
  assign glbl.GTS = GTS;

  check check();

  initial
    begin
      $dumpfile("test.vcd");
      $dumpvars;
      GSR = 1;
      GTS = 1;
      #100 GSR = 0;
      GTS = 0;
      #100 GSR = 1;
      GTS = 1;
      #100 GSR = 0;
      GTS = 0;
    end

endmodule

//check.v
//this module monitors the GSR global signal

module check();

  wire  GSR;            //Global Set Reset
  wire watch;
  reg check;

  assign watch = GSR;

  always @(GSR)
    begin
      check = GSR;
    end

endmodule

When I simulate this (Verilog-XL 3.0 running on NT) along with the
glbl.v module from Xilinx using something like

       verilog test.v check.v d:\xilinx\verilog\src\glbl.v

I can see that GSR and GTS in the testbench test.v are being driven
properly, GSR and GTS in glbl.v are being driven properly, but GSR in
check.v is never being driven.

Anybody know how to use these global signals properly ?

Thanks,

--

Regards, Craig

Article: 29359
Subject: Xilinx XC18v04 programming via FPGA
From: "Stan Ramsden" <sramsden@hoflink.com>
Date: Fri, 16 Feb 2001 02:32:21 GMT
Links: << >>  << T >>  << A >>
Here is the scenario:
I know this is not safe to do, but the board has been layed out and we are
stuck with what we have. I need to be able to program the XC18v04
configuration memory thru the configured FPGA using the non dedicated JTAG
pins.
Has anyone done such a design?



Article: 29360
Subject: Implementing a 64-bit/66MHz PCI controller
From: Kostas Marinis <kmarinis@netscape.net>
Date: Fri, 16 Feb 2001 09:41:56 +0200
Links: << >>  << T >>  << A >>
Greetings all,

my question relates to the difficulty/complexity of designing and
implementing a 64-bit/66MHz PCI master/target controller core in VHDL.
Could anybody give me an estimate on the amount of time/work such a task
would require to complete? I understand that this is a *very* general
question, and that it basically depends on the experience/ingeniuty/IQ
of the designer, the tools used, the target technology (try implementing
that in a MAX5000! :) and lots of other factors. A rough estimate would
suffice though (something in the form "assuming x years of
VHDL/FPGA/digital design experience, about y to z man-months"). 

There is basically no restriction on the target technology - assume the
fastest/largest device is available (a Virtex-II or Apex maybe?)
You can also assume that access to virtually all FPGA/VHDL tools
currently in the market is available.
Make any other reasonable assumptions you wish, but please state them
appropriately.
I would greatly appreciate it if you avoided answers like "just buy a
ready made core and forget about the whole thing"! ;-)

Thanks in advance,

Kostas
Article: 29361
Subject: Re: VHDL PID
From: "Blake Henry" <nobody@nowhere.com>
Date: Fri, 16 Feb 2001 08:04:05 GMT
Links: << >>  << T >>  << A >>
Yes, I am putting the finishing touches on one now.  It will be offered as
one of my company's products.  The datasheet is nearly complete but I would
be glad to get you a copy as it is.

You can also check out my web site at www.bitwisesys.com

Thanks.


EKC <NOSPAMalpha3.1@ix.netcom.com> wrote in message
news:6T0h6.1465$_B3.325418@dfiatx1-snr1.gtei.net...
>     Has anyone implemented a PID servo motion controller in VHDL? If so,
is
> there any code or documentation that I can look at?
>
> Thanks in advance,
>
> EKC
>
> alpha3.1 AT ix DOT netcom DOT com
>
>
>
>



Article: 29362
Subject: Re: Xilinx GSR in Verilog simulations
From: eml@riverside-machines.com.NOSPAM
Date: Fri, 16 Feb 2001 09:43:06 GMT
Links: << >>  << T >>  << A >>
On Thu, 15 Feb 2001 22:29:32 +0000, Craig McAdam
<craig@mysterio.freeserve.co.uk> wrote:

>I'm trying to use the Xilinx global GSR signal in a SpartanII design
>(according to Xilinx' own guidelines).
>
>But I cannot get the values assigned to the global GSR signal to take
>effect in other Verilog modules. As an example if I have a simple module
>(check.v) and testbench (test.v) to try to observe the behaviour -
>
>//testbench.v -
>//this testbench is just to look at how the Xilinx global set/reset
>works
>

Almost right, except that:

>module check();
>
>  wire  GSR;            //Global Set Reset

GSR here isn't the global GSR; it's just a local wire called GSR,
which is undriven. If you replace the points where you look at GSR
with references to 'glbl.GSR' then it'll work.

BTW, I find it easier to put the 'glbl' module in my own testbench;
this results in less messing around, and makes it more obvious what's
going on.

Evan

Article: 29363
Subject: Re: Rijndael
From: "Brendan Lynskey" <brendan.lynskey@pace.co.uk>
Date: Fri, 16 Feb 2001 10:30:51 -0000
Links: << >>  << T >>  << A >>
Sorry for the newbie question, but what is ECB-mode?

Thanks.

"Catalin Baetoniu" <starnet@home.com> wrote in message
news:3A8B5446.5706B508@home.com...
> Jabari,
>
> You seem to advocate non-pipelined designs but with the exception of
> non-ECB mode encryption there is no advantage to a non-pipelined design.
In
> Xilinx VitexE-8 FPGAs DES/3DES as well as AES pipelined designs can run at
> speeds of 150-200MHz (incuding key schedule) with one block processed
every
> cycle. This leads to levels of performance at least an order of magnitude
> higher than the ones you describe (including the GaAs asynchronous
design).
>
> A pipelined design will get you either a faster or at the same speed a
> smaller design compared to a non-pipelined implementation, which is just
an
> inneficient use of the hardware.
>
> Catalin Baetoniu
>
> jzakiya@mail.com wrote:
>
> > In article <qhhf28a7vv.fsf@ruckus.brouhaha.com>,
> >   Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote:
> > > jzakiya@my-deja.com writes:
> > > > I'm cofounder of a startup,
> > > >
> > > > ---- 3rdeye Technology, LLC ----
> > > >
> > > > We have patent-pending IP cores
> > > > that can do a number of encryption
> > > > algorithms as logic gate functions,
> > > > meaning, completely non-sequentially.
> > > > (DES, AES, Twofish, RC6, Serpent, SHA-1)
> > > > Thus, we can perform these algorithms
> > > > in just one process (clock) cycle,
> > > > versus multiple sequential cycles.
> > >
> > > Sure, one SUFFICIENTLY LONG clock cycle.  Care to quote cycle times
> > > for real FPGAs (or ASIC processes)?
> > >
> > > For most applications a pipelined implementation is much preferred,
> > > as you get much higher total throughput.  The exception is usually
> > > when you have a single stream of data to be encrypted in a feedback
> > > mode.
> > >
> > > I have no doubt that you'll get a patent (it's possible to get a
> > > patent on *anything*), but I'm curious as to what aspect of the
> > > encryption implementation you're patenting.  Surely you don't think
> > > that simply expanding the equations into a large combinatorial
> > function
> > > is in any way novel?  For instance, there have been many DES chips
> > > that implemented a single round combinatorially.  If you try to
> > flatten
> > > two rounds into a sum-of-products, it gets completely unmanageable,
> > > but you can simply chain multiple single-round combinatorial circuits
> > > to get what you describe.  It's just not particularly better than
> > > doing it the conventional way, with pipeline registers between the
> > > rounds.
> >
> > -------------------------------
> > We have compiled and simulated a 1DES design which can
> > both encipher/decipher in ECB mode in one device.
> > It was fitted in an EPF10K100EQC-208-1 and was simulated
> > with Altera Maxplus II 9.6 almost a year ago. It had a
> > worse case total propagation delay (TPD) for a complete block
> > of 155 ns. With current Altera and Xilinx devices, and
> > using newer (better) synthesis and place and route tools,
> > we can do under 100 ns in their small devices, and better
> > in their bigger devices.
> >
> > We were able to briefly use a gallium-arsenide ASIC library to
> > compile a full 1DES design, and its worse case TPD was under
> > 20 ns (~18 ns) (>50 MBlocks/s -> 3.2Gbits/s). This, again
> > is without pipelining, which allows these cores to easily
> > implement various design modes (ECB, CBC, ect) with the
> > minimalist amout of control logic and with the lowest
> > possible power consumption.
> >
> > A full 3DES design in an Altera or Xilinx (currently the
> > FPGA device families with the largest gate count chips)
> > should have a 3DES TPD of < 150 ns, based on their device
> > specifications.  ASIC designs in even .25 micron families
> > should do < 75-100 ns. and with .18-.13 micron CMOS devices
> > we project full 3DES TPDs around 50-75 ns.
> >
> > AES was a very good selection by NIST (National Institute of
> > Standards and Technology) as the AES algorithm from a
> > hardware implementation viewpoint.  Since it only requires
> > 10, 12, or 14 rounds (for 128, 192, and 256 bit keys) it
> > is relatively faster than DES, even though it's blcoksize
> > is twice as wide (128 vs 64 bits) and its key schedule is
> > much more involved.
> >
> > The full encipher/decipher chip for a 128-bit key which can
> > compile (unoptimized) into an Altera EP20K1500 device had a
> > simulated worse case TPD of about 200 ns with Quartus 2000.9
> > With the claimed better synthesis and place and route tools
> > of Quartus II, it should not only compile to be faster, but
> > we may also be able to compile a full 128-256 bit key design
> > in one device.
> >
> > But you must also realize, when I say **FULL** design, I mean
> > not only the cipher arithmetic is done non-sequentially, but
> > also the full key expansion (for AES) for each keysize is also
> > done non-sequentially, ALL IN ONE DEVICE!
> >
> > Our devices are the simplest encryption devices to design with,
> > requiring the least amount of external control logic to interface
> > to, which enables systems to be made with less parts (which lowers
> > total system costs), using less power, and which are faster than
> > all other sequential design EXCEPT highly pipelined designs, which
> > have all their attendant problems. In fact, you can pipeline our
> > design at the block level, versus the single cipher round function
> > level, and get better perfermance too.
> >
> > Also, for special purpose applications, such as for MACs, where
> > you only need the encipher function, we can make even faster devices
> > which will fit in smaller chips.  We can also strip out the key
> > expansion logic for AES if desired, if that function can be done
> > in software.
> >
> > The point is, their is a science to performing these algorithms
> > non-sequentially which is much more involved than stringing a
> > bunch of XOR gates together. And just like many things are
> > "obviious" AFTER someone has done it, our design methodology is
> > not very "obvious" especially since no one has done any of the
> > algorithms we have implemented in the manner we have AND with
> > their efficiency and utility.
> >
> > Again, for parties interested in learning more about our
> > technology and IP portfolio, please feel free to contact me.
> >
> > Jabari Zakiya
> > 3rdeye Technology, LLC
> > 703-608-9233
> > jzakiya@hushmail.com
> >
> > Sent via Deja.com
> > http://www.deja.com/
>



Article: 29364
Subject: Optimization problem with SPARTANII
From: Richard Meester <rme@quest-innovations.com>
Date: Fri, 16 Feb 2001 11:42:46 +0100
Links: << >>  << T >>  << A >>
Hello all,

I have a problem with the optimizer. I have created a design, which uses
a comparater to compare two 16bit values and see if a is less than b. I
have hooked up B to a constant value(i.e. vcc and ground). I have done
this also with an adder. When i do simulation all simulates well. When
implementing the design, the constant values are optimized with other
types of vcc and ground pins. The optimization of the adder goes OK, but
the optimization if the comparator results in a fact that all 16 bits
are tied to VCC, instead of the appropriate values. This resulting in a
wrong comparison. The comparison itself works, only obviously on the
wrong value. Does anyone have any idea. (for the comparator i use the
core generator comparator.) Is this perhaps a bug in the core, or in the
optimizer?

Thanks Richard

--
Quest Innovations
tel: +31 (0) 227 604046
http://www.quest-innovations.com



Article: 29365
Subject: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
From: Ed Ngai <engai@sprintmail.com>
Date: Fri, 16 Feb 2001 11:17:51 GMT
Links: << >>  << T >>  << A >>
To NG users, so what if a student asks questions. You all had to 
learn before. A student wants to cheat, then ok by me.  But
just wait till it's exam time and you get C,D,F ... so what.

Hi Marc, I can't see the jpg you posted,  but how about the NG
alt.binaries.schematics.electronics .  This NG was made just for
pics.  As to the problem, I can't help w/o a pic. You can use
just
letters, it dosen't have to be pic.  IS it like this?

A --+-- X
    |
    +-- y
    |
    +-- Z 

Anyway, I think you want to make a logic diagram w/ the gates you 
need to use, AND, NOT, NOR, etc,etc.
Condense your design to the smallest number of ICs you have to
use.
Convert you design to Able code or vhdl.
Xilinx's FREE WebPack, visit:
http://www.xilinx.com/products/software/webpowered.htm


Marc wrote:
>Hello,  I need to build a 'switching matrix'. (Please look at the
> picture to understand the message ). I must be able to 'route' the
> signal from port A to port X,Y or Z, and idem for B and C. If port X
> is used, it quite understandable that i wont be able to 'route' an
> other signal comming from port A.B or C there. The signal that i'll
> use is PCM clocked at the speed of "from 64Khz to 3Mhz". Each
> port has a TX and RX pin.
> 
>         Once a 'virtual' route is created, ( example, from port B to
> port Z ) i must be able to create a other 'route'  ( example, from
> port A to port Y ) without creating a glitch or noise to the first one
> already 'live'.For testing a 3x3 ports matrix is ok. but the next one
> will be around 30x30 ports matrix.
> 
>         My question is, which device can be the best for this
> kind of application, and , an idea how to build the concept of
> a matrix like that.
> 
>                         Regards,
> 
>                         Marc./
>                         S_mythicbird@hotmail.com
> 
> Ps: remove the S_ if you want to reply via email. Thanks.

Article: 29366
Subject: Re: Rijndael
From: krw@btv.ibm.com (Keith R. Williams)
Date: Fri, 16 Feb 2001 13:46:07 GMT
Links: << >>  << T >>  << A >>
On Fri, 16 Feb 2001 10:30:51 -0000, "Brendan Lynskey"
<brendan.lynskey@pace.co.uk> wrote:

>Sorry for the newbie question, but what is ECB-mode?

Electronic Code Book.  There is no chaining, so all like characters
are represented by the same code. For example, all  <space> characters
might be represented as a '*'. It's the security equivalent of a magic
decoder ring.

----
  Keith

Article: 29367
Subject: Re: Rijndael
From: Panu =?iso-8859-1?Q?H=E4m=E4l=E4inen?= <panuh@cs.tut.fi>
Date: Fri, 16 Feb 2001 16:30:27 +0200
Links: << >>  << T >>  << A >>

> <brendan.lynskey@pace.co.uk> wrote:
> 
> >Sorry for the newbie question, but what is ECB-mode?
> 

A block cipher mode. Each plaintext block is independently encrypted into
ciphertext. No feedback loop from cipher output to its input. 

See http://www.rsasecurity.com/rsalabs/faq/2-1-4-2.html.

-- Panu

Article: 29368
Subject: help
From: hsdary <hjhcsw2000@yahoo.com.cn>
Date: Fri, 16 Feb 2001 06:53:22 -0800
Links: << >>  << T >>  << A >>
Hi:
  Now, i implement my project with
Foundation 3.1 on pc,when it will finish,it said:
  WARNING:Anno:197 - NGDAnno found 48 physical component(s) for which 100 percent
   back-annotation is not possible. Simulation models for these components will
   be constructed from the NCD. Rerun NGDAnno with the -report option for
   additional details, including any net and instance names which are lost in
   this process.
Resolving logical and physical hierarchies...
WARNING:Anno:178 - 8 hierarchical blocks were flattened during back-annotation.
   Rerun NGDAnno with the -report option to see a list of these blocks, as well
   as additional information about nets and instances that may not have their
   original names.
Running NGD DRC...
WARNING:Ngd:333 - NOTE: This design contains the undriven net "GSR" which you
   could drive during simulation to get valid results.
WARNING:Ngd:333 - NOTE: This design contains the undriven net "GTS" which you
   could drive during simulation to get valid results.
   what's meaning?

Article: 29369
Subject: Re: help
From: Chris Dunlap <cdunlap@xilinx.com>
Date: Fri, 16 Feb 2001 09:50:39 -0700
Links: << >>  << T >>  << A >>
Check out the following link for questions one:
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=8602

For those last warnings, it means that chip you are using has dedicated logic for
global reset and global tristate but you are not using this in the device.  These
pins have been enabled in simulation presumably so you could use those to either
reset or tristate your logic in simulation but this would not be accurate because
that logic is not enabled in your device.

Best regards,

Chris Dunlap

hsdary wrote:

> Hi:
>   Now, i implement my project with
> Foundation 3.1 on pc,when it will finish,it said:
>   WARNING:Anno:197 - NGDAnno found 48 physical component(s) for which 100 percent
>    back-annotation is not possible. Simulation models for these components will
>    be constructed from the NCD. Rerun NGDAnno with the -report option for
>    additional details, including any net and instance names which are lost in
>    this process.
> Resolving logical and physical hierarchies...
> WARNING:Anno:178 - 8 hierarchical blocks were flattened during back-annotation.
>    Rerun NGDAnno with the -report option to see a list of these blocks, as well
>    as additional information about nets and instances that may not have their
>    original names.
> Running NGD DRC...
> WARNING:Ngd:333 - NOTE: This design contains the undriven net "GSR" which you
>    could drive during simulation to get valid results.
> WARNING:Ngd:333 - NOTE: This design contains the undriven net "GTS" which you
>    could drive during simulation to get valid results.
>    what's meaning?


Article: 29370
Subject: Re: Configuration of FPGA using SPROM
From: Chris Dunlap <cdunlap@xilinx.com>
Date: Fri, 16 Feb 2001 10:02:00 -0700
Links: << >>  << T >>  << A >>
There are so many variables that could be leading to your failed configuration this is not the best forum to troubleshoot such an issue.  I would recommend calling the support hotline where you can talk to someone who can gain all the necessary information and give you ideas quickly rather than going back and forth in a discussion forum.

INIT should go low initially but only at the very beginning.  If INIT goes low during actual configuration, then DONE can not go high.  Since you say DONE did go high did HDC go low and what is CLK doing, is it still running?  All of these scenarios are outlined in the configuration troubleshooter however which is very very helpful if you have not
already looked into this.  You may need a few extra clocks.  it is hard to tell from such little information.  Again though, check the troubleshooter.

Best regards,

Chris

Chris

radhika wrote:

> hi chris!
>  Thank you for the information.I am sorry to trouble you again - in our configuration we found that INIT signal is initially going low during configuration and when it is switching to high both the LDC and the DONE pins are going high indicating configuration of FPGA.But we find that the output is erroneous.We would appreciate if you could help us.
> sincerely
> radhika


Article: 29371
Subject: DSPIA Inc. becomes Xilinx XPERTS Partner
From: Muzaffer Kal <muzaffer@dspia.com>
Date: Fri, 16 Feb 2001 17:25:49 GMT
Links: << >>  << T >>  << A >>
hi,
Our web page at Xilinx has finally appeared. Please visit
http://www.xilinx.com/company/consultants/partdatabase/usdatabase/northwest/dspia.htm

Our home page is at http://www.dspia.com.

All comments on content are welcome.

Muzaffer

FPGA DSP Consulting
http://www.dspia.com

Article: 29372
Subject: Re: Design of a divide by 6.5 counter ?
From: Lukose Ninan <lukose@gte.net>
Date: Fri, 16 Feb 2001 18:04:27 GMT
Links: << >>  << T >>  << A >>
Hi Mark ,

I had  a similar problem some time ago (divide by 4.5) and I am attaching a
post  I placed on comp.lang . verilog below.

I think I was hasty in saying that it synthesized without any problems , the
routed circuit
showed  a small period variation between alternate samples, I think  the
routing
delay between clocking with posedge and negedge caused this . So if your
application is tolerant of this , try this code. Attached is the reference in
EDNmag for the basic idea, but not the code.

Still looking for better solutions ...


Previous post :--

I found something simpler on the net that you
might be interested in .

http://www.ednmag.com/ednmag/reg/1997/052297/11di_05.htm#Listing 1

This shift register based implementation takes only few lines of code and
synthesizes without any problems.


//duty factor 1:3.5
module edn4_5(inclk,Reset,outclk);
 input inclk;
input Reset;
output outclk;
reg [8:0] a;
reg b;

  always@ (posedge inclk or posedge Reset)
 begin
 if (Reset)  a = 9 'b 000000001;
 else a = {a[7:0], a[8]} ;
 end

  always@ (negedge inclk or posedge Reset)
 begin
  if (Reset)  b =0;
  else b=a[4];
 end

assign outclk = b|a[0] ;
 endmodule



mark wrote:

> Hi ,
>
>     Being new to vhdl I have only ever designed integer counters, so could
> someone tell me how you would design a synthesizable divide by 6.5 counter.
>
> Thanks
>
> Mark


Article: 29373
Subject: Vertex Place & Route Time
From: "Erik Wahlstrom" <erikw@lumnet.com>
Date: Fri, 16 Feb 2001 19:42:31 GMT
Links: << >>  << T >>  << A >>
We are looking for ways to decrease the place, route and synthesis time
required for the Vertex II 1000 and above.

Does anyone have any experience comparing,

Pentium II vs. Pentium III at the same frequency?
I remember reading something about a "shift by N number of bits" instruction
which was removed in P3.

What about Cache size. Is there a signifigent speedup going to the 2MB
cache.

What about interleaving main memory.

What about RAMBUS main memory? I know RAMBUS get it's speed up from
pipelining.

What about striped filesystems across 2 to 4 UltraSCSI disks?

No doubt all of the above will help but has anybody actually done the
comparative cost analysis?

Cheers Erik



Article: 29374
Subject: Re: Vertex Place & Route Time
From: "Simon Bacon" <simonb@tile.demon.co.cuthis.uk.>
Date: Fri, 16 Feb 2001 20:23:11 -0000
Links: << >>  << T >>  << A >>
Of course, nothing approaches the gain from floorplanning...

"Erik Wahlstrom" <erikw@lumnet.com> wrote in message
news:Hofj6.1623$JS2.206543@newsread2.prod.itd.earthlink.net...
> We are looking for ways to decrease the place, route and synthesis
time
> required for the Vertex II 1000 and above.
>
> Does anyone have any experience comparing,
>
> Pentium II vs. Pentium III at the same frequency?
> I remember reading something about a "shift by N number of bits"
instruction
> which was removed in P3.
>
> What about Cache size. Is there a signifigent speedup going to the 2MB
> cache.
>
> What about interleaving main memory.
>
> What about RAMBUS main memory? I know RAMBUS get it's speed up from
> pipelining.
>
> What about striped filesystems across 2 to 4 UltraSCSI disks?
>
> No doubt all of the above will help but has anybody actually done the
> comparative cost analysis?
>
> Cheers Erik
>
>





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