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Messages from 29125

Article: 29125
Subject: FAQ
From: Philip Freidin <philip@fliptronics.com>
Date: Tue, 06 Feb 2001 19:01:22 -0800
Links: << >>  << T >>  << A >>

I am creating a new web site:   www.fpga-faq.com  and
intend for it to be a central site for FPGA related questions.

Don't go there yet, there isn't any content.

At this point I am open to suggestions of how the site should
be set up.

I am planning for the site to include the total archive of this
news group, with multiple ways to access the articles.

I would also like the site to host tutorial and FAQ type articles,
and I would like people to volunteer to be contributors.

Volunteers for proof reading, HTML page formatting, and
other content creation and management would also be greatly
appreciated.

I have already paid for the site registration, and the hosting
account.

Volunteers/others can email me at philip@fpga-faq.com

Philip Freidin
Philip Freidin
Fliptronics

Article: 29126
Subject: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
From: "Theron Hicks (Terry)" <hicksthe@egr.msu.edu>
Date: Tue, 06 Feb 2001 22:20:39 -0500
Links: << >>  << T >>  << A >>
I understand your frustration but what about those of us who don't have
access to a place to post the graphic support for these types of questions
(i.e. a web site)?  I have a 28.8K baud connection and it only took a very
short time to down load his file so I don't think it was that large of a
file to complain about either from bandwidth or storage space.  A legalistic
interpretation of the "rules" would disallow a graphic posting but frankly I
wonder if the jpg might require less bandwidth than a overly long text
posting.  Almost certainly all the time and energy wasted on the response to
the issue requires more bandwidth, etc. than the jpg did.

On the other hand, in this case, I wonder if a graphic was really required
to describe what appears to be a simple function.

Just my two cents worth,
Theron Hicks

Andy Peters wrote:

> Marc wrote:
> >         I need to build a 'switching matrix'. (Please look at the
> > picture to understand the message ). I must be able to 'route' the
> > signal from port A to port X,Y or Z, and idem for B and C. If port X
> > is used, it quite understandable that i wont be able to 'route' an
> > other signal comming from port A.B or C there. The signal that i'll
> > use is PCM clocked at the speed of "from 64Khz to 3Mhz". Each
> > port has a TX and RX pin.
> >
> >         Once a 'virtual' route is created, ( example, from port B to
> > port Z ) i must be able to create a other 'route'  ( example, from
> > port A to port Y ) without creating a glitch or noise to the first one
> > already 'live'.For testing a 3x3 ports matrix is ok. but the next one
> > will be around 30x30 ports matrix.
> >
> >         My question is, which device can be the best for this
> > kind of application, and , an idea how to build the concept of
> > a matrix like that.
>
> Please don't post binaries of your homework assignments in this
> newsgroup.
>
> Have a happy day.
>
> -a


Article: 29127
Subject: Re: Switching matrix, FPGA or CPLD? -
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Wed, 07 Feb 2001 16:43:47 +1300
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> Marc,
> you should be ashamed of yourself for this response.
> Your question was not well formulated ( were you talking about many ports or
> wide ports ?), and the idea of doing this in a CPLD is so incredibly naive that
> one  automatically suspects an ineperienced student.
> Especially when you are hiding behind an anonymous e-mail address.
> So, behave yourself next time.
> 
> Peter Alfke
> ========================
> Marc wrote:
> 
> > IF you don't know how to awnser, don't wasted our bandwidth
> > with your stupidity. Im technician for 10 years in fiber optical
> > networks, not a student.

Boys..Boys - settle down..

CPLD is not a silly target, and it does sound a bit like homework :-)

 Treat the TX.RX as two cross point 'sheets', and some care is 
needed in correctly pairing the channels, but that's a SW issue.

 Certainly for a 3x3 crosspoint, a SPLD will do.

 Above that, it depends on the total cross point matrix, 
and the active cross point density. 

eg I estimate 30 x 30 Array, with 6 active crosspoints will fit into an
ATF1508.

If you want all crosspoints active, and two way, then the CPLD scales 
to the larger end of the spectrum 

-jg

Article: 29128
Subject: Re: Xilinx XC4010
From: V R <nospam@nononononodifjskdjfslspam.com>
Date: Wed, 7 Feb 2001 03:53:50 +0000 (UTC)
Links: << >>  << T >>  << A >>
Brian P <brian.doesn'twantspam@xilinx.com> wrote:
> This is a multi-part message in MIME format.
> --------------1063928F65A48100F8EADDE2
> Content-Type: text/plain; charset=us-ascii
> Content-Transfer-Encoding: 7bit




> If you do attempt to use these older devices, I either suggest getting your
> hands on the older software (safest) or use the newer sofftware but be sure
> not to use any of the features supported in 4000E that are not availible in

Can you tell me what was the last version/name of the Xilinx tool(s) that
supported the 4000 & 4000A?

If these are outdated, would they be available without license?

Thanks!
V R.


Article: 29129
Subject: Re: interior timing constraints - Xilinx F1.5
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Wed, 07 Feb 2001 09:01:03 +0200
Links: << >>  << T >>  << A >>
Rob Finch wrote:

> Thanks but..
>
> Perhaps I wasn't clear. I have already looked at the manuals. What I want to
> know is how to specify the 'net_name' that is used everywhere when the net
> is not at the root of the hierarchy.
>
> eg for the example is the net name "av_testmod_clk2" ? or "testmod_clk2"
> neither of these work. I've tried many different permutations. I can get the
> net name to work when the net is at the root of the hierarchy, but I haven't
> found any examples where the net is within another net.
> Do I have to somehow specify the net name in the source code ? How do I do
> this? I'm using Verilog.

Only synthesis tools can change the name of the signals, when you can't find
a signal name, which was declared in your HDL code, in your XNF or EDIF file.

It seems that your synthesizer has changed the name of the signal, such that
you don't know the new name.

In order to find the real name of the signal, you must look at the synthesizer
features.

For examples, Synplify's graphical viewer of its synthesis result is the only
practical way to find the name of the signals it has changed. In its old versions,
Synplify changed even the name of the derived clock inside. In order to find
that, I had to look at the Technology View. There was no such feature in
Synopsys FPGA Express at that time, and it was very difficult to find the name
of the signal in the XNF file.

In order to prevent signal name from being changed, I think Synplify's
synthesis directive

wire internal_signal /*synthesis syn_keep=1 */;

is available. I don't know the case in other synthesizers.

Utku



Article: 29130
Subject: Re: Re: Handel-C language.
From: ejeandeau@mpc-data.co.uk ("Eric Jeandeau")
Date: 7 Feb 2001 10:43:59 +0100
Links: << >>  << T >>  << A >>
Hi Jian,

Firstlly, thank you for your answer ( Now I know that I am not
the only Handel-C programmer !!!)

I have got the Handel-C Version 3.0 Beta from Celoxica actually.
This version contains *on line help* with
- Handel-C User manual
- Handel-C reference manual
- Pre-processor manual
So is it what you call "manual from Celoxica" ?

But what I am looking for is (for instance) :
- Theses/Rapport with program sample program Handel-C
- internet topics : www or ftp or newsgroup

If you can help me, it would be nice ;-)

PS : How long time did you work with Handel C ?
What is your target ?

Cheers
Eric JEANDEAU

ejeandeau@mpc-data.co.uk





-- 
Posted from finch-post-10.mail.demon.net [194.217.242.38] 
via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 29131
Subject: Spartan II/Virtex DLL with Exemplar - help
From: Gil Golov <golov@sony.de.REMOVE_THIS>
Date: Wed, 07 Feb 2001 11:19:24 +0100
Links: << >>  << T >>  << A >>

I try to use DLL using the standard connection path
Ibufg->DLL_input->DLL_clk0->Gbuf->DLL_fb+my_system_clock.
Leonardo Spectrom does not understand that there is a connection between
the input and the output of the DLL. Therefore under the
constrains/clock I get nothing and instead my input clock appears under
the input signal sections. This is wrong because the tool does not
realize that my clock signal is the input clock of the system.

Any ideas?

Many thanks

Gil Golov



Article: 29132
Subject: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
From: eml@riverside-machines.com.NOSPAM
Date: Wed, 07 Feb 2001 11:40:16 GMT
Links: << >>  << T >>  << A >>
On Tue, 06 Feb 2001 22:20:39 -0500, "Theron Hicks (Terry)"
<hicksthe@egr.msu.edu> wrote:

>I understand your frustration but what about those of us who don't have
>access to a place to post the graphic support for these types of questions
>(i.e. a web site)?  I have a 28.8K baud connection and it only took a very
>short time to down load his file so I don't think it was that large of a
>file to complain about either from bandwidth or storage space.  A legalistic
>interpretation of the "rules" would disallow a graphic posting but frankly I
>wonder if the jpg might require less bandwidth than a overly long text
>posting.  Almost certainly all the time and energy wasted on the response to
>the issue requires more bandwidth, etc. than the jpg did.

My server (or something, anyway) automatically removes any jpgs on
this newsgroup. In fact, it normally dumps the entire message. This is
probably one of the two biggest news servers in the UK.

Evan

Article: 29133
Subject: Re: interior timing constraints - Xilinx F1.5
From: eml@riverside-machines.com.NOSPAM
Date: Wed, 07 Feb 2001 11:41:29 GMT
Links: << >>  << T >>  << A >>
On Wed, 07 Feb 2001 00:31:14 GMT, "Rob Finch" <robfinch@sympatico.ca>
wrote:

>Thanks but..
>
>Perhaps I wasn't clear. I have already looked at the manuals. What I want to
>know is how to specify the 'net_name' that is used everywhere when the net
>is not at the root of the hierarchy.
>
>eg for the example is the net name "av_testmod_clk2" ? or "testmod_clk2"
>neither of these work. I've tried many different permutations. I can get the
>net name to work when the net is at the root of the hierarchy, but I haven't
>found any examples where the net is within another net.
>Do I have to somehow specify the net name in the source code ? How do I do
>this? I'm using Verilog.

You may be able to do this, but it depends on your synth and your
backend tools. I'd start by downloading the webpack software - you
won't get anywhere with the student edition.

In general, you can specify an attribute for a netname in your HDL,
but I've never tried this with a clock period. Do something like this
(it's synth-dependent) in your Verilog:

module test(CLK, ...);
input CLK;
...
// specify the period of CLK as 60ns with a metacomment:
// this example probably doesn't work
//synthesis attribute period of CLK is "60"

This probably wont work, but you may be able to get it to work by
experimenting. The idea is to get the synth to put the appropriate
attribute on the real netname in the EDIF output, and then to get
ngdbuild/map to understand the attribute. If in doubt, get a working
test case in schematics, with a period attribute, check the EDIF
output, and then try to get the synth to produce the same thing in
it's own EDIF output.

BTW, Verilog2000 now has attributes, but they're little or no better
than metacomments, and it'll be some time before they're supported (if
ever). 

The 'approved' way to do this is to spend the $$$ and get the modular
design software. This'll let you set cycle times on modules, although
I haven't tried it.

Evan

Article: 29134
Subject: 8B/10B Encoding
From: "S. Ramirez" <sramirez@deletethis.cfl.rr.com>
Date: Wed, 07 Feb 2001 12:14:26 GMT
Links: << >>  << T >>  << A >>
     Does anyone know where I can find some Internet information on 8B/10B
encoding?
     Thank you very much in advance.
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL  USA



Article: 29135
Subject: Re: 8B/10B Encoding
From: Michael Boehnel <boehnel@iti.tu-graz.ac.at>
Date: Wed, 07 Feb 2001 15:25:59 +0100
Links: << >>  << T >>  << A >>
Maybe you can get a rough overview at the following links:

http://www.cisco.com/warp/public/759/ipj_2-3/ipj_2-3_gethernet.html

http://www.iol.unh.edu/training/fc/fc_tutorial.html#8B10B

Have a look at datasheet of some Gigabit devices (e.g. transceiver chips):
http://www.amd.com/products/npd/techdocs/21560.pdf

Details of 8B/10B for Gigabit Ethernet can you find in IEEE 802.3.

Good luck,

Michael


"S. Ramirez" wrote:

>      Does anyone know where I can find some Internet information on 8B/10B
> encoding?
>      Thank you very much in advance.
> Simon Ramirez, Consultant
> Synchronous Design, Inc.
> Oviedo, FL  USA


Article: 29136
Subject: Re: 8B/10B Encoding
From: "Jason Daughenbaugh" <jad_NOSPAM@aedinc.net>
Date: Wed, 7 Feb 2001 07:23:09 -0800
Links: << >>  << T >>  << A >>
The Cypress Hotlink series has great documentation.  The Xilinx 8b/10b cores have ok documentation as well.

I have a question - IBM Patented it.  How does this limit its use?  
Xilinx has a Notice on their core saying that use of it may infringe on IBM's patent.  But it seems like everyone is using 8b/10b codes.

Thanks!
Jason Daughenbaugh
http://www.aedinc.net

Article: 29137
Subject: Re: 8B/10B Encoding
From: Michael Strothjohann <strothjohann@rheinahrcampus.de>
Date: Wed, 07 Feb 2001 15:49:49 +0000
Links: << >>  << T >>  << A >>
Hi,
    The 8B/10B encoding is IBM Pat Nr ....
    You may find some infos when looking
    for amd's TAXI-chip. look at cypress.com
    search for hotchip. look at xilinx.com
    look at ...
michael


"S. Ramirez" schrieb:

>      Does anyone know where I can find some Internet information on 8B/10B
> encoding?
>      Thank you very much in advance.
> Simon Ramirez, Consultant
> Synchronous Design, Inc.
> Oviedo, FL  USA


Article: 29138
Subject: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
From: Jean-Paul Smeets <jpsmeets@xs4all.nl>
Date: Wed, 07 Feb 2001 17:24:47 +0100
Links: << >>  << T >>  << A >>
On Tue, 06 Feb 2001 02:57:49 GMT, S_mythicbird@hotmail.com (Marc)
wrote:

>Hello,
>
>
>	I need to build a 'switching matrix'. (Please look at the
>picture to understand the message ). I must be able to 'route' the
>signal from port A to port X,Y or Z, and idem for B and C. If port X
>is used, it quite understandable that i wont be able to 'route' an
>other signal comming from port A.B or C there. The signal that i'll
>use is PCM clocked at the speed of "from 64Khz to 3Mhz". Each 
>port has a TX and RX pin.
>
>	Once a 'virtual' route is created, ( example, from port B to
>port Z ) i must be able to create a other 'route'  ( example, from
>port A to port Y ) without creating a glitch or noise to the first one
>already 'live'.For testing a 3x3 ports matrix is ok. but the next one
>will be around 30x30 ports matrix.
>
>	My question is, which device can be the best for this
>kind of application, and , an idea how to build the concept of 
>a matrix like that.
>

Hi,

Does it have to be an FPGA or CPLD?

Both Lattice Semiconductor
(http://www.latticesemi.com/products/devices/ispgdx.html ) and

I-Cube ( http://www.icube.com  )

make these as standard devices.

Jean-Paul Smeets



J.P. Smeets
business:
Ellips
Woenselsestr 352A
5623 EG Eindhoven
tel: +31-40-2456540
fax: +31-40-2467183
email: jeanpaul@ellips.nl
home:
Loondermolen 23
5612 MH Eindhoven
tel: +31-40-2465105
email: jpsmeets@xs4all.nl

Article: 29139
Subject: Re: Xilinx XC4010
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Wed, 07 Feb 2001 10:29:58 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------8858EE6892E42B8F5596219B
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit


V R,

Thanks for the Spam removal below.  I appreciate it.

The last version to support 4000/4000A was XACT 6.0.1/5.2.1 (the 6 version refers
to the GUI, the 5 version refers to the command-line tools).  It was last
distributed maybe 3 or 4 years ago.  Unfortuantely, even though it is obsoleted
software, it does still require licensing which means if you are on a PC, you
need a dongle to use the software.  I might be able to help you out with
obtaining the old software but lets do this off-line.  Send me an e-mail without
including the newsgroup and I will see what I can do for you.

I still suggest getting a hold of a Spartan device because you will have a much
easier go at targeting that part and probably a better FPGA experience but I
understand not wanting those parts you have in-hand go to waste.  The software
has come a long way in those few years as I am sure many on this newgroup will
agree.


--  Brian



V R wrote:

> Brian P <brian.doesn'twantspam@xilinx.com> wrote:
> > This is a multi-part message in MIME format.
> > --------------1063928F65A48100F8EADDE2
> > Content-Type: text/plain; charset=us-ascii
> > Content-Transfer-Encoding: 7bit
>
> > If you do attempt to use these older devices, I either suggest getting your
> > hands on the older software (safest) or use the newer sofftware but be sure
> > not to use any of the features supported in 4000E that are not availible in
>
> Can you tell me what was the last version/name of the Xilinx tool(s) that
> supported the 4000 & 4000A?
>
> If these are outdated, would they be available without license?
>
> Thanks!
> V R.

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begin:vcard 
n:Philofsky;Brian
tel;work:1-800-255-7778
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url:http://www.xilinx.com
org:Xilinx, Inc.;Software Marketing
adr:;;2300 55th Street;Boulder;CO;80301;USA
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title:Sr. Technical Marketing Engineer
fn:Brian Philofsky
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--------------8858EE6892E42B8F5596219B--


Article: 29140
Subject: Mentor Advice
From: p25486@my-deja.com
Date: Wed, 07 Feb 2001 17:35:44 GMT
Links: << >>  << T >>  << A >>
Hi, this is slightly off topic, sorry.

I work for a big corporation that shall remain nameless (starts with
an "M" and ends with an "ola").  Anyway, some corporate type purchased
company wide licenses for the Mentor Graphics suite of tools (seems
like a suspiciously smart thing for a corporate type to do).

I'm an FPGA designer, and have been doing mostly VHDL designs aimed at
FPGAs/CPLDs.  Having lived with Xilinx's foundation Express for the
last several years, this upgrade seems to be great.  Saved us $60k or
so from buying Synplicity.

The Mentor tools seem really good.  However, their front-end tool is
something called Renoir.  At first glance it looks like a really cool
tool, and I'm sure that there are people out there who love it.  I am
not one of them.

Renoir, is a graphical environment.  So the source files in which you
work are not all text, but contain some Mentor proprietary crap-o-
lium.  I thought the whole point of VHDL and Verilog was that you could
use any dumb text editor to view or edit a design.  This Renoir thing
seems to be taking that away.

The Mentor people I've talked to say that is not so.  True, that a VHDL
only version of the code is saved, but you can't directly edit it from
within Renoir.

So here's the question.  What's the best way to approach using this
tool (assuming that I have to stay Mentor because it's free to me)?

Approaches:

1.  Use some other tool, emacs, or the foundation stuff for the HDL
entry, then import the design to Renoir.

2.  Use some other tool emacs, or the foundation stuff for the HDL, and
go directly to ModelSim and then on to Leonardo Spectrum (I haven't
attempted this, any pitfalls?).

3.  Use some nifty option in Renoir that I don't know about.

4.  Use your incredibly cool approach that hasn't occurred to me.

Thanks,

John


Sent via Deja.com
http://www.deja.com/

Article: 29141
Subject: JTAG debugging?
From: eml@riverside-machines.com.NOSPAM
Date: Wed, 07 Feb 2001 17:59:20 GMT
Links: << >>  << T >>  << A >>
Anyone know how to drive JTAG manually for debugging? I've got a 9572
with an 8-bit instruction register, and an ADI device with a 3-bit
register, in series. Ideally, I'd like to put them both in bypass, and
just clock bits through to make sure that they get from TDI to TDO (or
something else very simple if it would be better). I've got Xilinx's
programmer, so I can set TDI and TMS, and then generate a TCK.

TIA -

Evan

Article: 29142
Subject: Re: 8B/10B Encoding
From: Philip Freidin <philip@fliptronics.com>
Date: Wed, 07 Feb 2001 10:36:37 -0800
Links: << >>  << T >>  << A >>
On Wed, 07 Feb 2001 12:14:26 GMT, "S. Ramirez" <sramirez@deletethis.cfl.rr.com>
wrote:

>     Does anyone know where I can find some Internet information on 8B/10B
>encoding?
>     Thank you very much in advance.
>Simon Ramirez, Consultant
>Synchronous Design, Inc.
>Oviedo, FL  USA
>

Extreme details are available in

   http://www.delphion.com/details?&pn=US04486739



Philip Freidin
Fliptronics

Article: 29143
Subject: Re: Mentor Advice
From: chris@cgschneider.com (Chris G. Schneider)
Date: 07 Feb 2001 22:34:54 +0100
Links: << >>  << T >>  << A >>
p25486@my-deja.com writes:

> Renoir, is a graphical environment.  So the source files in which you
> work are not all text, but contain some Mentor proprietary crap-o-
> lium.  I thought the whole point of VHDL and Verilog was that you could
> use any dumb text editor to view or edit a design.  This Renoir thing
> seems to be taking that away.

You can still use your fave editor by calling it from within Renoir. Renoir 
is just a kind of frontend that provides a statemachine editor, version 
control interface and some differnt views of your design and some stuff I do
not rember. However if you don't like it, you can still use the other tools 
from Mentor like Modelsim and Leonardo. There is no need to use Renoir. Just 
use a text editor if you prefer this.

> The Mentor people I've talked to say that is not so.  True, that a VHDL
> only version of the code is saved, but you can't directly edit it from
> within Renoir.

Renoir does something really weird: It reads your design, no matter if its
a "Renoir statemachine" or a VHDL source code, and then it is transformed 
into some kind of (very well) readable VHDL source code. But remember that
that the output is a transformed _copy_ of your original design.

> So here's the question.  What's the best way to approach using this
> tool (assuming that I have to stay Mentor because it's free to me)?

You may be interested in a statemachine editor that writes out good 
readable VHDL code or in a version control interface. If you think
that it is best to describe the statemachine in VHDL directly and
you allready have a good version control than just forget about Renoir.

> Approaches:
> 
> 1.  Use some other tool, emacs, or the foundation stuff for the HDL
> entry, then import the design to Renoir.

I don't see the need for import, if you don't want to use it.

> 2.  Use some other tool emacs, or the foundation stuff for the HDL, and
> go directly to ModelSim and then on to Leonardo Spectrum (I haven't
> attempted this, any pitfalls?).

I just use the commandline to create a library for ModelSim and to compile
my sources. After that you can write out a Makefile to do this task. No
Renoir involved. I think it is not a good idea to create projects form the 
Modelsim GUI, because Modelsim copies your source files into the project 
directory. You have to be very careful what files you edit then. 

I did not use Leonardo jet but I think you can use it standalone as well. 
 
> 3.  Use some nifty option in Renoir that I don't know about.
> 
> 4.  Use your incredibly cool approach that hasn't occurred to me.

To be honest, I just tried out Renoir, because our company bought it. I still
prefer to use my own scripts, makefiles and my fave editor.

> Thanks,
> 
> John
> 
> 
> Sent via Deja.com
> http://www.deja.com/

-- 
Chris


Article: 29144
Subject: Xilinx vs Altera
From: "Raymond Chow" <rchow@endpoints.com>
Date: Wed, 07 Feb 2001 22:59:18 GMT
Links: << >>  << T >>  << A >>
Hi,

Has anyone done a comparison between Xilinx and Altera, especially
on how well each do on route utilization and meeting timing requirements.

I'd just tried routing a design that routed fine using XCV600E with 56% LUT
utilization
and when I tried using XCV400E the router will stop with the following
error:

Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.

Using target part "v400ebg432-6".

Reading NGD file "u200.ngd"...

Processing FMAPs...

Removing unused or disabled logic...

Running cover...

Writing file u200.ngm...

Running directed packing...

Running delay-based packing...

Running related packing...

Running unrelated pack...

EXEWRAP detected a return code of '-1073741819' from program 'map'

Done: failed with exit code: 0005.

-any help will be greatly appreciated

-Raymond




Article: 29145
Subject: Verilog model of I2C/SMB
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 07 Feb 2001 23:05:12 +0000
Links: << >>  << T >>  << A >>
Anyone know of a  model of a I2C or SMB [System management bus] slave-
doesn't have to be synthesisable.


Article: 29146
Subject: Re: Xilinx vs Altera
From: "S. Ramirez" <sramirez@deletethis.cfl.rr.com>
Date: Thu, 08 Feb 2001 00:35:17 GMT
Links: << >>  << T >>  << A >>
"Raymond Chow" <rchow@endpoints.com> wrote in message
news:arkg6.58416$9v2.1057309@quark.idirect.com...
> Hi,
>
> Has anyone done a comparison between Xilinx and Altera, especially
> on how well each do on route utilization and meeting timing requirements.
>
> I'd just tried routing a design that routed fine using XCV600E with 56%
LUT
> utilization
> and when I tried using XCV400E the router will stop with the following
> error:
>
> Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
>
> Using target part "v400ebg432-6".
>
> Reading NGD file "u200.ngd"...
>
> Processing FMAPs...
>
> Removing unused or disabled logic...
>
> Running cover...
>
> Writing file u200.ngm...
>
> Running directed packing...
>
> Running delay-based packing...
>
> Running related packing...
>
> Running unrelated pack...
>
> EXEWRAP detected a return code of '-1073741819' from program 'map'
>
> Done: failed with exit code: 0005.
>
> -any help will be greatly appreciated
>
> -Raymond

Raymond,
     In general and especially with certain types of functions such as
anything using carry chains, Brand X will win hands down.
     But the great thing about Brand X is that soon enough, a Brand X person
will pick off your error code and translate it into an answer for you.
That's because this newsgroup is monitored by Brand X.  It is even
advertised on their web site!
     So kick back and wait for the answer.  Some Brand X employee will go
research the answer by going into their code documentation and finding out
what the error means.
     Would Brand A do that on this newsgroup?  Yeah, I know.  They dont have
access to the Xilinx code!
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL  USA


Article: 29147
Subject: VHDL-Mode
From: kfalser@durst.it (Klaus Falser)
Date: Thu, 08 Feb 2001 08:04:40 GMT
Links: << >>  << T >>  << A >>
Does anybody know where to find VHDL-Mode for Emacs?

The official site should be http://www.emacs.org/hdl/vhdl-mode.html, 
but www.emacs.org seams dead.

Thanks

Falser Klaus
R&D Electronics Department
Company	: Durst Phototechnik AG
	Vittorio Veneto Str. 59
	I-39042 Brixen
Voice	: +0472/810235
	: +0472/810111
FAX	: +0472/830980
Email	: kfalser@IHATESPAMdurst.it 

Article: 29148
Subject: AES (Rijndael) in FPGAs
From: Panu =?iso-8859-1?Q?H=E4m=E4l=E4inen?= <panuh@cs.tut.fi>
Date: Thu, 08 Feb 2001 10:12:15 +0200
Links: << >>  << T >>  << A >>
Hi!

I'm trying to implement AES encryption algorithm in Xilinx Virtex FPGAs. There
are some published articles about AES reconfigurable hardware implementations
and I have read them. However, they mainly deal with the high level design
methods (loop unrolling etc.) and the implementation results. If someone has
made an AES FPGA implementation, I could use some advice and suggestions about
how to do it, meaning lower level desing methods (e.g. how to implement the
S-boxes and the MixColumn phase).

Moreover, I have tried the synthesize the VHDL code that is available on the AES
web site (http://csrc.nist.gov/encryption/aes/round2/r2anlsys.htm#NSA), but at
least the Xilinx Foundation 2.1i (PC version) gets stuck during the elaboration
phase. I tried to find an answer to the problem from the Xilinx web page. They
said that the reason for getting stuck and finally running out of memory could
be due to a large number of complex or nested for and generate loops. Well, I
unrolled most of them but still the tool runs out of memory. Currently my PC's
main memory is 384 Mbytes and the amount of virtual memory 1 Gbytes. Shouldn't
this be enough?

Previously, in some other designs, I noticed that if I use large vectors (e.g.
256 x 8-bytes, constant or non-constant vector) this may have the same affect
(the tool hangs). I solved the problem by replacing the vectors with ROM/RAM.
Anyway, the AES code uses this kind of large vectors and the designers claim
that it should be possible to target the code to FPGAs (the VHDL was originally
written for ASIC synthesis). Has someone else had similar problems? Do you know,
if it's possible to use this kind of large vectors on (Xilinx) FPGAs or is it
always necessary to replace them with ROM/RAM?

Regards, Panu

Ps. There was some discussion about Rijndael implementations in this group some
time ago. However, the discussion ended before anyone gave any hints.

Article: 29149
Subject: Re: JTAG debugging?
From: "Jaan Sirp" <jaan.sirp@mail.ee>
Date: Thu, 8 Feb 2001 00:16:33 -0800
Links: << >>  << T >>  << A >>
Hi Evan.

>Anyone know how to drive JTAG manually for debugging?

If you are SW guy, write a small program, which uses parallel port for driving JTAG. If you like HW, use glitch-free switches.

Jaan



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