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Messages from 32825

Article: 32825
Subject: Re: Max+2 and multi-cycle timing analysis WAS: Altera ACEX
From: "Marco" <curgan@t-online.de>
Date: Tue, 10 Jul 2001 09:29:15 +0200
Links: << >>  << T >>  << A >>
Thanks for all,

is there any possiblility to compile and simultate a program for the ACEX
device ??
My senior engineer wants to buy it. Is it necessary ????

thx

Marco


Mike Treseler <mike.treseler@flukenetworks.com> schrieb in im Newsbeitrag:
3B49FFC6.83FE115E@flukenetworks.com...
> bob elkind wrote:
>
> > By the way, Quartus II has 3 different files to provide the aggregate
> > functionality of the MAX+II .ACF file, and all three are *binary*,
> > not ASCII text.
>
> This is not true.
> The quartus settings files are .CSF, .PSF and .ESF.
> They are all ASCII text.
> The only binary files are for the internal database.
>
>       -Mike Treseler



Article: 32826
Subject: Re: Modlesim5.5
From: "Johan Petersson" <johan.petersson@wdi.se>
Date: Tue, 10 Jul 2001 07:33:47 GMT
Links: << >>  << T >>  << A >>
Search the archives for comp.lang.vhdl - I have a rememberance of something
like
this being related to which languare standard you are running...

How do you read the line?

Good Luck,
/Johan - www.wdi.se

"Nicolas Matringe" <nicolas.matringe@IPricot.com> skrev i meddelandet
news:3AD7110B.E0E82CA3@IPricot.com...
> Filip Gielen wrote:
> >
> > I just tried it and it looks more stable than the 5.5
> > So I thinks they solved the problem.
>
> I have downloaded it and encountered a problem with textio (I've
> reported it but have no news yet): ModelSim crashes just after reading
> the last character of a line.
>
> Anyone else got the problem?
>
> --
> Nicolas MATRINGE           IPricot European Headquarters
> Conception electronique    10-12 Avenue de Verdun
> Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
> Fax +33 1 46 52 53 01      http://www.IPricot.com/



Article: 32827
Subject: Re: How to specify Spartan2 GSR/GTS for Synthesis
From: "Johan Petersson" <johan.petersson@wdi.se>
Date: Tue, 10 Jul 2001 07:37:07 GMT
Links: << >>  << T >>  << A >>
Depending on what you want to do you could also design a "local" reset
signal
for you FF

Something on the lines of

local_reset = true when my_condition else false;

and use local reset for you flip_flop/flip_flops -

Why don't you want to use a global reset?

/Johan - www.wdi.se


"Philip Freidin" <philip@fliptronics.com> skrev i meddelandet
news:1pqadtg20sc3sma87gueem56q84uvqu6bp@4ax.com...
> Kolja Sulimma wrote:
> >
> > I have an additional questions to this:
> >
> > If I have no explicit reset signal in my design, how do I specify the
reset value of a
> > DFF?
> >
> > Thanks,
> >             Kolja
>
> In Verilog, with Synplicity, you do it like this:
>
> module ROCBUF (I, O); //synthesis syn_black_box
>           input I;
>           output O;
> endmodule
>
> module gsr_test(q_async_reset_ff, q_async_set_ff, i, clk,
strippable_reset);
>
> input i,clk,strippable_reset;
> output q_async_reset_ff, q_async_set_ff;
> reg q_async_reset_ff, q_async_set_ff;
>
> wire internal_reset;
>
> // expect the following to be stripped by MAP
> ROCBUF u1 (.I(strippable_reset), .O(internal_reset));
>
> always @ (posedge clk or posedge internal_reset) begin
> if(internal_reset) begin
> q_async_reset_ff  <= 0;
> q_async_set_ff    <= 1;
> end
> else begin
> q_async_reset_ff  <= i;
> q_async_set_ff    <= i;
> end
> end
>
> endmodule
>
>
> Philip
>
>
> Philip Freidin
> Fliptronics



Article: 32828
Subject: Re: Handel-C
From: "Johan Petersson" <johan.petersson@wdi.se>
Date: Tue, 10 Jul 2001 07:42:12 GMT
Links: << >>  << T >>  << A >>

"Brendan Lynskey" <brendan.lynskey@pace.co.uk> skrev i meddelandet
news:9b40sg$gr6$1@nh.pace.co.uk...
> So considering all that's been said, what a VHDLer to do?
>
> Is anyone else out there slightly worried about this whole thing? Maybe we
> should all accept the inevitable and take a course in programming?
>
>

NO! You'll be able to use your vhdl/gate arrays skills till death if you
just keep an awareness
of what happens with the gate arrays themselves -

But it's no bad idea to take a programming course so that you can do HIGH
LEVEL models
of your HW. If you do something like microprocessor architecture, VHDL is a
little to slow to
write a high level model - or rather the VHDL high level model would take
weeks in the simmulator -
thats when a HWdesigner might want some programming skills :)

My own opinions, of course -

/Johan - www.wdi.se



Article: 32829
Subject: Re: What chip!?
From: bob elkind <eteam@aracnet.com>
Date: Tue, 10 Jul 2001 00:43:36 -0700
Links: << >>  << T >>  << A >>
My noble apologies and comments inserted in context -- Bob

Rick Filipkiewicz wrote:

> bob elkind wrote:
>
> > Rick Filipkiewicz wrote:
> >
> >
> > > I think one of the bigger reasons must be the one mentioned by Peter A. some
> > > while back. Altera employees are not allowed to post on this NG whereas
> > > Xilinx ones are automatically issued with flame-proof underwear and directed
> > > to the battlefield.
> >
> > Poppycock.  Altera employees have posted on this newsgroup in the past, although
> > not anywhere near the extent of Xilinx representative postings.  Check recent
> > history of the group for postings by Brian Sullivan.
>
> >
> > Think of what you're saying:  Actel and Altera each has employees paid
> > specifically to communicate with customers, and yet both companies prohibit
> > communication to 1000s of customers at a time via a usenet newsgroup?
> > That probably is not the case.
> >
>
> This wasn't my comment - it came from Peter A.

Apologies -- Peter, you should be ashamed of yourself for saying such a thing!

> > The reasons for Altera and Actel *not* having their own "Peter Alfke
> > equivalents" are (my guesses):
> >
> > 1.  There is and will only be *one* Peter Alfke (had to throw that one in!).
>
> Not forgetting Austin Lesea doing good work on the DLL/PLL debate [and Shannon],
> Vikram Seth, Brian ??, Mark Ng.

Granted.  The distinction I try to make in point 2 below is that Austin, Shannon, et al
seem to be representing to this newsgroup their area of specific or general responsibility
within Xilinx, whereas Peter is Xilinx's ombudsman (I love that word!).

> > 2.  The organisational structures of Altera and Actel maintain more or less
> > distinct responsibilities between groups (e.g. marketing, sales, tech support,
> > customer service, field apps/sales, etc.).  Altera or Actel) would need 3 or
> > more people (from different groups with different VPs in charge) to
> > represent the various groups in the company, a logistical (and managerial)
> > problem that makes the implementation too complicated for most companies.
> >
>
> I don't see why organisational structure has, or should have, anything to do with
> posting on a NG.

Easy...  I want to represent myself to this newsgroup, and take a dim view of
someone else doing so on my behalf without my say.  Similarly, the VP of Mktg
at company B or Y (not A or X) probably takes a dim view of someone in the
tech support group presenting information to customers that is distinctly marketing
in nature.  The timing, form, style, and forum all belong to the Mktg dept to
craft and plan in its own way.  That planning and crafting is what Mktg gets paid to
do better than anyone in tech support.  And so on...  Businesses care very much
what gets "released" to customers, and how it gets "released".

> What you seem to be saying is IMHO far too formal an approach for a NG. We're all
> grown-ups here & will allow for the fact that even an FPGA Vendor employee may have
> only part of the picture.

Let me spin what you just said...
  *MANY* of us are grownups, and *MOST* of us can handle a "raw" info feed from
vendors without sharing it with any of our colleagues who may "mishandle" the information.
After all, the institution of usenet newsgroups is one of "no-spin" raw data exchange
without the polish that makes news and info from large businesses so sterile and impersonal.

The old days of newsgroups are (mostly) gone.  What worked as a comunications
back-channel between nerds (not businesses!) can be converted to an official news
spigot for large businesses, but not without the care and "management" needed to avoid
inconsistent re-transmission, downright wrong/mis information, inadvertent pre-release
information (can you spell SEC investigation?), and corporate liability/slander risks.

> Most times I'd rather have a description of the elephant's leg right now than wait
> for a sanctioned description of the whole animal.

Understood.  Of course, given a decent right leg description, I bet our collective minds
could come up with a pretty good picture of what we think the rest of the animal
should look like, and the fact that we all agree should be compelling evidence that
we must be pretty close to target.

I'm not sure I've maintained the metaphors properly, but I hope we've done a good
enough job so that we  can undertand each other's points of view.  You make a good
case for the way things out to be (and sometimes are), and I've tried to draw an alternate
picture of the way things (sometimes) might actually be, in practice.

I'm willing to call it a tie, and leave it at that.

Regards,

Bob Elkind, the e-team -- fpga/design consulting




Article: 32830
Subject: Problems with JTAG on XC95144 was:Best JTAG H/W,...
From: arast@qwest.net (Alex Rast)
Date: Tue, 10 Jul 2001 07:45:45 GMT
Links: << >>  << T >>  << A >>
In article <Vc617.4238$xY4.282582@news.uswest.net>, arast@inficom.com (Alex Rast) wrote:
>We are in the process of trying to get a board up and running that has a CPLD 
>on board (a xilinx XC95144) I've run the programming step several times 
>through the Xilinx software and MultiLinx cable with no success. It gives the 
>same old message (familiar to many) - 
>"...boundary-scan chain test failed at bit position '7' on instance 
>'DesignFile(Device1)'..."
>
>In the past I had similar problems with the same board and eventually got it 
>to work, but I can't remember everything that's involved and I suspect the 
>notes I have left out a key step.
>

OK, I now know a little bit what's going on.

We are using the XC95144XL in a circuit board where we have the JTAG lines to 
the chip switched. The lines pass through a set of switches (Pericom PI5A100) 
that are supposed to turn the JTAG lines on and off.

Trouble is, it doesn't seem to want to work. Any time we try to pass JTAG 
configuration signals through the switches, the software always errors out. 
You can configure the device without incident by bypassing the switches and 
connecting the JTAG signal lines from the configuration cable directly to the  
XC95144.

But I've done multiple tests with meters and scopes that verify that the 
PI5A100's really are simply performing the analog switch function they're 
supposed to - acting as a low resistance when on, and a very high resistance 
when off. Everything - the switch voltages, the CPLD I/O, and the CPLD core, 
is running at 3.3V. So why would the switches be interfering with JTAG?

Thanks for any help. 

Alex Rast
arast@qwest.net
arast@inficom.com

Article: 32831
Subject: Pins state on Spartan XL before config.
From: "Lionel DORIS" <lionel.doris@lab-leas.fr>
Date: Tue, 10 Jul 2001 10:13:08 +0200
Links: << >>  << T >>  << A >>
Hello.

I use Spartan XL in slave mode for debug and y have some problems when my
FPGA is loaded or not loaded :
( FPGA is connected on 16 bits microcontroller data bus and not used for
main central unit ) When FPGA is configured, it's impossible for me to load
and execute my firmware in external RAM ; when FPGA is not configured, my
firmware is loaded and executed correctly !!!

I would like to know which is state of all I/Os before the configuration is
loaded in FPGA.
Is it a bus configuration / capacitance problem ??

--
Lionel
LEAS - FRANCE



Article: 32832
Subject: Re: SpartanII: non clock pad drives clock net ?
From: "Andrew Barnes" <andrew.barnes@linn.co.uk>
Date: Tue, 10 Jul 2001 01:57:12 -0700
Links: << >>  << T >>  << A >>
I am currently using FPGA Express 3.5 from Synopsys, but am fast considering changing to something a wee bit more powerfull (Synplify, possibly).

Article: 32833
Subject: assigning signals with Altera Max+PlusII vhdl
From: "Michael Johnen" <michajo@gmx.de>
Date: Tue, 10 Jul 2001 11:26:21 +0200
Links: << >>  << T >>  << A >>
Hi all,

i try to learn vhdl and now i have problems
i never had before:

the following code..........

entity TEST13 is
    port (
   I  : in bit;
   AOUT : out bit_vector (7 downto 0));

end TEST13;

architecture TEST of TEST13 is
    signal SA  : bit_vector (7 downto 0) := "11110000";
    signal SB  : bit_vector (7 downto 0) := "00001111";

begin
process (I)
    begin
        case I is
            when '1' =>
                AOUT <= SA;
            when '0' =>
                AOUT <= SB;
       end case;
end process;

end TEST;

..........results in following (16) errors:

Error: Node ':109.IN1' missing source
                .....115.IN1...
                .....157..

What is wrong ???

Thanks,
Michael









Article: 32834
Subject: Re: Problem with resolution functions
From: abhijit@computer.org (Abhijit K. Deb)
Date: 10 Jul 2001 02:42:43 -0700
Links: << >>  << T >>  << A >>
s.blankenberg@hs-zigr.de (Sven Blankenberg) wrote in message 
> > Can you post the reference manual example?
> 
> of course, i' can.
>

: Hello Sven
  I donot see any problem in the code from the reference manual:

> -- copy from Manual
>   function RES_FUNC(DATA: in BIT_VECTOR) return BIT is
>   begin
>    for I in DATA'range loop
>      if DATA(I) = '0' then
>        return '0';
>      end if;
>    end loop;
>    return '1';
>   end;
> end;

: And I used this resolution function in the following
  entity as you have given:

> use work.RES_PACK.all;
> entity WAND_VHDL is
>   port(X, Y: in BIT; Z: out RESOLVED_BIT);
> end WAND_VHDL;
> architecture WAND_VHDL of WAND_VHDL is
> begin
>  Z <= X;
>  Z <= Y;
> end WAND_VHDL;

: My tool (Modelsim 5.2a) did not issue any error message
  and I simulated it without trouble.

  Maybe your problem stems from your testbench.
  Regards/Abhijit

Article: 32835
Subject: Re: Online threshold limit counter
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Tue, 10 Jul 2001 12:25:44 +0200
Links: << >>  << T >>  << A >>
Yes, but are you able to change your preloaded value during run-time? It
appears that what you are saying is that you set the preload value, and
thats what its stuck at. I need to be able to change the preloaded value
during runtime.

Adrian


John_H <johnhandwork@mail.com> wrote in message
news:3B49CD8A.ED23F65F@mail.com...
> You mean like counting from 0 to 78 and resetting the counter to zero
after you
> reach 78?
>
> Rather than resetting the counter to 0, I design my counters to reset
(preload)
> to -78 and count up to 0.  An added benefit:  the LSB of the counter (the
sign
> bit) can be used to directly drive the counter reset.
>
> Very programmable.
> - John
>
> Noddy wrote:
>
> > Hi all,
> >
> > Can anyone think of a way (without using a whole lot of XOR gates) to
create
> > a counter which has a threshold limit which can be updated via a port.
Right
> > now, I am just using a standard counter, then using an input bus and the
> > output bus of the counter, XOR them all together and use result to reset
the
> > counter. Is there a more efficient way?
> >
> > Adrian
>



Article: 32836
Subject: Re: Two's complement to binary translation problem
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Tue, 10 Jul 2001 12:44:55 +0200
Links: << >>  << T >>  << A >>
Well, all you really gotta do is, since MatLAB will only produce
coefficients normalised to 1, is to firstly take the modulus of the number
(ie. take away sign), then convert the number into binary and then take
two's complement of the number. You don't really have to worry about fixed
point arithmatic, since MatLABs filter coefficients will always be less than
1.

So, should get: 0.12456985477 = 0001 1111 1110 0011 (to 16 bits)
then, twos comp = 1110 0000 0001 1101

Think the calculations are right!

Adrian




Antonio <dottavio@ised.it> wrote in message
news:fb35ea96.0107092234.f76974f@posting.google.com...
> Good Morning,
> my problem is that Matlab produce for me the coefficient
> -0.12456985477 that I've to translate in two's complement with one bit
> for the sign , one bit before the point and 10 bit later, may you tell
> me which string of binary number I've to put inside my FIR for this
> coefficient ??
>
> Thank you really much...
>
>
>                           Antonio D'Ottavio



Article: 32837
(removed)


Article: 32838
Subject: Re: Online threshold limit counter
From: Keith R. Williams <krw@attglobal.net>
Date: Tue, 10 Jul 2001 08:11:35 -0400
Links: << >>  << T >>  << A >>
In article <994760615.735193@turtle.ru.ac.za>, g9731642@campus.ru.ac.za 
says...
> Yes, but are you able to change your preloaded value during run-time? It
> appears that what you are saying is that you set the preload value, and
> thats what its stuck at. I need to be able to change the preloaded value
> during runtime.

It depends on how you deal with the loading of the (negative) number.  
If you load it into a register and use the MSB to re-load the counter 
the new value won't be available until the next overflow/reset.  If you 
load the new value into the counter when the value changes or zero is 
reached, it will take effect immediately. 

----
  Keith

Article: 32839
Subject: Re: 8031 microcontroller on FPGA development board :-)
From: sknapp@triscend.com (Steven K. Knapp)
Date: 10 Jul 2001 05:37:42 -0700
Links: << >>  << T >>  << A >>
Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3B44F221.3CAF@designtools.co.nz>...
> Dave Vanden Bout wrote:
> > 
> > Niki Steenkamp wrote:
> > 
> > >
> > > The only significant difference, besides the on board code memory, is
> > > that the 8031 has 128 bytes of RAM while the 8051 has 256.  Also, AFAIK,
> > > the 8051 also has one additional timer (timer 2).
> > 
> > No, I believe the 8032/8052 micros are the ones with 256 bytes of internal
> > RAM and three timers.  The 8031/8051 micros only have 128 bytes and two
> > timers.
> 
> This is correct.
> The 8031/51 as single chip is starting to 'drop off the bottom', as the 
> more usefull 8052(89C52) is close in price.
> However, ROMless 8031/32 are still very cheap, well under $1, so soft
> cores have a way to go yet :-)
> 
> If you have a FPGA Board, with a '8031' socket, then ANY package
> compatible
> family member can be used.
> There are quite a few 'more current' members worthy of going alongside a
> FPGA,
> and with greatly increased speeds, more compatible with FPGA systems. 
> 
> o Dallas DS89C420 = 50 MIPS, 8052 core, 16K FLASH, 1K XRAM, 2 UART 5V
> o Winbond W77LE58 = 6-10 MIPS, 8052 core, 32K FLASH, 1K XRAM, 3-5V
> o Temic T89C51RD2 = 5 MIPS, 8052 Core, 64K Flash, 2KEE, 1K RAM, 3-5V
> 
> Not a 'std' 40/44 package, but interesting is
> o Dallas 80C400 = 10 Mips, Ethernet, CAN, TCP/IP in ROM, QFP100?
> 
> - jg


Also not a standard 40- or 44-pin package but also potentially
interesting are the Triscend E5 Configurable System-on-Chip (CSoC)
devices.  All four family members contain the following.

10 MIPS 8052 core
Two-channel DMA controller
Glueless memory interface to external Flash (up to 2MB code, 16MB
data)
JTAG port and hardware breakpoint unit eliminates need for emulator
Large XDATA RAM
Embedded LUT-based SRAM programmable logic matrix with integrated
high-speed bus

TE502:  8Kx8 XRAM,  256 CSL cells = ~3,200 gates, 52 to 76 user-I/O
TE505: 16Kx8 XRAM,  512 CSL cells = ~6,400 gates, 60 to 124 user-I/O
TE512: 32Kx8 XRAM, 1152 CSL cells = ~14,400 gates, 60 to 150 user-I/O
TE520: 40Kx8 XRAM, 2048 CSL cells = ~25,600 gates, 126 to 252 user-I/O

There is more information available at ...
http://www.triscend.com/products/IndexE5.html

I see that Dave Vanden Bout posted earlier.  His company XESS also has
an E5-based development board called myCSoC.  See ...
http://www.xess.com/prod022.php3

Similarly, check out these other E5 development boards ... 
http://www.triscend.com/products/indexdeve5.html

Steve Knapp
www.triscend.com

Article: 32840
Subject: Re: assigning signals with Altera Max+PlusII vhdl
From: timjeno@visto.com (Tim O'Connell)
Date: 10 Jul 2001 06:42:03 -0700
Links: << >>  << T >>  << A >>
I would like to know also.  I've never been able to get a constant
signal that way.  If I were to code it I would use the lines

SA <= "11110000";
SB <= "00001111";

instead of the initialization in the signal declaration.  This will
work.  I don't know why the initialization doesn't work though.


"Michael Johnen" <michajo@gmx.de> wrote in message news:<9iehkl$bub$1@nets3.rz.RWTH-Aachen.DE>...
> Hi all,
> 
> i try to learn vhdl and now i have problems
> i never had before:
> 
> the following code..........
> 
> entity TEST13 is
>     port (
>    I  : in bit;
>    AOUT : out bit_vector (7 downto 0));
> 
> end TEST13;
> 
> architecture TEST of TEST13 is
>     signal SA  : bit_vector (7 downto 0) := "11110000";
>     signal SB  : bit_vector (7 downto 0) := "00001111";
> 
> begin
> process (I)
>     begin
>         case I is
>             when '1' =>
>                 AOUT <= SA;
>             when '0' =>
>                 AOUT <= SB;
>        end case;
> end process;
> 
> end TEST;
> 
> ..........results in following (16) errors:
> 
> Error: Node ':109.IN1' missing source
>                 .....115.IN1...
>                 .....157..
> 
> What is wrong ???
> 
> Thanks,
> Michael

Article: 32841
Subject: FPGA on flex?
From: hitomiandanno@cs.com (Anno)
Date: 10 Jul 2001 07:16:16 -0700
Links: << >>  << T >>  << A >>
Good morning:

Does anyone know of a vendor who would sell a FPGA on a flex? Barring
that, are there any vendors who would put such a part on a flex (for
money, of course, but hopefully a limited amount of the same...)

Thanks,

Anno

Article: 32842
Subject: Adder/Subtracter Core???
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Tue, 10 Jul 2001 16:20:53 +0200
Links: << >>  << T >>  << A >>
Hi,

Using the Adder/Subtracter (for Spartan II), have noticed that while it
claims to be able to do 2's complement arithmatic, if I set both inputs to 4
bits, and set my output to 4 bits (I need to truncate result to 4 bits), the
core merely outputs the 4 most significant bits and doesn't maintain two's
complement outputs.

Does anyone know a way around this?

Adrian




Article: 32843
Subject: Re: FPGA on flex?
From: jschneider@cix.ceeowe.ewekay
Date: 10 Jul 2001 15:25:15 +0100
Links: << >>  << T >>  << A >>
hitomiandanno@cs.com (Anno) writes:

> Does anyone know of a vendor who would sell a FPGA on a flex?

Gosh. Money to be maid by simply sellotaping a chip to some cable.

        Jon



Article: 32844
Subject: XC17S00XL vs XC17S00A
From: jad@aedinc.net (Jason Daughenbaugh)
Date: 10 Jul 2001 08:11:06 -0700
Links: << >>  << T >>  << A >>
I am looking for an OTP SPROM in a 8-pin PDIP for a XC2S100.  

I found the XC17S00XL and XC17S00A, but what is the difference?

Why does Xilinx make both the XC17S100XL and the XC17S100A?  
The data sheets seem to be nearly word-for-word identical.
Or am I missing something?

Thanks in advance,
Jason Daughenbaugh
http://www.aedinc.net

Article: 32845
Subject: Re: Two's complement to binary translation problem
From: John_H <johnhandwork@mail.com>
Date: Tue, 10 Jul 2001 15:40:36 GMT
Links: << >>  << T >>  << A >>
To get 10 bits after the decimal in fixed binary for a positive number,
multiply the coefficient by 2^10 and use the rounded integer part.

  +0.12456985477 * 2^10 = 127.55953128448

so a 10-bit-after-decimal representation would be 128 (hex 0x080).

Two's complement of x is just ~x+1 in your 12-bit system (10 after
decimal, 1 before, plus sign) for

~0x080 + 1 = 0xf7f + 1 = 0xf80

which represents -0.125 (next possibility is about -0.12402).  This
approach should help you generate your coefficients with greater ease.

- John

Antonio wrote:

> Good Morning,
> my problem is that Matlab produce for me the coefficient
> -0.12456985477 that I've to translate in two's complement with one bit
> for the sign , one bit before the point and 10 bit later, may you tell
> me which string of binary number I've to put inside my FIR for this
> coefficient ??
>
> Thank you really much...
>
>                           Antonio D'Ottavio


Article: 32846
Subject: Re: What chip!?
From: Niki Steenkamp <steenkmp@ing.sun.ac.za>
Date: Tue, 10 Jul 2001 17:43:23 +0200
Links: << >>  << T >>  << A >>
Hi,

Eric Smith wrote:
> 
> cyber_spook <pjc@cyberspook.freeserve.co.uk> writes:
> > Why dose everyone suggest Xilinx? when there are *other* people out
> > there making FPGA's. We should not suggest that Xilinx is the world
> > standard as their are compines that don't use Xilinx chips and only use
> > one other make (ie Altera).
> >
> > Lets keep it balanced chaps, or we will have to start advertising within
> > our own messages. Worst still - someone will paten this group 8o) !
> 
> Hey, if people want Altera discussions on this NG, they should start some.
> This is a forum of the readers, by the readers, for the readers.  There
> aren't any people chartered to generate new interesting content and post
> it here.
I would like to start an Altera discussion on why I get so many
"Internal Errors" from MaxPlusII as soon as I try to use more
interesting VHDL.  ;-)
I wasted an afternoon trying to find such an error, when all what it
was, was a missing else clause.  The other day I wasted a whole day
trying to get the "for generate" construct to work with a 2 dimensional
array.  Eventually I gave up, compiled it in FPGA express and pulled in
the EDIF - no problems.  ...sigh...

I am starting to become more and more pro-3rd-party-tools.  (Not that
they don't have any problems, but lets leave it at that!)

Niki

-- 
.........-----====**====-----.........
Niki Steenkamp
Electronic Systems Laboratory (ESL)
University of Stellenbosch
South Africa
Tel. +27 21 8084934
http://sunsat.ee.sun.ac.za
--------------------------------------

Article: 32847
Subject: Re: Shift and Add Multiplier With Signed Numbers
From: Santiago de Pablo <sanpab@eis.uva.es>
Date: Tue, 10 Jul 2001 18:24:57 +0200
Links: << >>  << T >>  << A >>
Hi folks,

Philip Freidin escribió:
> 
> One solution is:
> Save the XOR of the MSB of both numbers.
> For each number, if the MSB is set, negate the number (make it positive)
> Do the multiply, N-1 steps, since MSBs are always '0'
> If the saved XOR result is set, negate the result.
> 
> Philip Freidin
> 
> On 8 Jul 2001 11:00:59 -0700, pmcguirk@mrcmicroe.com (Pat McGuirk) wrote:
> >Hi,
> >
> >I'm trying to implement a scaling multiplier for 2s complement
> >numbers.  I can't come up conceptually with how to do the shift and
> >adds and handle the signs.   If I want to multiply two numbers such as
> >-2 * -3, what should the partial products be ?
> >
> >Ex:
> >    1110     -2
> >    1101     -3
> >---------
> >11111110  -- Sign extend first partial product
> >00000000  -- Second partial product zero
> >11111000   -- Third partial product
> >????????  -- For this partial product I need -2^3 * (-2^3 + 2^2 + 2^1)
> > =                                             2^6 - 2^5 -2^4.

       1110 (-2)
       1101 (-3)
  ---------
   11111110 (-2)*1   * 1
   0000000  (-2)*2   * 0
   111110   (-2)*4   * 1
   11110    (-2)*8   * 1 -> (-2)*(8+16+32+64+128+...) =
   1110     (-2)*16  * 1  = (-2)*(1+2+4+8+16+...)*8 =
   110      (-2)*32  * 1  = (-2)*(-1)*8 ! = (+2)*8
   10       (-2)*64  * 1
   0        (-2)*128 * 1
  ----------
   00000110 (+6)

       1110 (-2)
       1101 (-3)
  ---------
   11111110 (-2)*1   * 1
   0000000  (-2)*2   * 0
   111110   (-2)*4   * 1
   00010    (+2)*8   * 1 !
  ----------
   00000110 (+6)

You may look at
http://www.dte.eis.uva.es/OpenProjects/OpenDSP/index.htm#CODIGOVERILOG.

Enjoy, Santiago.



> >
> >So, I guess I don't know the trick for representing this last partial
> >product, or I'm missing something obvious.  Or, do I have the wrong
> >approach for doing the scaling multiplier with 2s complement numbers?
> >Can anyone help out or provide a good reference for me?
> >
> >Thanks in advance,
> >Pat
> 
> Philip Freidin
> Fliptronics

Article: 32848
Subject: Re: Xilinx System Generator Simulation Problem
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Tue, 10 Jul 2001 10:30:54 -0600
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Since you indicated you are using ModeSIm XE, the solution is easy.  All you
need to do is go to the Xilinx Website and grab the updated libraries for
ModelSIM XE.  The web page is located at:
http://support.xilinx.com/support/mxelibs/index.htm and grab the D_IP4 libraries
for either VHDL or Verilog (which ever you are using).  Decompress the zip file
to your hard drive where MTI-XE is installed and you should be able to continue
your simulation.


--  Brian




JianYong Niu wrote:

> Hi, Ray:
> Thanks for your suggestion. I have solved the problem following your
> suggestion. However, new errors occured as follows:
>
> # -- Loading package standard
> # -- Loading package std_logic_1164
> # -- Compiling entity xlmult_core1
> # -- Compiling architecture behavior of xlmult_core1
> # ERROR: Could not find
> C:/modeltech_xe/xilinx/vhdl/XilinxCoreLib.mult_vgen_v2_0
> # ERROR: xlmult_core1.vhd(34): cannot find expanded name:
> xilinxcorelib.mult_vgen_v2_0
> # ERROR: xlmult_core1.vhd(34): Unknown field: mult_vgen_v2_0.
> # ERROR: xlmult_core1.vhd(59): VHDL Compiler exiting
> # ERROR: C:/Modeltech_xe/win32xoem/vcom failed.
> # Error in macro C:\MATLABR11\work\vcom.do line 26
> # C:/Modeltech_xe/win32xoem/vcom failed.
> #     while executing
> # "vcom -93 xlmult_core1.vhd"
>
> There is only mult_vgen_v1_0 in xilinxcorelib, but no mult_vgen_v2_0. Where
> can I find that mult_vgen_v2_0?  If it is a library update problem, where
> can I find the update file?
>
> I am using modelsim XE 5.3d with a starter's licence.
> Thanks
>
> Ray Andraka <ray@andraka.com> wrote in message
> news:3B38CD19.B9FC0B5@andraka.com...
> > You are pointing to the unisims source, not to a compiled library.  You
> need to
> > compile the unisim library with modelsim, and then the token should point
> to
> > the compiled library.  CHeck the answers data base on the xilinx website.
> There
> > are instructions there on how to compile the library, as well as tcl
> scripts to
> > do it.
> >
> > JianYong Niu wrote:
> >
> > > Hi, All:
> > >
> > > I am using Xilinx System Generator to design an application in Matlab
> > > simulink evironment. I use ModelSim starter version to simulate the
> design.
> > >
> > > Problems occured while the vcom.do file was excecuted:
> > >
> > > I have changed the %XILINX% token in the vcom.do file into the xilinx
> path
> > > in my computer. errors occured as follows:
> > >
> > > # ERROR: C:/XILINX/vhdl/src/unisims is not a valid library: no info
> file.
> > > # ERROR:
> C:/MATLABR11/toolbox/xilinx/sysgen/vhdl/synth_reg_w_init.vhd(14):
> > > Library unisim not found.
> > > # ERROR:
> C:/MATLABR11/toolbox/xilinx/sysgen/vhdl/synth_reg_w_init.vhd(15):
> > > Unknown identifier: unisim
> > > # ERROR:
> C:/MATLABR11/toolbox/xilinx/sysgen/vhdl/synth_reg_w_init.vhd(17):
> > > VHDL Compiler exiting
> > >
> > > what is the info file?
> > >
> > > I find a info file from my matlab work directory, and copied it into the
> > > xilinx unisims path. then the following errors occured when I run
> modelsim:
> > >
> > > ERROR: Could not find C:/XILINX/vhdl/src/unisims.vcomponents
> > > # ERROR:
> C:/MATLABR11/toolbox/xilinx/sysgen/vhdl/synth_reg_w_init.vhd(15):
> > > cannot find expanded name: unisim.vcomponents
> > > # ERROR:
> C:/MATLABR11/toolbox/xilinx/sysgen/vhdl/synth_reg_w_init.vhd(15):
> > > Unknown field: vcomponents.
> > > # ERROR:
> C:/MATLABR11/toolbox/xilinx/sysgen/vhdl/synth_reg_w_init.vhd(17):
> > > VHDL Compiler exiting
> > > # ERROR: C:/Modeltech_xe/win32xoem/vcom failed.
> > >
> > > However, I do find a file 'unisims.vcomp' in the directory. what is the
> > > problem?
> > >
> > > thanks.
> > >
> > > Jianyong
> >
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> >

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Article: 32849
Subject: ATMCAM & UTOPIA Bus in VHDL
From: bhamon@elios-informatique.fr (=?ISO-8859-1?Q?Beno=EEt?=)
Date: 10 Jul 2001 09:34:38 -0700
Links: << >>  << T >>  << A >>
Hi all,

I'm trying to Simulate in VHDL  the ATMCAM (MU9C4320L) from MUSIC
Semiconductors. I have to use a Utopia 16bit generator too.

Do you know where I could find an example (core, ..) in VHDL or Verilog to
simulate these modules ?.

thanks in advance,

Benoit.



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