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Messages from 32700

Article: 32700
Subject: Re: Driven clocks balancing
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Thu, 5 Jul 2001 12:17:31 +0100
Links: << >>  << T >>  << A >>
Easiest solution is probably to copy the 'logic-available clock'
section from the Xilinx DDR Application Note.

"Rotem Gazit" <rotemg@mysticom.com> wrote in message
news:86b060d0.0107042309.213ce7b7@posting.google.com...
> Hi,
>
> I need to drive 4 identical clocks out of my Virtex-E FPGA.
> I have to align the 4 pins on the same side of the chip, where 2 of
> those pins are at the corners and 2 of those pins are in the middle.
> Because of other logic on the FPGA I can spare only one or two DLLs
> for driving the 4 clocks .
> The clocks are related to data , also driven from the FPGA,  so I
> cannot use tricks like dividing clkx2 near the output pines.
> Is there any way to balance the routing delay inside the FPGA ,from
> the DLL to the 4 output pins ?
> After the routing has been balanced can it be fixed , so it will not
> change when the design will be re-implemented ?
>
> Thanks,
>
> Rotem Gazit
> MystiCom LTD
>
> mailto:rotemg@mysticom.com
> http://www.mysticom.com/



Article: 32701
Subject: Re: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (1/1)
From: Dave Colson <dscolson@rcn.com>
Date: Thu, 05 Jul 2001 08:25:53 -0400
Links: << >>  << T >>  << A >>
Mike,
Very nice. Can you add multiple entities to it? I have a testbench that
needs several other entities to run.
Any Doc yet?
Dave Colson

Mike Hicks wrote:

>                  Name: tb_gen.tcl
>    tb_gen.tcl    Type: TCL Program (application/x-tcl)
>              Encoding: x-uuencode


Article: 32702
Subject: Re: 8031 microcontroller on FPGA development board :-(
From: Keith R. Williams <krw@attglobal.net>
Date: Thu, 5 Jul 2001 08:57:57 -0400
Links: << >>  << T >>  << A >>
In article <3B442DCA.609A753@ing.sun.ac.za>, steenkmp@ing.sun.ac.za 
says...
> 
> 
> "Keith R. Williams" wrote:
> > 
> > In article <c2ec2c5b.0107040649.522dca1e@posting.google.com>, throne7
> > @my-deja.com says...
> > > I notice that some of the development boards e.g. xess and burched
> > > use the 8031 microcontroller.  I am wondering why the older 8031 is
> > > used
> > > instead of the 8051??  I personally would like to learn to assembly
> > > program
> > > for the 8051 instead so would it be a waste to order one of these
> > > boards
> > > and end up knowing code for the inferior 8031?  Maybe its not too bad
> > > if the 8031 is used widely in industry, how widely used is the 8031?
> > 
> > The 8031 is an 8051 with no (or disabled) on board code memory. They're
> > the same processor, same instruction set.
> The only significant difference, besides the on board code memory, is
> that the 8031 has 128 bytes of RAM while the 8051 has 256.  Also, AFAIK,
> the 8051 also has one additional timer (timer 2).

No, the 8031 (with no modifiers) is identical to the 8051 and only has 
128 bytes of RAM.  In fact some of the early 8031s were someone's 8051s 
with a bad mask ROM.  Now, there are variations on the 8051 that have 
256bytes of RAM and all sorts of other widgets, but they are not 8051s.  
For example, I'm using (a now antique - first used them in 1989) 
87C51FC, which does have 256bytes of RAM, 32KB code memory, a timer-
counter array, UART, and a bunch of other widgets.

----
   Keith

Article: 32703
Subject: Aldec Active-HDL 4.2 Windows 2000 Verilog back anno Xilinx problems
From: Dave Colson <dscolson@rcn.com>
Date: Thu, 05 Jul 2001 09:02:35 -0400
Links: << >>  << T >>  << A >>
Hello,

I am trying to evaluate Aldec 4.2 under windows 2000, full capabilities
with latest service pack installed. However, a back annotated Xilinx
Spartan design ( done with the Web_pack software) does not simulate
properly. This exact same design runs fine under two other simulators. A

functional simulation of this design works OK.

Has anyone had a similar experience?

Thanks
Dave Colson


Article: 32704
Subject: Re: How to estimate the number of CLBs ?
From: "Jamie Sanderson" <jamie@nortelnetworks.com>
Date: Thu, 5 Jul 2001 09:05:07 -0400
Links: << >>  << T >>  << A >>
The Virtex II has 4 slices per CLB, instead of the 2 found in Virtex/E.

Cheers,
Jamie

"Ray Andraka" <ray@andraka.com> wrote in message
news:3B43B901.B4BA324@andraka.com...
> Look at the structure of the chip.  Each CLB contains 2 slices, each of
> which has 2 flip-flops, 2 4 input look-up tables,  and a dedicated carry
> chain each running through both LUTs.
<cut>

> vhdl wrote:
>
> > I'm targeting Virtex II, I need to have an estimate for my design.
> > I didnot entered in Xilinx tools. But I want to know
> > like an adder 12bits, a multiplier 12x12 bits, a flip-flop
> > How many CLBs they use ? is there a data book/sheet with
> > estimate of chip area used by library element ?
<cut>



Article: 32705
Subject: Re: 8031 microcontroller on FPGA development board :-(
From: Dave Vanden Bout <devb@xess.com>
Date: Thu, 05 Jul 2001 09:41:26 -0400
Links: << >>  << T >>  << A >>
Niki Steenkamp wrote:

>
> The only significant difference, besides the on board code memory, is
> that the 8031 has 128 bytes of RAM while the 8051 has 256.  Also, AFAIK,
> the 8051 also has one additional timer (timer 2).

No, I believe the 8032/8052 micros are the ones with 256 bytes of internal
RAM and three timers.  The 8031/8051 micros only have 128 bytes and two
timers.  At least that was the case with the Intel and Winbond versions.

My apologies as I think we have drifted out of the comp.arch.fpga topic
area....



--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||



Article: 32706
Subject: Re: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (0/1)
From: Nial Stewart <nials@sqf.hp.com>
Date: Thu, 05 Jul 2001 16:17:05 +0100
Links: << >>  << T >>  << A >>
Mike Hicks wrote:
> 
> This Tcl/Tk based VHDL testbench generator, like everything else,
> could probably use some improvement, but it works well enough to keep
> you from retyping all those port entity names everytime you create a
> new testbench. It's been tested on Windoz and SuSE Linux so far. If
> you improve it, please post your improvement for the rest of us.
>         Mike Hicks


Mike,

_What_ Tcl/Tk based VHDL testbench generator is that then?

Sounds useful.

Nial.

Article: 32707
Subject: Re: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (0/1)
From: Nial Stewart <nials@sqf.hp.com>
Date: Thu, 05 Jul 2001 16:25:48 +0100
Links: << >>  << T >>  << A >>
Mike Hicks wrote:
> 
> This Tcl/Tk based VHDL testbench generator, like everything else,
> could probably use some improvement, but it works well enough to keep
> you from retyping all those port entity names everytime you create a
> new testbench. It's been tested on Windoz and SuSE Linux so far. If
> you improve it, please post your improvement for the rest of us.
>         Mike Hicks
>         Computer Design Matrix
>         mrmikehicks[at]yahoo.com

Mike,

Further to my comment above, it looks like Nutscrape doesn't
pick up attachments, or something's blocking the binaries
on the server I'm on.

Would there be any chance of sticking it on a web site with 
a URL to it?

Nial.

Article: 32708
Subject: Downloading file to Xilinx (Vertex_E) FPGA.
From: subodh@best.com (Subodh Nijsure)
Date: Thu, 5 Jul 2001 16:44:13 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hello,

Is the following sequence to download bit file to Xilinx Vertex_E correct?
I am using CPLD which to send bit stream to FPGA.

Here are the steps I am doing from my Linux driver that downloads the
bitstream to the FPGA.

1. Hold PROGRAM high wait for 400 us 
2. Hold PROGRAM low, monitor the INIT pin, wait for it to go high, this
will indicate FPGA has cleared the memory.

3. Then hold PROGRAM pin high, CCLK 0, send data bit 0, 
4. Then hold PROGRAM pin high, CCLK 1, send data bit 0, 
Repeat steps 3 through 4 for entire .bit file. 

Now monitor the DONE pin if its high everything is okay else FPGA download
failed.

WHat I have observed is after step 2 above if i wait for 100 us and go
back and check the INIT pin it has gone low, I haven't sent any data bits 
to FPGA yet. So if INIT pin has gone low (0) should I still continue to
send data? 
Also in steps 3 and 4 should one be checking if INIT has gone low or DONE
has gone high?

/Subodh Nijsure

Article: 32709
Subject: Re: How to estimate the number of CLBs ?
From: Ray Andraka <ray@andraka.com>
Date: Thu, 05 Jul 2001 16:56:58 GMT
Links: << >>  << T >>  << A >>
That is correct.  I missed the II when I quickly read the question.  The
multipliers in his design can be done in the dedicated multiplier resources in
VirtexII as well.  Each of the multipliers is an 18x18 multiplier.  The XC2V40
has 4 of them, and these can be run in non-pipelined mode up to about 140 MHz
for 18 bit inputs, faster if the input sizes are reduced.  Refer to the
VIrtexII data sheet on the Xilinx website.

Jamie Sanderson wrote:

> The Virtex II has 4 slices per CLB, instead of the 2 found in Virtex/E.
>
> Cheers,
> Jamie
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3B43B901.B4BA324@andraka.com...
> > Look at the structure of the chip.  Each CLB contains 2 slices, each of
> > which has 2 flip-flops, 2 4 input look-up tables,  and a dedicated carry
> > chain each running through both LUTs.
> <cut>
>
> > vhdl wrote:
> >
> > > I'm targeting Virtex II, I need to have an estimate for my design.
> > > I didnot entered in Xilinx tools. But I want to know
> > > like an adder 12bits, a multiplier 12x12 bits, a flip-flop
> > > How many CLBs they use ? is there a data book/sheet with
> > > estimate of chip area used by library element ?
> <cut>

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 32710
Subject: Arc Tangente and Square Root algorithms
From: Fredj Rouatbi <vhdluser@MailAndNews.com>
Date: Thu, 5 Jul 2001 14:17:33 -0400
Links: << >>  << T >>  << A >>
I'm looking for Arc Tangent and Square root algorithms.
For I and Q of 8 bits. How many Clbs they consume.

THX Fredj


Article: 32711
Subject: Re: poor man's floating point...
From: gah@ugcs.caltech.edu (glen herrmannsfeldt)
Date: 5 Jul 2001 18:25:15 GMT
Links: << >>  << T >>  << A >>

On 3 Jul 2001 11:11:40 -0700, dpariseau@compuserve.com (David Pariseau) wrote:
>Actually I do know exactly what I want to do but I probably didn't
>do a great job of explaining it.  It's somewhat similar to companding
>but it's exactly floating point notation.
>
>I want to start with a value that's 27 bits wide... 
>   BTime <something>(26 downto 0)
>and stuff the manipulated value into a value that's 16 bits wide...
>   FOut <something>(15 downto 0)
(snip)

A google search for mu law comes up with articles on both mu-law and
a-law encoding.  The page with both formulae seems to be:

http://www.epanorama.net/documents/telecom/ulaw_alaw.html

It is not exactly like floating point, though mu-law is closer.
It is important to make the transition though zero smooth, where
this is not normally so important in floating point math.

I believe that both are usually implemented as look-up tables,
as could your floating point representation.

-- glen


Article: 32712
Subject: Re: 8031 microcontroller on FPGA development board :-(
From: "Spehro Pefhany" <speff@interlog.com>
Date: Thu, 05 Jul 2001 18:25:24 GMT
Links: << >>  << T >>  << A >>
In comp.arch.fpga Niki Steenkamp <steenkmp@ing.sun.ac.za> wrote:

> The only significant difference, besides the on board code memory, is
> that the 8031 has 128 bytes of RAM while the 8051 has 256.  Also, AFAIK,
> the 8051 also has one additional timer (timer 2).

No, you are thinking of the 8032/8052 vs. the 8031/8051. 

      ROM       RAM  TIMERS
8031   0        128    2
8032   0        256    3
8051  4K x 8    128    2
8052  8K x 8    256    3

Best regards, 
-- 
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
Spehro Pefhany --"it's the network..."            "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com
Contributions invited->The AVR-gcc FAQ is at: http://www.BlueCollarLinux.com
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

Article: 32713
Subject: AMS Wildstar Board
From: sandra.a.nielsen@boeing.com (Sandra Nielsen)
Date: 5 Jul 2001 12:26:35 -0700
Links: << >>  << T >>  << A >>
Hi,

Sorry in advance for a dumb question from a newbie.  I'm looking for
information on the AMS Wildstar board.  Can anyone point me in the
right direction?

Thank you,
Sandra

Article: 32714
Subject: low skew in vertex II
From: tiderh <tiderhuang@yahoo.com>
Date: Thu, 5 Jul 2001 15:28:08 -0700
Links: << >>  << T >>  << A >>
Hi, 
There are 2000 2to1 mux in vertex2V3000 of my design. The mux's are in different columns. How can I make the mux selection control signal 'Sel' has very low skew? Can I use the BUFG to buffer the 'Sel', then use BUFG output to drive the 2000 mux's? or use the register duplication or using low skew resources constraint to minimize the skew? Thanks a lot.

Article: 32715
Subject: Re: Arc Tangente and Square Root algorithms
From: Ray Andraka <ray@andraka.com>
Date: Thu, 05 Jul 2001 22:31:29 GMT
Links: << >>  << T >>  << A >>
I suspect you are trying to do cartesian to polar conversions and have
already figured out how to do the squares.  I'd recommend using the
CORDIC algorithm instead, which is an algorithm for performing vector
rotations using just shifts and adds.  In the "vectoring" mode, the
vector gets rotated to the I axis where you can read the magnitude
directly and you can record the history of elemental rotations to
determine phase.  I have a paper on my website (A survey of CORDIC...)
which serves as a decent introduction to the algorithm and also
discusses FPGA implementations.

In answer to your questions on size, it depends on what your available
clock and desired performance are.  A fully parallel unrolled 8 bit
CORDIC will take up a 5x8 CLB tile in virtex, not including the gain
correction (which is done with a constant coef multiplier, if needed).
The paper describes an XC4000 design that occupies 22 CLBs for a bit
serial iterative design (would be around 10 Virtex CLBs).

Fredj Rouatbi wrote:

> I'm looking for Arc Tangent and Square root algorithms.
> For I and Q of 8 bits. How many Clbs they consume.
>
> THX Fredj

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 32716
Subject: Re: AMS Wildstar Board
From: Ray Andraka <ray@andraka.com>
Date: Thu, 05 Jul 2001 22:36:43 GMT
Links: << >>  << T >>  << A >>
have you tried http://www.annapmicro.com?

What information are you looking for specifically?

Sandra Nielsen wrote:

> Hi,
>
> Sorry in advance for a dumb question from a newbie.  I'm looking for
> information on the AMS Wildstar board.  Can anyone point me in the
> right direction?
>
> Thank you,
> Sandra

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 32717
(removed)


Article: 32718
(removed)


Article: 32719
Subject: Best JTAG H/W, S/W for most meaningful debug info?
From: arast@inficom.com (Alex Rast)
Date: Thu, 05 Jul 2001 22:46:46 GMT
Links: << >>  << T >>  << A >>
We are in the process of trying to get a board up and running that has a CPLD 
on board (a xilinx XC95144) I've run the programming step several times 
through the Xilinx software and MultiLinx cable with no success. It gives the 
same old message (familiar to many) - 
"...boundary-scan chain test failed at bit position '7' on instance 
'DesignFile(Device1)'..."

In the past I had similar problems with the same board and eventually got it 
to work, but I can't remember everything that's involved and I suspect the 
notes I have left out a key step.

Really, though, the bigger problem is that the Xilinx suite doesn't give back 
very meaningful debugging information as to what actually happened. What I'd 
like to find, then, is some software or hardware that will give me more 
comprehensive and useful feedback on everything that's going on as I attempt 
to program the device. It would be particularly valuable to see details on the 
JTAG boundary-scan chain itself because I'm wondering if there's something 
amiss in the chain, in which case that's what I need to debug. Are there any 
tools out there that let you debug problems with the JTAG chain itself? In any 
case, what software and/or hardware, in your experience, gives the greatest 
amount of meaningful debugging data with JTAG?

Thanks.

Alex Rast
arast@inficom.com
arast@qwest.net

(please respond to both e-mail addresses, yes, they *do* both work as of July 
5, 2001)

Article: 32720
Subject: Re: 8031 microcontroller on FPGA development board :-)
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Fri, 06 Jul 2001 11:02:57 +1200
Links: << >>  << T >>  << A >>
Dave Vanden Bout wrote:
> 
> Niki Steenkamp wrote:
> 
> >
> > The only significant difference, besides the on board code memory, is
> > that the 8031 has 128 bytes of RAM while the 8051 has 256.  Also, AFAIK,
> > the 8051 also has one additional timer (timer 2).
> 
> No, I believe the 8032/8052 micros are the ones with 256 bytes of internal
> RAM and three timers.  The 8031/8051 micros only have 128 bytes and two
> timers.

This is correct.
The 8031/51 as single chip is starting to 'drop off the bottom', as the 
more usefull 8052(89C52) is close in price.
However, ROMless 8031/32 are still very cheap, well under $1, so soft
cores have a way to go yet :-)

If you have a FPGA Board, with a '8031' socket, then ANY package
compatible
family member can be used.
There are quite a few 'more current' members worthy of going alongside a
FPGA,
and with greatly increased speeds, more compatible with FPGA systems. 

o Dallas DS89C420 = 50 MIPS, 8052 core, 16K FLASH, 1K XRAM, 2 UART 5V
o Winbond W77LE58 = 6-10 MIPS, 8052 core, 32K FLASH, 1K XRAM, 3-5V
o Temic T89C51RD2 = 5 MIPS, 8052 Core, 64K Flash, 2KEE, 1K RAM, 3-5V

Not a 'std' 40/44 package, but interesting is
o Dallas 80C400 = 10 Mips, Ethernet, CAN, TCP/IP in ROM, QFP100?

- jg

Article: 32721
Subject: Re: XC9500 drive capability
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Fri, 06 Jul 2001 11:41:29 +1200
Links: << >>  << T >>  << A >>
Rick Filipkiewicz wrote:
> 
> Peter Alfke wrote:
> 
> > Yes, it works. All these output structures are almost the same.
> > The issue is to what extent the current divides equally between
> > the two drivers. And if they have the same basic characteristic,
> > and are adjacent on the die, they track very well.
> >
> > Peter Alfke, Xilinx Applications
> >
> > Vitali wrote:
> >
> > > Hello,
> > >
> > > can I double current sink capability by tying two output pins?
> > > I know it runs on FPGAs (on "senior" XC4000s). How about CPLDs?
> > >
> > > Thanks
> > >
> > > Vitali.
> 
> How can you tell which IOs are next to each other on the die for an
> XC95K part ? For Virtex devices you can get this info from a .par report
> file.

 Look at the pinout of the largest package version of that die - bond
wires
do not cross - but sometimes IO pads as skipped in smaller packages.

 Other tips when 'pushing' current :-

- Choose drivers closest (Adjacent) to GND pins, in preferance to ones
further away

- We do LED driver designs using Atmel ATF15xx'L' devices, where the L 
variants have sub mA core Icc, so the package/bond/thermal capability
are all available for
LED drivers.
 Other CPLD have high static Idd, which lowers the load power budget.

- Newest 5V relays are candidates for CPLD driving, from shared pins.
 ( We are looking into this  )

-jg

Article: 32722
Subject: Re: Best JTAG H/W, S/W for most meaningful debug info?
From: "Daniel J. Morelli" <dmorelli@zoominternet.net>
Date: Thu, 5 Jul 2001 20:16:21 -0400
Links: << >>  << T >>  << A >>
Alex

I may be able to solve your problem.  I wrote a program for a customer I had
last year that used the JTAG port to program the FPGA (Spartan), test the
FPGA and SA1100 processor interface and then flash the board all through the
parallel port using a DOS based program.  The program used the BSDL files to
create a link list representation of the JTAG chain and then I manipulated
the link list structure to talk to the board via the JTAG port.  The program
is pretty flexible so it may work for you.  If you can are interested send
me an email and I will give you my contact information.

Daniel Morelli
Advantage Custom Chips, Inc.






-----= Posted via Newsfeeds.Com, Uncensored Usenet News =-----
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Article: 32723
Subject: Re: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (1/1)
From: edick@hotmail.com (Richard Erlacher)
Date: Fri, 06 Jul 2001 01:22:19 GMT
Links: << >>  << T >>  << A >>
How was this message encoded?

Dick

On Thu, 05 Jul 2001 04:02:10 GMT, bhicks02@tampabay.rr.com (Mike
Hicks) wrote:

>begin 644 tb_gen.tcl
>M.R,M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM
>M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+3L-"CLC('1B7V=E
<snip>

Article: 32724
Subject: Spartan-II (XC2S200) Configuration Help~ DONE doesn't go HIGH
From: donald7@dreamwiz.com
Date: Fri, 06 Jul 2001 01:27:22 GMT
Links: << >>  << T >>  << A >>
hello,

please help me with configurating Spartan-II~
DONE pin never goes to HIGH, INIT pin remains LOW, and CCLK sends
clocking signals continuously...
And two power sources are input to the device, 2.5V for core and 3.3V
for  I/O separately. But the resistor value measured between VCCO pin
and VCCINT is about 26 ohm. Is it normal? Or my chip is broken??

Any advices welcome :)
donald



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2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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