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Messages from 32950

Article: 32950
(removed)


Article: 32951
Subject: PCI arbiter core
From: Sebastien <sebastien.p-auguste@avnet.com>
Date: Thu, 12 Jul 2001 12:41:48 -0700
Links: << >>  << T >>  << A >>
Hi all,

I am looking for a PCI arbiter
"core" that could be dropped in a Xilinx FPGA. Preferably a V-2 part. Would you have any idea who would have that?

Article: 32952
Subject: Re: Xilinx BRAM failures
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Thu, 12 Jul 2001 12:47:01 -0700
Links: << >>  << T >>  << A >>
Achlys wrote:
> 
> Is anyone experiencing block ram failures in Xilinx Virtex-E devices?
> We've seen a condition where different bit files will cause hard
> failures on a small percentage of the parts. 
. . .
> Re-synthesising the design helps sometimes but not always.
> Working boards will fail with new bit files. We've seen the failure on
> multiple parts and on multiple designs.



Sounds like a race condition somewhere.
Did static timing run ok?

  


  --Mike Treseler

Article: 32953
Subject: Re: DLL Phase Locking in Division Mode
From: John_H <johnhandwork@mail.com>
Date: Thu, 12 Jul 2001 20:06:17 GMT
Links: << >>  << T >>  << A >>
Kevin Neilson wrote:

> The DLL doesn't seem to take into account the delay
> across the BUFG in 1/2x mode.  Am I wrong?

If the output of the BUFG is what you want phase aligned to the reference, then
the feedback should also go through a BUFG.  The 1/2x, 1x, and 2x outputs should
all be phase aligned to each other so the feedback delay should also be matched
to the clock distribution delay by using the extra BUFG.

Austin - do you agree?


Article: 32954
Subject: Re: PCI arbiter core
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 12 Jul 2001 22:32:14 +0200
Links: << >>  << T >>  << A >>
Sebastien <sebastien.p-auguste@avnet.com> writes:

> Hi all,
> 
> I am looking for a PCI arbiter
> "core" that could be droped in a Xilinx FPGA. Preferably a V-2 part. Would you have any idea who would have that?

A PCI arbiter is not hard to do yourself, especially if yuou have an
embedded system, where you don't have to take into account all the
buggy PCI board out there.

How many initiators are you looking for?

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se

Article: 32955
Subject: Re: Xilinx makefile under RedHat
From: frank bergmann <frank.bergm@gmx.de>
Date: Thu, 12 Jul 2001 23:04:51 +0200
Links: << >>  << T >>  << A >>
try:
http://www.polybus.com/xilinx_on_linux.html

frank

Article: 32956
Subject: How to fan out signals to bus lines in Xilinx Foundation Schematic Editor?
From: arast@inficom.com (Alex Rast)
Date: Thu, 12 Jul 2001 22:58:54 GMT
Links: << >>  << T >>  << A >>
I am running into an irksome difficulty with Xilinx' Schematic editor in 
Foundation. To give you the background, my design is a memory controller, 
interfacing a main processor to various different memory types. It does memory 
transfers and also loads the processor boot code from flash memory. There are 
2 basic, related problems.

1) I have a signal (STARTUP) that is the output of a nor-gate, indicating that 
the system has just powered up. In this condition, the memory controller needs 
to issue an instruction, which I store in register INSTR, that begins the boot 
process by starting the flash memory transfer to the main processor (MPU). 
INSTR is a 16-bit register, and the instruction opcodes are rationalized, so 
that each bit indicates a specific, binary-separable pair of states. So, if 
STARTUP is high, I need to write a well-defined bit-pattern to INSTR. 

As I see it, the most efficient way to do this is to drive the bits (input bus 
lines) of INSTR corresponding to HIGHs in the instruction I need to issue with 
STARTUP. So, basically, I need to connect the output of the nor to multiple 
different bus lines in the input of INSTR. Now, since INSTR is a 16-bit 
register, I have connected a 16-bit bus (MAINBUS[0:16]) to its input. But now, 
if I need to set bits 0,1,3,5 and 10 to HIGH when STARTUP is high, that means 
connecting MAINBUS0, MAINBUS1...MAINBUS 10 to the output of the nor-gate. If I 
do that, however, the Xilinx software complains: shorting 2 nets. And it won't 
allow the operation. So I'm stymied. All I need to do is connect the output of 
the nor-gate to multiple different lines on a bus, but the S/W doesn't want to 
let me do that. How do I then achieve what I need?

2) I have a common internal bus (INTBUS[0:31]) that could be driven from 
multiple sources, including registers and some I/O buffers. Of course, only 
one source drives the bus at any one time: I tristate the outputs of all 
sources except the current bus master. 

So the bus just has a bunch of tristate buffers connected to it, with some 
logic to drive the tristate signals on the buffers. But if I connect up the 
buffers to the bus, as soon as I run implementation, the software complains 
"multiple drivers for net: INTBUS0", and INTBUS1, INTBUS2,...INTBUS31. So 
again, the software doesn't like this, and I'm at an impasse. What is 
necessary to get around this problem?

As a general rule, the Xilinx software just doesn't seem to work well with 
situations where you've got multiple fanouts or fanins to a bus. Is there a 
general method, alternative software, workaround, etc. that people have used 
to eliminate this problem?

Thanks.

Alex Rast
arast@inficom.com
arast@qwest.net

Article: 32957
Subject: Re: Xilinx makefile under RedHat
From: Duane Clark <junkmail@junkmail.com>
Date: Thu, 12 Jul 2001 16:46:43 -0700
Links: << >>  << T >>  << A >>
Clyde R. Visser wrote:

> Someone some time back said that they do 95% of their
> xilinx builds under RedHat and had a URL documenting it.
> Anybody have the related URL?
> 
> crv

That was possibly me, since I have made similar claims here in the past. 
I do 100% of my Xilinx builds in Redhat, using Windoze only for 
synthesis (though I hope to change that soon). However I use scripts 
rather than makefiles, though my scripts are much more elaborate than 
those on polybus. In particular, I check returned error codes and stop 
when there is a problem. In principle, makefiles should work fine 
though, and that is another thing I was planning to do soon.

-- 
My real email is akamail.com@dclark (or something like that).


Article: 32958
Subject: reading a vcd file into verilog xl
From: cjwang_1225@hotmail.com (chris)
Date: 12 Jul 2001 18:17:05 -0700
Links: << >>  << T >>  << A >>
hi all.
i am trying to re-create a problem found on an fpga and so i need to
read a .vcd file into our simulator...verilog-xl. does anyone know how
this is done?
thanks.
chris

Article: 32959
Subject: Re: ne one knows wat this AHDL code is doing??
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Fri, 13 Jul 2001 11:38:24 +1000
Links: << >>  << T >>  << A >>
p186_read    : NODE;
p186_write    : NODE;

p186_read = !/up_cs5 & !/up_rd;
p186_write = !/up_cs5 & !/up_wr;

When /up_cs5 and /up_rd pins go low, p186_read is asserted.
Similar for p186_write.

Abhimanyu Rastogi wrote:
> 
> Hello all,
> 
> I have been working on this AHDL code but i don't understand how the
> register mapping works when chip select /up_cs5 is set....  i would also
> appreciate if someone can cooment the code....
> 
> Thx for ur help
> Abhimanyu Rastogi
> 2nd year student
> University of Ottawa
> Canada
> 
> --  Include Section
> include "2x8mux.inc";
> 
> --  Title Section
> TITLE "NORMAL RUN MODE CONFIGURATION";
> 
> --  Constant Section
> 
> --  Options Section
> -- OPTIONS BIT0 = LSB;
> 
> --  Subdesign Section
> SUBDESIGN RM2RUNA
> (
> -- micro I/O pins
>  upa[19..8]               :INPUT;
>  upad[7..0]               :BIDIR;
>  up_ale , /up_bhe , /up_rd , /up_wr , /up_ucs , /up_lcs    :INPUT;
>  /up_cs0 , /up_cs1 , /up_cs2 , /up_cs3 , /up_cs4 , /up_cs5    :INPUT;
>  up_int4 , /up_reset              :OUTPUT;
> 
> -- printer interface port I/O pins
>  prtd[7..0] , prt_strb             :INPUT;
>  prt_ack , prt_busy , prt_paper , prt_slct , /pr_en      :OUTPUT;
> 
> -- micro flash , sram I/O pins
>  ma[18..0] , /cs_flash , /rd_flash , /we_ldbfl , /we_udbfl    :OUTPUT;
>  /cs_upram1 , /cs_upram2 , /we_ldbupr , /we_udbupr , /rd_upram  :OUTPUT;
> 
> -- dsp I/O pins
>  /cs_dsp1 , /we_dsp1 , /cs_arctic1 , /rd_arctic1 , /we_arctic1   :OUTPUT;
>  /cs_dsp2 , /we_dsp2 , /cs_arctic2 , /rd_arctic2 , /we_arctic2   :OUTPUT;
>  /dspa_reset , /dspb_reset            :OUTPUT;
> 
> -- misc I/O pins
>  in_clk , sel[4..0] , XI[6..0]          :INPUT;
>  tp5 , tp6 , tp7 , tp8 , tp9 , sw_on , XO       :OUTPUT;
> )
> 
> --  Variable Section
> VARIABLE
> ma[18..0]    : DFFE;
> lobyte     : DFFE;
> hibyte     : DFFE;
> micro_reset    : DFFE;
> -- in_clk     : JKFF;
> 
> pr_addr[7..0]   : DFFE;
> pr_to_p186[7..0]  : DFFE;
> pr_rcv_rdy    : SRFFE;
> xmt_rdy_inten   : DFFE;
> pr_xmt_rdy    : NODE;
> rcv_rdy_inten   : DFFE;
> p186_dspa_run   : DFFE;
> p186_dspb_run   : DFFE;
> panel_switch   : DFFE;
> pr_rd     : SRFFE;
> prd_en     : NODE;
> pr_readbus[3..0]  : NODE;
> pr_read_hi_P186   : NODE;
> pr_write_data   : NODE;
> pr_write_ctrl   : NODE;
> 
> p186_to_pr[7..0]  : DFFE;
> p186_rdmux    : 2x8mux;
> p186_rdmux_tri[7..0] : TRI;
> p186_rcv_rdy   : SRFFE;
> p186_xmt_rdy   : NODE;
> p186_read    : NODE;
> p186_write    : NODE;
> p186_read_data   : NODE;
> p186_write_data   : NODE;
> p186_write_ctrl   : NODE;
> 
> strb[7..0]    : DFFE;
> wr_lobyte    : NODE;
> wr_hibyte    : NODE;
> card_en     : NODE;
> pr_strb_latch   : SRFF;
> pr_strb_latchsr[1..0] : DFF;
> strb_on[1..0]   : DFF;
> strb_off[1..0]   : DFF;
> 
> --  Logic Section
> BEGIN
> 
> DEFAULTS
> (/dspa_reset , /dspb_reset) = GND;
> (/up_reset) = VCC;
> (/cs_flash , /rd_flash , /we_ldbfl , /we_udbfl , /cs_upram1 , /cs_upram2 ,
> /we_ldbupr , /we_udbupr , /rd_upram) = VCC;
> (/cs_dsp1 , /we_dsp1 , /cs_dsp2 , /we_dsp2) = VCC;
> (/cs_arctic1 , /rd_arctic1 , /we_arctic1 , /cs_arctic2 , /rd_arctic2 ,
> /we_arctic2) = VCC;
> (rcv_rdy_inten , xmt_rdy_inten) = GND;
> END DEFAULTS;
> 
> -- micro address latch
>  (ma[] , lobyte , hibyte).clk = !up_ale;
> -- (ma[] , lobyte , hibyte).ena = up_ale;
>  ma[] = (upa[19..8] , upad[7..1]);
>  lobyte = !upad[0];
>  hibyte = !/up_bhe;
>  wr_lobyte = lobyte & !/up_wr;
>  wr_hibyte = hibyte & !/up_wr;
> 
> -- micro flash and sram address decode
>  if(!/up_rd) THEN (/rd_flash , /rd_upram) = GND; END IF;
>  if(!/up_lcs) THEN /cs_upram1 = GND; END IF;
>  if(!/up_cs0) THEN /cs_upram2 = GND; END IF;
>  if(!/up_ucs) THEN /cs_flash = GND; END IF;
>  if(wr_lobyte) THEN (/we_ldbupr , /we_ldbfl) = GND; END IF;
>  if(wr_hibyte) THEN (/we_udbupr , /we_udbfl) = GND; END IF;
> 
> -- dsp sram address decode
>  if(!/up_wr) THEN (/we_dsp1 , /we_dsp2) = GND; END IF;
>  if(!/up_cs1 & !/dspa_reset) THEN /cs_dsp1 = GND; END IF;
>  if(!/up_cs2 & !/dspb_reset) THEN /cs_dsp2 = GND; END IF;
> 
> -- dsp arctic chip address decode
>  if(!/up_wr) THEN (/we_arctic1 , /we_arctic2) = GND; END IF;
>  if(!/up_rd) THEN (/rd_arctic1 , /rd_arctic2) = GND; END IF;
>  if(!/up_cs3) THEN /cs_arctic1 = GND; END IF;
>  if(!/up_cs4) THEN /cs_arctic2 = GND; END IF;
> 
> --
> -- printer port I/O logic
> --
> -- printer reg map (xx denotes 5 bit card address):
> --  addr  function
> --  xx0 ... read status #1
> --  xx1 ... read status #2
> --  xx2 ... read lo nibble P186 data port
> --  xx3 ... read hi nibble P186 data port
> --  xx4 ... write control reg
> --  xx5 ... write P186 data port
> --
> --  status reg #1 bit assignments
> --   bit     func
> --   0    data available from P186
> --   1    data port to P186 empty
> --
> --  control reg bit assignments
> --   bit     func
> --   0    release reset on P186
> --
> 
> -- strobe line filtering and edge detection
>  (pr_strb_latch , pr_strb_latchsr[] , strb[] , strb_on[] , strb_off[]).clk =
> in_clk;
>  strb[] = (strb[6..0] , prt_strb);
>  pr_strb_latch.s = strb[] == b"11111111";
>  pr_strb_latch.r = strb[] == b"00000000";
>  pr_strb_latchsr[] = (pr_strb_latchsr[0] , pr_strb_latch);
>  strb_on[] = (strb_on[0] , pr_strb_latchsr[] == b"10");
>  strb_off[] = (strb_off[0] , pr_strb_latchsr[] == b"01");
> 
> -- card/brd address latch and card selection
>  pr_addr[].clk = in_clk;
>  pr_addr[] = prtd[];
>  pr_addr[].ena = strb_on[0];
>  card_en = pr_addr[7..3] == sel[];
> 
> -- register address selection truth table
> TABLE
>  pr_addr[2..0]  , card_en =>  prd_en ,  pr_read_hi_P186 , pr_write_ctrl ,
> pr_write_data;
> 
>   X   , 0   => 0  , 0    , 0   , 0 ;
>   0   , 1   => 1  , 0    , 0   , 0 ;
>   1   , 1   => 1  , 0    , 0   , 0 ;
>   2   , 1   => 1  , 0    , 0   , 0 ;
>   3   , 1   => 1  , 1    , 0   , 0 ;
>   4   , 1   => 0  , 0    , 1   , 0 ;
>   5   , 1   => 0  , 0    , 0   , 1 ;
>   6   , 1   => 0  , 0    , 0   , 0 ;
>   7   , 1   => 0  , 0    , 0   , 0 ;
> END TABLE;
> 
> -- data port and control reg logic
>  (pr_to_p186[] , micro_reset).clk = in_clk;
>  pr_to_p186[] = prtd[];
>  pr_to_p186[].ena = strb_off[1] & pr_write_data;
> -- (pr_dsp_run , /up_reset) = prtd[1..0];
> -- (pr_dsp_run , /up_reset).ena = strb_off[1] & pr_write_ctrl;
>  micro_reset = !prtd[0];
>  (micro_reset).ena = strb_off[1] & pr_write_ctrl;
>  /up_reset = !micro_reset;
> 
> -- read logic
>  pr_rd.clk = in_clk;
>  pr_rd.s = strb_on[1] & prd_en;
>  pr_rd.r = strb_off[1];
>  /pr_en = !pr_rd;
>  CASE pr_addr[2..0] & card_en IS
>   WHEN 1 =>
>    pr_readbus[] = (1 , 0 , 1 , 0);
>   WHEN 2 =>
>    pr_readbus[] = p186_to_pr[3..0];
>   WHEN 3 =>
>    pr_readbus[] = p186_to_pr[7..4];
>   WHEN OTHERS =>
>    pr_readbus[] = (0 , 1 , pr_xmt_rdy , pr_rcv_rdy);
>  END CASE;
>  (prt_busy , prt_ack , prt_paper , prt_slct) = (!pr_readbus[3] ,
> pr_readbus[2] , pr_readbus[1] , pr_readbus[0]);
> 
> -- microcontroller bus decode logic
>  p186_read = !/up_cs5 & !/up_rd;
>  p186_write = !/up_cs5 & !/up_wr;
>  p186_write_ctrl = p186_write & !ma[0];
>  p186_read_data = p186_read & ma[0];
>  p186_write_data = p186_write & ma[0];
> 
> -- microcontroller data port and control reg write logic
> --
> --  ctrl reg bit assignments
> --   bit     func
> --   0    rcv_rdy interrupt enable
> --   1    xmt_rdy interrupt enable
> --   2    dspa reset (0 = reset , 1 = run)
> --   3    dspa reset (0 = reset , 1 = run)
> --   4    front panel switch (0 = off , 1 = on)
> --
>  (p186_to_pr[] , rcv_rdy_inten , xmt_rdy_inten , p186_dspa_run ,
> p186_dspb_run , panel_switch).clk = in_clk;
>  p186_to_pr[].ena = p186_write_data;
>  (rcv_rdy_inten , xmt_rdy_inten , p186_dspa_run , p186_dspb_run ,
> panel_switch).ena = p186_write_ctrl;
>  p186_to_pr[] = upad[];
> -- (panel_switch , p186_dsp_run , rcv_rdy_inten , xmt_rdy_inten) =
> upad[5..2];
>  (panel_switch , p186_dspb_run , p186_dspa_run , xmt_rdy_inten ,
> rcv_rdy_inten) = upad[4..0];
>  /dspa_reset = p186_dspa_run;
>  /dspb_reset = p186_dspb_run;
>  sw_on = !panel_switch;
> 
> -- microcontroller data port and status reg read logic
>  p186_rdmux.a[] = pr_to_P186[];
> -- p186_rdmux.b[] = (b"000" , p186_dsp_run , rcv_rdy_inten , xmt_rdy_inten ,
> p186_xmt_rdy , p186_rcv_rdy);
>  p186_rdmux.b[] = (0 , sel[] , p186_xmt_rdy , p186_rcv_rdy);
>  p186_rdmux.sel = p186_read & ma[0];
>  p186_rdmux_tri[].in = p186_rdmux.y[];
>  p186_rdmux_tri[].oe = p186_read;
>  upad[] = p186_rdmux_tri[].out;
> 
> -- data port semaphore logic
>  (pr_rcv_rdy , p186_rcv_rdy).clk = in_clk;
>  pr_xmt_rdy = !p186_rcv_rdy;
>  p186_xmt_rdy = !pr_rcv_rdy;
> 
>  pr_rcv_rdy.s = p186_write_data;
>  pr_rcv_rdy.r = pr_read_hi_P186 & strb_off[1];
>  p186_rcv_rdy.s = pr_write_data & strb_off[1];
>  p186_rcv_rdy.r = p186_read_data;
> 
>  pr_xmt_rdy = !p186_rcv_rdy;
>  p186_xmt_rdy = !pr_rcv_rdy;
> 
>  up_int4 = (p186_rcv_rdy & rcv_rdy_inten) # (p186_xmt_rdy & xmt_rdy_inten);
> 
> -- misc logic
>  XO = XI[] == 0;
>  tp5 = p186_rcv_rdy;
>  tp6 = p186_xmt_rdy;
>  tp7 = up_int4 ;
>  tp8 = strb_on[0] # strb_on[1];
>  tp9 =  pr_strb_latch;
> -- in_clk.(j,k,prn,clrn) = VCC;
> -- in_clk.clk = in_clk_x2;
> END;

--
   ___                                           ___
  /  /\                                         /  /\
 /  /__\                                       /  /\/\
/__/   / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/
\  \  /  Victoria, Australia, Down-Under      \  \/\/
 \__\/                                         \__\/

Article: 32960
Subject: Re: Shift and Add Multiplier With Signed Numbers
From: Ray Andraka <ray@andraka.com>
Date: Fri, 13 Jul 2001 05:37:04 GMT
Links: << >>  << T >>  << A >>
Booth recoding won't help much in this case.  A scaling accumulator
multiplier is a single accumulator with the feedback shifted.  It is a
serial by parallel multiplier, that uses a conventional adder.   Booth
recoding seeks to reduce the number of partial products by recoding
strings of '1' bits into an equivalent 1, -1 and zeros.  The result is
that you can reduce the number of partial products to be combined in an
adder tree, which in turn reduces the size of the tree.  Since the
scaling accumulator multiplier is shifting once and adding for N cycles,
you essentially are doing all the partial products regardless of whether
or not they are zero.  You could conceivably use Booth recoding in this
case to reduce the number of cycles, but in a practical sense, the added
complexity to the circuit would outweigh the benefit (one could use two
scaling accumulator multipliers, or go to a 2 bits/clock version to get
on average a better speedup for less area and complexity).  All he has
to do is subtract the partial product corresponding to the MSB of the
serial input and sign extend the parallel input to handle signed
muliplicands.

Rob Finch wrote:

> Try using Booth recoding.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 32961
Subject: Re: Problems: Xilinx 3.1i Service Pack 8
From: Stephan Neuhold <stephan.neuhold@xilinx.com>
Date: Fri, 13 Jul 2001 07:27:34 +0100
Links: << >>  << T >>  << A >>
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Hi Peter,

You have to make sure that you install FPGA Express update along with
the SP. Don't install it seperately.

Cheers,
Stephan

Peter Lang wrote:

> Hi,
> I just updated my Xilinx Foundation 3.1i with the
> very new 3.3i Service Pack 8. After that
> I am not able to open any Design in
> the Design Manager. I get always the message
> "Cannot initialize Automation -Synopsys initialization failed"
>
> thanks for any help
> peter

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Article: 32962
Subject: Help needed: why am I getting device programming errors on Webpack.
From: www@plexus-technologies.com (Dean)
Date: Fri, 13 Jul 2001 14:36:30 GMT
Links: << >>  << T >>  << A >>
I'm trying to program my first Xilinx device - a 95108. I've created the
jed file, no errors. What I've done is designed a small PCB with a 6-way
header for the JTAG interface (no pull up resistors - do I really need them?
Local FAE says no), and two other headers to pull out all the I/O pins so I
can interface it to the processor board I've added this little board to
(double-sided tape is a wonderful thing).

I've made sure the connections are right, and am trying to program the
device. I'm using WebPACK v3.3.

I can apparently erase the device (all entries from the log file):

(null):Release 3.3WP8.x - JTAG Boundary-Scan Download D Copyright:(null)
JTAG Programmer Started 2001/07/13 23:35:05
'accelerometercounter(Device1)': Checking boundary-scan chain
integrity...done.
'accelerometercounter(Device1)': Putting device in ISP mode...done.
'accelerometercounter(Device1)': Erasing device....done.
'accelerometercounter(Device1)': Erasure completed successfully.


I can also apparently read the ID number from it too:

'accelerometercounter(Device1)': Manufacturer's ID = Xilinx XC95108 Rev:
0010

But when I try to program it, I get this:

'accelerometercounter(Device1)': Checking boundary-scan chain
integrity...done.
'accelerometercounter(Device1)': Putting device in ISP mode...done.
'accelerometercounter(Device1)': Processing JEDEC file...done.
'accelerometercounter(Device1)': Programming device....ERROR:JTag - The
program operation failed for instance 'accelerometercounter(Device1)' when
attempting to address location '0x12298'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x1229b'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x914d'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x1b2db'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x1b2d3'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x1b0d9'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x1a2d9'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x1b2d9'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x1b0d1'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x1b2db'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x1b0db'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x1b2db'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x1a0db'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x12090'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x12091'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x12090'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x12093'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x12092'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x12092'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x12093'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x12090'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x12091'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x12090'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x12098'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x12099'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x1209a'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x14827'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x120d9'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x120d8'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x120d9'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x120da'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - The program operation failed for instance
'accelerometercounter(Device1)' when attempting to address location
'0x120d2'.
	The part appears to be in read or write protect mode.
	You will have erase the part the disable this mode.
	If the part is not in this mode then a problem may exist in the
hardware configuration.
	Check that the cable, scan chain, and power connections are intact,
	that the specified scan chain configuration matches the actual
hardware, and
	that the power supply is adequate and delivering the correct
voltage.
ERROR:JTag - More program failures occurred.  (Display message limit per
burst: '32').
'accelerometercounter(Device1)': Programming terminated due to error.




Wow. Quite a long log file error from one button press. I assume that if I
go File -> New and then File -> InitialiseChain and when that pretty picture
of a PLD comes up with "95108" underneath it, the "95108" is actually being
read out of the device live, right? So the chain integrity, signal wiring,
power supply etc must be OK, as is the device itself, for if it was dead or
not talking, I'd never read that 95108 back, nor would I be able to execute
operations such as "Get ID". 

Now oddly enough if I do a "Get ID" on it, I now get the following error
messages:

ERROR:JTag - No instance of the name 'accelerometercounter(Device1)' was
found in the instance database.
	Make certain that the complete boundary-scan chain was specified and
that you are using the correct JEDEC, .BIT and BSDL files.
ERROR:JTag - 'accelerometercounter(Device1)':  Manufacturer's ID read
failed.


I'm not quite sure what this means. Apart from clicking on the image of the
device in the chain and loading the jedec file into the dialogue, is there
any other setup I'm missing out on? In other words, this action is
sufficient to tell the system "this file goes into this device here"... .or
am I assuming wrong?

The local FAE lent me his cable and 9536 demo board to play with and
everything seems fine on his Johnson Counter test file and board.

Do I need to specify something in the project manager to let it know that my
single 95108 is "device 1", or does the error message

ERROR:JTag - No instance of the name 'accelerometercounter(Device1)' was
found in the instance database.

mean something else?

Article: 32963
Subject: Foundation2.1i
From: T.Dattuprasad <dattuprasad@hotmail.com>
Date: Fri, 13 Jul 2001 08:44:20 -0700
Links: << >>  << T >>  << A >>
Dear friends,
I am beginner in using the FPGA tools. I have designed a small FIFO based design. When I Synthesise the Design using the Foundation Express 2.1i, I am getting the following error : "Global Set/Reset (GSR)net could be used in the design because there is not a unique net that sets or resets all the sequential cells. (FPGA-GSRMP-5)"

I ahve used a common Rst pin for all the sequential elements also I am getting the same error. When Synthesize the same design in Virtex devices the oproblem is not coming where in if i synthesize it in Spartan devices  the problem is coming.

Pl. let me know at the given ID if anyone knows the answers.

Thank u.

Article: 32964
Subject: Re: Xilinx BRAM failures
From: "Kevin Neilson" <kevin_neilson@yahoo.com>
Date: Fri, 13 Jul 2001 15:50:26 GMT
Links: << >>  << T >>  << A >>
Remember that Xilinx has made some drastic changes to TBCKO in the speed
files in some of the recent service packs.  For example, in one recent
service pack they added about a whole nanosecond to TBCKO for the VirtexE-8,
so even if you were meeting static timing analysis by quite a margin with
the old speed file, you could still be failing on real parts.  This means
that firstly, you need the newest speed files, and secondly, they are never
to be trusted, because this particular and drastic change wasn't implemented
until the eighth service pack.  I don't even know what the most recent is.

Also, FIFOs are tricky; make sure domains are crossed properly and that the
address for the read port is generated inside the read clock domain.

-Kevin

"Achlys" <Achlys4now@yahoo.com> wrote in message
news:e5464095.0107121101.1acc5dd2@posting.google.com...
> Is anyone experiencing block ram failures in Xilinx Virtex-E devices?
> We've seen a condition where different bit files will cause hard
> failures on a small percentage of the parts. The block rams are
> configured as 32-bit wide FIFO's; certain nibbles of the fetched data
> seem to be from the previous clock cycle. Locking the block RAM
> locations in the design doesn't always help; some devices still fail,
> some pass. Re-synthesising the design helps sometimes but not always.
> Working boards will fail with new bit files. We've seen the failure on
> multiple parts and on multiple designs.
>
> Is anyone experiencing anything similar or other unexplained failures
> with Virtex-E parts?
>
> Thanks
>



Article: 32965
Subject: Re: Problems: Xilinx 3.1i Service Pack 8
From: qlyus@yahoo.com (qlyus)
Date: 13 Jul 2001 09:33:37 -0700
Links: << >>  << T >>  << A >>
"Peter Lang" <Peter.Lang@rmvmachinevision.de> wrote in message news:<9ik53h$oaj$01$1@news.t-online.com>...
> Hi,
> I just updated my Xilinx Foundation 3.1i with the
> very new 3.3i Service Pack 8. After that
> I am not able to open any Design in
> the Design Manager. I get always the message
> "Cannot initialize Automation -Synopsys initialization failed"
> 
> thanks for any help
> peter

I found the similar problem if SP8 is directly installed over the
original Foundation 3.1i.  If you have the copy of SP6 (or 7?),
install it over 3.1i first and then install SP8.

Article: 32966
(removed)


Article: 32967
Subject: Re: Xilinx BRAM failures
From: Achlys4now@yahoo.com (Achlys)
Date: 13 Jul 2001 10:04:25 -0700
Links: << >>  << T >>  << A >>
Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3B4DFEB5.3EB92611@flukenetworks.com>...
> Achlys wrote:
> > 
> > Is anyone experiencing block ram failures in Xilinx Virtex-E devices?
> > We've seen a condition where different bit files will cause hard
> > failures on a small percentage of the parts. 
>  . . .
> > Re-synthesising the design helps sometimes but not always.
> > Working boards will fail with new bit files. We've seen the failure on
> > multiple parts and on multiple designs.
> 
> 
> 
> Sounds like a race condition somewhere.
> Did static timing run ok?
> 
>   
> 
Hi Mike,

Static timing is ok - and we have updated timing files (Service pack
8). As you probably know Xilinx had incorrect timing files. When we
first started this project we had the intermittent type problems
caused by race conditions. This was from DesignManager reporting OK
timings which were actually 1-2ns over.

These are repeatable, hard failures that are temperature insensitive.
Replacing the IC usually fixes it. The design(s) is now fairly mature
and is being functionally enhanced. Replacing the suspect block ram
with a different resource internally can fix the problem. Same design,
new placement with both routes meeting the timing constraints. Yikes!
Not good for field upgrades.

Sound familiar to anyone?

Thanks


> 
>   --Mike Treseler

Article: 32968
(removed)


Article: 32969
(removed)


Article: 32970
(removed)


Article: 32971
Subject: Re: Xilinx BRAM failures
From: "Jamie Sanderson" <jamie@nortelnetworks.com>
Date: Fri, 13 Jul 2001 13:34:41 -0400
Links: << >>  << T >>  << A >>
"Achlys" <Achlys4now@yahoo.com> wrote in message
news:e5464095.0107130904.5e59294a@posting.google.com...
> Hi Mike,
>
> Static timing is ok - and we have updated timing files (Service pack
> 8). As you probably know Xilinx had incorrect timing files. When we
> first started this project we had the intermittent type problems
> caused by race conditions. This was from DesignManager reporting OK
> timings which were actually 1-2ns over.
>
> These are repeatable, hard failures that are temperature insensitive.
> Replacing the IC usually fixes it. The design(s) is now fairly mature
> and is being functionally enhanced. Replacing the suspect block ram
> with a different resource internally can fix the problem. Same design,
> new placement with both routes meeting the timing constraints. Yikes!
> Not good for field upgrades.
>
> Sound familiar to anyone?

I had this happen a few years ago with XCV4010XL parts. This may seem like
an obvious suggestion, but have you tried over-constraining by a few
percent? A nanosecond so far as your board is concerned may not be the same
as the timing analyzer is concerned. Among other things, oscillators have
some tolerance, your constraints should at least account for that. For
example, suppose you were using 33 MHz PCI. Try a period constraint of 29
ns, instead of 30 ns. That way, marginal parts should not fail in the field.

Cheers,
Jamie



Article: 32972
Subject: Re: Help needed: why am I getting device programming errors on Webpack.
From: mikeandmax@aol.com (Mikeandmax)
Date: 13 Jul 2001 17:36:25 GMT
Links: << >>  << T >>  << A >>
Dean (perplexed at plexus) ponders
>
>I'm trying to program my first Xilinx device - a 95108. I've created the
>jed file, no errors. What I've done is designed a small PCB with a 6-way
>header for the JTAG interface (no pull up resistors - do I really need them?
>Local FAE says no), and two other headers to pull out all the I/O pins so I
>can interface it to the processor board I've added this little board to
>(double-sided tape is a wonderful thing).
>
>I've made sure the connections are right, and am trying to program the
>device. I'm using WebPACK v3.3.
>
>I can apparently erase the device (all entries from the log file):

Sounds like you are connecting a couple of 'deadbugs' together - and also
sounds like you've got it pretty close to 'right'.  Did you make sure to
adequately decouple and hook up power the the device - when doing a simple
read, not much current consumed, not much noise generated, but writing is a
whole other ballgame, onchip programming supply ramps up and sucks plenty of
current - poor regulation can cause the types of intermittent errors you are
having.  I figure you may have tried more than one device also?
 >
>Do I need to specify something in the project manager to let it know that my
>single 95108 is "device 1", or does the error message
>
>ERROR:JTag - No instance of the name 'accelerometercounter(Device1)' was
>found in the instance database.
>
On many programmable devices, partial and/or improper  programming can get the
device into a failed state, which hopefully full erase can resolve, but if the
tool needs to first read the device, then we get into one of those catch-22 -
chicken or egg- loops.
good luck - 
Mike (and max, the wonder dog!)


Article: 32973
Subject: Re: Design entry
From: vhdlcohen@aol.com (VhdlCohen)
Date: 13 Jul 2001 18:56:37 GMT
Links: << >>  << T >>  << A >>
>As you've guessed from recent posts, I'm very new to using FPGAs (couple of
>months). I've been spending my time implementing schematic design entries
>(using Foundation ISE). This brings me to my question? Should I rather be
>attempting to implement my designs in VHDL instead? My experience with VHDL
>is the Designer's Guide to VHDL!
>
>Any suggestions?
>
Definitely use an HDL instead of schematic  entry.  You gain faster design
entry, better documentation (provided you type it in), easier verification (one
language or interface to a common lnaguage 9e.g., Specman)), and reuse. 
--------------------------------------------------------------------------
-----------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830
http://www.vhdlcohen.com/                 vhdlcohen@aol.com  
Author of following textbooks: 
* Component Design by Example ... a Step-by-Step Process Using 
  VHDL with UART as Vehicle",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
--------------------------------------------------------------------------
------------------------------------------

Article: 32974
Subject: Re: How do I distribute cores?
From: "Steve Casselman" <sc@vcc.com>
Date: Fri, 13 Jul 2001 12:17:19 -0700
Links: << >>  << T >>  << A >>
> The same problem exists for distributing source code for software.
> Non-disclosure agreements, licensing and sueing, are the only things I can
> think ok.

You have the same problem with any program. You can disassemble anything and
reverse engineer anything. You might consider a Open Source type of thing
where you just sell the code and trust no one will distribute it (with
licensing agreements). I think most of the people who buy IP really need to
have source to simulate it right and what not.  Just charge for it.

Steve





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