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Messages from 33225

Article: 33225
Subject: Re: SystemC
From: Jonathan Bromley <Jonathan.Bromley@doulos.com>
Date: Thu, 19 Jul 2001 17:25:46 +0100
Links: << >>  << T >>  << A >>
In article <9j6ukm$73u$1@nh.pace.co.uk>, Brendan Lynskey
<brendan.lynskey@pace.co.uk> writes
>I thought that SystemC was intended only as a descriptive language - not as
>a language for synthesis.

I suspect that Synopsys (CoCentric SystemC Compiler), Frontier Design
(A|RT Designer) and others would disagree.  OTOH maybe one should ask
the customers :-)
-- 
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223                     Email: jonathan.bromley@doulos.com
Fax: +44 1425 471573                             Web: http://www.doulos.com

                   **********************************
                   **  Developing design know-how  **
                   **********************************

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are not the views of Doulos Ltd., unless specifically stated.




Article: 33226
(removed)


Article: 33227
Subject: Re: 30 m cable reception with APEX LVDS I/O ?????
From: "Jamie Sanderson" <jamie@nortelnetworks.com>
Date: Thu, 19 Jul 2001 13:28:43 -0400
Links: << >>  << T >>  << A >>
"Stéphane" <sjulhes@free.fr> wrote in message
news:Irw57.158$Q34.447547@nnrp3.proxad.net...
> My question is :
> Are the APEX's LVDS I/O directly compatible with such signals ?
> The main problem is the common mode which seems to be to small.

I haven't used the Apex LVDS yet, but I will offer some advice on LVDS in
general. Look at the differential signal when evaluating the quality of the
overall signal. The common-mode signal will be nearly invisible to the
receiver. This is the advantage of using differential signals.

As someone else suggested, you may also want to check the cable. In the
past, I've used a cable from Gore called "twin-ax" for carrying LVDS
signals. The cable is like coax, but with two conductors carried within a
single elliptical cross-section shield, instead of a single conductor with a
circular cross-section shield. Differential signals are really only useful
if they are treated as such. If the individual signals see very different
skew and noise, the benefits of using differential signalling go away.

Cheers,
Jamie



Article: 33228
Subject: Re: assigning signals with Altera Max+PlusII vhdl
From: timjeno@visto.com (Tim O'Connell)
Date: 19 Jul 2001 10:50:43 -0700
Links: << >>  << T >>  << A >>
Hmmm, whatdoyaknow.... constant seems to work just fine.  Thanks.

The assignmet I used does work in the silicon using MAX+PLUS II,
Quartus, or Leonardo and targetting Apex, Acex, MAX, or FLEX devices. 
That's the limit of my experience so that's all I can say.

  Thanks again,

       Tim


cyber_spook <pjc@cyberspook.freeserve.co.uk> wrote in message news:<3B4B70A6.3D4F3FE1@cyberspook.freeserve.co.uk>...
> Tim O'Connell wrote:
> 
> > I would like to know also.  I've never been able to get a constant
> > signal that way.  If I were to code it I would use the lines
> 
> Use the CONSTANT keyword.
> 
> >
> >
> > SA <= "11110000";
> > SB <= "00001111";
> >
> > instead of the initialization in the signal declaration.  This will
> > work.  I don't know why the initialization doesn't work though.
> 
> Correct me if I'm wrong (and they will). When this is in slicon the initialisation dose not happen -
> this is for simulation. You should always code your logic with constants like this.
> 
> >

Article: 33229
Subject: Re: 30 m cable reception with APEX LVDS I/O ?????
From: John_H <johnhandwork@mail.com>
Date: Thu, 19 Jul 2001 18:37:45 GMT
Links: << >>  << T >>  << A >>
"Stéphane" wrote:

> The fact is that signal at my side of the cable are very perturbed, I don't
> know exactly what they look like but I was told there is a lot of, skew,
> jitter, and voltages are disturbed. The clock is also transmitted on the
> cable in LVDS protocol and I have to get the FPGA's clock out of it.

Skew for a 40MHz signal shouldn't be a problem since skew should not amount to a
significant part of the 25nS cycle time.  What *is* a problem is if the LVDS
pairs have skew within the two wires!  LVDS is a differential signalling
standard and MUST use differential pairs (two wires twisted together over their
length before being packaged with other pairs and jacketed).  Twinax probably
isn't required for 40MHz but is helpful in getting cleaner signals.

The twisted pairs should have 100 ohms differential impedance - mismatches at
the transmitter and/or receiver can cause problems.

For 30m of Cat5 cable, the tables in the National Semiconductor "LVDS Owner's
Manual, 2nd Edition" it appears you'll have 20% jitter at 100MHz.  40MHz should
be cleaner.

As far as I'm aware, there is no "protocol" to the LVDS signalling standard.
The clock may be embedded in an 8b/10b format, for instance, but this is design
dependent.  If the clock is coming over as an LVDS clock, this should be able to
run natively in the Altera devices.


Article: 33230
(removed)


Article: 33231
Subject: xilinx web pack problem
From: Gonzalo Arana <gonzaloa@sinectis.com.ar>
Date: Thu, 19 Jul 2001 22:36:42 -0300
Links: << >>  << T >>  << A >>
Hi,

It's me again.
I am using Xilinx WebPACK, and I get this error when trying to
'implement' my design:

Checking expanded design ...
ERROR:NgdBuild:455 - logical net
   'buildclock9600_cnt_counterno0_count_net_sig_inv_updown' has multiple
drivers

My questions are:

1) Does it mean that I have something like this?
   z <= x;
   z <= y;

2) How may I know wich are theese multiple drivers?

Thank you verry much in advance,

Gonzalo

Article: 33232
(removed)


Article: 33233
Subject: foundation series 2.1i
From: ramshankar <rramshankar@excite.com>
Date: Thu, 19 Jul 2001 20:52:49 -0700
Links: << >>  << T >>  << A >>
I am working on a board with a virtex xcv100. I am hoping to locate a student edition of foundation series that is capable of compiling for a virtex xcv100. If anyone has used the student version for a virtex xcv100 please reply.

Article: 33234
Subject: Re: How to see ram contents in maxplus2 simulation?
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Fri, 20 Jul 2001 14:40:48 +1000
Links: << >>  << T >>  << A >>
Wolfgang Loewer wrote:
> 
> In the MAX+plus II simulator you can display a waveform for every single
> word of all memories used. So in your case you would just select the first
> memory word that you expect the statemachine to write to and watch it during
> simulation...

Thanks WL, that worked too:)


BTW, i can't find a library function for a simple RS (reset-set)
flip-flop (to use as a sticky flag). Do these need to be made
manually from a D flip-flop or AND gates?

--Russell


Article: 33235
Subject: Re: How to see ram contents in maxplus2 simulation?
From: bob elkind <eteam@aracnet.com>
Date: Thu, 19 Jul 2001 22:06:50 -0700
Links: << >>  << T >>  << A >>
In AHDL, cast the SR (or RS) flop (in VARIABLES section) as SRFF or SRFFE.

-- Bob Elkind

Russell Shaw wrote:

> ...
> BTW, i can't find a library function for a simple RS (reset-set)
> flip-flop (to use as a sticky flag). Do these need to be made
> manually from a D flip-flop or AND gates?
>
> --Russell



Article: 33236
Subject: Re: foundation series 2.1i
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 19 Jul 2001 22:26:51 -0700
Links: << >>  << T >>  << A >>
ramshankar <rramshankar@excite.com> writes:
> I am working on a board with a virtex xcv100. I am hoping to locate a
> student edition of foundation series that is capable of compiling for
> a virtex xcv100. If anyone has used the student version for a virtex
> xcv100 please reply.

If you don't need exact timing, use WebPACK, and target the Spartan II
XC2S100.  It uses exactly the same configuration bitstream as the XCV100.

Article: 33237
Subject: Re: SystemC
From: kw@dtek.chalmers.se (Kristian Wiklund)
Date: 20 Jul 2001 05:43:34 GMT
Links: << >>  << T >>  << A >>
"Brendan Lynskey" <brendan.lynskey@pace.co.uk> writes:

>I thought that SystemC was intended only as a descriptive language - not as
>a language for synthesis.

I recently attended a presentation where it was claimed that it
is possible to synthesise the HW parts of the system from SystemC.

Unfortunately, the presentation was quite boring, causing me to
doze off in the middle, which means that I have no idea how mature
the support for synthesis is.

My reaction to SystemC was slightly negative, probably because
I find C++ ugly, but also because the language/library/whatever you like
to call it, seems to be "unfinished". I got the impression that the
language/library/whatever you like to call it was "unfinished",
in a way similar to when the Java hype started. (Libraries that
changed, functions that were deprecated between releases, and so on.)

I'm very interested in hearing about some real-life experience with
SystemC. 

I know that there are people that are very enthusiastic
about it, so it could be that I'm to stubborn to realize that it
in fact is a good thing. 

/w.

-- 
Rädda viltet, förbjud O-ringen!

Article: 33238
Subject: Re: FPGAs in Safety Involved Applications
From: "Victor Schutte" <victors@mweb.co.za>
Date: Fri, 20 Jul 2001 08:48:25 +0200
Links: << >>  << T >>  << A >>
I started using Altera 7032S and 7064S in fire safety systems (for tanks and
related weapons) about 3 years ago  with huge success. The electronics gets
exposed to high temperatures, enormous shock and vibration  and the box is
situated next to a cable sometime carriying 700Ampere through it.

For hazardous environments I would not use a FPGA for fear that the device
might not be configured correctly.

The one thing you can do is to use a couple of the lines as  test outputs.
E.g. 8 wires in a  1 0 1 0 1 0 1 0 output after config. Use something like a
74LS688 (yeah I know, ancient) to compare the pattern after config or during
operation. If you get something else then reconfig. ...but you can still get
the right value even after the device goes corrupt.

2nd option is to implement a watch dog timer (MAX690/1/2/3). The FPGA must
contain a counter plus output. When the device is configured correctly the
FPGA will strobe the the WDT. When the stobe output stops the WDT will reset
the FPGA (reconfig).

3rd option. Use many of the same circuits and then check if they output the
same values. A client of mine uses 4 CPLDs calculating the same outputs. The
final 4 outputs are fed into a 4 input hardcoded AND circuit (relays or
qualified solid state). If the any one of the outputs differ the output is
not implemented.

Remember to check for how long your system can tolerate a faulty FPGA. In
medical equipment no errors at all is preferred. When switching a relay
output the time is less than the reaction time of the relay.  In you
airborne app. how much "faulty" time must pass before the aircraft start
behaving incorrectly?

I can write a whole book about what to look for. You must just ask the right
questions and then you might even find a place for a buggy PIC
microcontroller.

Victor

"Jon Harrison" <jon.harrison@gecm.com> wrote in message
news:3b5575d0@pull.gecm.com...
> Hi,
>
> We are starting out on a new design for an airborne application, which
will
> employ a large numer of Virtex-E/II FPGAs. The issue of safety
> classification has raised it's head, and whether the volatility of SRAM
> FPGAs constitutes an intrinsic hazard. Conventionaly with SRAM devices
which
> hold program information in microprocessor based systems this is addressed
> by the use of continuous memory testing and checksumming.
>
> Has anyone else crossed this thorny issue yet ? Guidance as to any
> procedures / processes followed would be useful.
>
> We would propose to address this issue by using device readback to allow
> checksumming of the configuration data - has this been found to be
> acceptable eleswhere ?
>
> Cheers,
>
> Jon
>
>
>
>



Article: 33239
Subject: Re: SystemC
From: Robert Siegmund <rsie@infotech.tu-chemnitz.de>
Date: Fri, 20 Jul 2001 08:51:08 +0200
Links: << >>  << T >>  << A >>
Hi,

currently, synthesis support for SystemC such as Synopsys CoCentric
is available. However, the SystemC subset supported is basically
equivalent to that of VHDL accepted by Synopsys Behavioural Compiler .

So I don't see any advantage to code in SystemC for synthesis, esp. if
there is
no standardized SystemC synthesis subset. You can stick to VHDL for
synthesizable
models and wait for model converter tools to SystemC which will surely
appear
as soon as the SystemC language got standardized.

-- robert

Vivian schrieb:

> Hi,
> Does anyone have experience with systemC synthesis tools for FPGAs.
>
> What works best ?
>
> Viv

--
------------------------------------------------------------------------------
Dipl.-Ing. Robert Siegmund                 email: rsie@infotech.tu-chemnitz.de
Chemnitz University of Technology
Dpt. of Systems and Circuit Design        www: http://www.tu-chemnitz.de/~rsie
Chemnitz,Germany
------------------------------------------------------------------------------




Article: 33240
Subject: FND Timing Simulator - Watch *
From: Michael Boehnel <boehnel@iti.tu-graz.ac.at>
Date: Fri, 20 Jul 2001 11:50:14 +0200
Links: << >>  << T >>  << A >>
Is there a posibility to watch all signals (watch *) in the Foundation
Timing Simulator? I haven't found such a command yet?

My intended workaround is to extract the signals from the design files
and place a watch for every single signal.

But in what design files can I find the signals? Do I have to analyze
the netlist? That would be very laborious for me.

Michael



Article: 33241
Subject: Re: xilinx web pack problem
From: Edwin Naroska <edwin@ds.e-technik.uni-dortmund.de>
Date: Fri, 20 Jul 2001 11:53:48 +0200
Links: << >>  << T >>  << A >>
Hi,

I assume you use VHDL...

Gonzalo Arana wrote:

> Hi,
>
> It's me again.
> I am using Xilinx WebPACK, and I get this error when trying to
> 'implement' my design:
>
> Checking expanded design ...
> ERROR:NgdBuild:455 - logical net
>    'buildclock9600_cnt_counterno0_count_net_sig_inv_updown' has multiple
> drivers
>
> My questions are:
>
> 1) Does it mean that I have something like this?
>    z <= x;
>    z <= y;

The answer is yes, if these are "concurrent signal assignments"
(= signal assignments which are not located within a process or
subprogram).

Roughly spoken: each process (or concurrent signal assignment) which
includes at least one assignment statement that targets a specific signal
forms a driver for this signal. Instantiated components may
also form a source if the corresponding signal it is connected to a
component port of mode "out", "inout" or "buffer".

>
>
> 2) How may I know wich are theese multiple drivers?

If your tool does not give you this information then you have to check
out the source code by yourself. Try to find all assignments that target
the corresponding signal and also search for all instantiated component
ports that build a source for this signal. See

http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#drivers

for further information.

--
Edwin



Article: 33242
Subject: Re: Working Design - Anyone
From: Keith Wootten <Keith@wootten.demon.co.uk>
Date: Fri, 20 Jul 2001 11:41:10 +0100
Links: << >>  << T >>  << A >>
In article <3B549BE4.5AD1A371@xess.com>, Dave Vanden Bout
<devb@xess.com> writes

>You might try looking at a few chapters of our online text at
>http://www.xess.com/pragmatic-2_1.html. 

Excellent work, Dave, I just wish you'd published this three years ago
:-)  


Cheers
-- 
Keith Wootten

Article: 33243
Subject: Async RS flip-flop (was How to see ram contents in maxplus2 simulation?)
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Fri, 20 Jul 2001 20:47:25 +1000
Links: << >>  << T >>  << A >>
Hi,

I found the SRFF library component. Unfortunately, its useless
because it needs a clock.

I have a state machine controlled case statement that sets a flag:
srff.s=vcc. However, srff.q only changes at the next clock edge
which is also when the transition into the next state case-statement
happens. But this is too late for another flip-flop which clocks in
that flag to do something else.

A clockless RS flip-flop wouldn't have that problem. Are asynchronous
things like that bad for some reason?

I could fix it by inserting extra states, but that just makes things
slower. Maybe things like flags should work on a x2 or x4 clock?

bob elkind wrote:
> 
> In AHDL, cast the SR (or RS) flop (in VARIABLES section) as SRFF or SRFFE.
> 
> -- Bob Elkind
> 
> Russell Shaw wrote:
> 
> > ...
> > BTW, i can't find a library function for a simple RS (reset-set)
> > flip-flop (to use as a sticky flag). Do these need to be made
> > manually from a D flip-flop or AND gates?
> >
> > --Russell

--
   ___                                           ___
  /  /\                                         /  /\
 /  /__\                                       /  /\/\
/__/   / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/
\  \  /  Victoria, Australia, Down-Under      \  \/\/
 \__\/                                         \__\/

Article: 33244
Subject: Re: xilinx web pack problem
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Fri, 20 Jul 2001 11:58:21 +0100
Links: << >>  << T >>  << A >>
On Thu, 19 Jul 2001 22:36:42 -0300, Gonzalo Arana
<gonzaloa@sinectis.com.ar> wrote:

>Hi,
>
>It's me again.
>I am using Xilinx WebPACK, and I get this error when trying to
>'implement' my design:
>
>Checking expanded design ...
>ERROR:NgdBuild:455 - logical net
>   'buildclock9600_cnt_counterno0_count_net_sig_inv_updown' has multiple
>drivers
>
>My questions are:
>
>1) Does it mean that I have something like this?
>   z <= x;
>   z <= y;
Probably...

>2) How may I know wich are theese multiple drivers?

In ModelSim (Xilinx offer a freebie version of this tool) there is a
useful command to list all drivers on any particular signal. 

- Brian


Article: 33245
Subject: Spartan XL Readback Problem
From: "pforyt" <foryt@sim.com.pl>
Date: Fri, 20 Jul 2001 12:07:58 +0100
Links: << >>  << T >>  << A >>
Hello.
The problem I am facing is that when I try to readback Spartan XL device
using Multilinx cable, Hardware Debugger informs:
    Total of 1299 bits mismatched
but device is working properly. Number of mismatched bits is not constant .
I have no such problem when I'm performing readback on Spartan device.

Thanks in advance.
Piotr Foryt




Article: 33246
Subject: Modulator Sizing Questions
From: dottavio@ised.it (Antonio)
Date: 20 Jul 2001 05:36:38 -0700
Links: << >>  << T >>  << A >>
Good Morning,
I'm Producing a QPSK modulator using an NCO, I use the classical
schema including 2 branches, each with a Polyphase
SquareRootRaisedCosine Filter whose output go to a multiplier having
on the other input the output of the NCO , the two branches then come
to a adder, my question is about the number of bits in the different
part of the circuit, for example :

1) How much bits I've to use for the coefficients of the polyphase
filter ??
2) the data arriving to the polyphase are 1 and -1 so the multiply is
reduced to invert the coefficient or not, how much bits I've to
consider at the output providing the coefficient are expressed in
2'complement and are -0.0103914189205138260
-0.0090424537413504452
-0.0015462472598948768
0.0104572775382219900
0.0225120416117039310
0.0285826337727227570
0.0233188590342006150
0.0046304157926415250
-0.0244042584244363110
-0.0551805195177435540
-0.0751980048558142520
-0.0714382299222202640
-0.0345746562804935130
0.0373165930609706130
0.1368592502236164500
0.2481225405617600900
0.3500278381428516000
0.4215598203650190400
0.4472906424227021100
0.4215598203650190400
0.3500278381428516000
0.2481225405617600900
0.1368592502236164500
0.0373165930609706130
-0.0345746562804935130
-0.0714382299222202640
-0.0751980048558142520
-0.0551805195177435540
-0.0244042584244363110
0.0046304157926415250
0.0233188590342006150
0.0285826337727227570
0.0225120416117039310
0.0104572775382219900
-0.0015462472598948768
-0.0090424537413504452
-0.0103914189205138260
by the way how you suggest me to implement these coefficients ??

3) If for example one input of the multiplier is 10 bits, also the
other must be ten bits ?? and how much for the output ???

4) By the way , it is important that the inputs of the multiplier have
the same rate ??

5) if for example the input of the following adder are both 10 bits,
how much bits I've to provide for the output.


I know many of these question could be stupid , but, how I can say,
I've not the answer so if you have some answer also only at some of
them I'll be really happy if you tell it to me or also if you redirect
me to some resource speaking strictly about these thinghs ...

Antonio D'Ottavio

Article: 33247
Subject: Modelsim and bidir ports?
From: khiltrop@gesytec.de
Date: 20 Jul 2001 12:59:21 GMT
Links: << >>  << T >>  << A >>
Hi

My Modelsim XE 5.3d claims
               Incompatible modes for port abc
with port abc being an 'inout' port.
Is there a special trick I do not know about? How can I simulate 
bidirectional ports?
I am using XILINX ISE 3.1i

Klaus Hiltrop

Article: 33248
Subject: Senior IC Engineer
From: "inGenius People" <Ellen@ingeniuspeople.com>
Date: Fri, 20 Jul 2001 13:32:01 GMT
Links: << >>  << T >>  << A >>
Our client has an outstanding opportunity for a Senior Integrated Circuit
Engineer.

The ideal candidate will have:


*5+ years of digital ASIC design experience

*Experience with verilog coding for modelling and synthesis

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information, contact:  Ellen@ingeniuspeople.com



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      K1Y 1P4

      Phone: (613) 729-6400 x 241

      Fax: (613) 729-6770

      www.ingeniuspeople.com


























































Article: 33249
Subject: Re: xilinx web pack problem
From: dpwright@iee.org (DAVE WRIGHT)
Date: 20 Jul 2001 07:20:16 -0700
Links: << >>  << T >>  << A >>
Brian Drummond <brian@shapes.demon.co.uk> wrote in message news:<ok3gltgatf6qcii7pcnc1ce9nctk14fhda@4ax.com>...
> On Thu, 19 Jul 2001 22:36:42 -0300, Gonzalo Arana
> <gonzaloa@sinectis.com.ar> wrote:
> 
> >Hi,
> >
> >It's me again.
> >I am using Xilinx WebPACK, and I get this error when trying to
> >'implement' my design:
> >
> >Checking expanded design ...
> >ERROR:NgdBuild:455 - logical net
> >   'buildclock9600_cnt_counterno0_count_net_sig_inv_updown' has multiple
> >drivers
> >
> >My questions are:
> >
> >1) Does it mean that I have something like this?
> >   z <= x;
> >   z <= y;
> Probably...
> 
> >2) How may I know wich are theese multiple drivers?
> 
> In ModelSim (Xilinx offer a freebie version of this tool) there is a
> useful command to list all drivers on any particular signal. 
> 
> - Brian

This is why it is best to use std_ulogic and std_ulogic_vector where possible.
That way, your simulations will catch any multiply driven signals.

There are issues with some simulation tools not support ulogic though.
A good rule of thumb is to use std_ulogic and std_logic_vector.
Synopsys, Synplify and Leonardo certainly have no problems with this strategy.



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