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Messages from 32550

Article: 32550
Subject: Re: Date/Time at synthesis -> std_logic_vector => just use a ROM
From: Andreas Schmidt <as@blueiguana.com>
Date: Fri, 29 Jun 2001 13:38:25 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
<b><font color="#CC33CC">Hi Andrew,</font></b><font color="#CC33CC"></font>
<p><font color="#CC33CC">- You would just use a small ROM....</font>
<br><font color="#CC33CC">&nbsp; You can generate a ROM very easy using
Coregen...</font>
<br><font color="#CC33CC">&nbsp;&nbsp; In the corresonding MIF (Memory
Iniatialization File) you have to specify the ROM contents...</font>
<br><font color="#CC33CC">- In VHDL you can define a string or integer
constant in your code....</font>
<br><font color="#CC33CC">&nbsp; (like 200106291340) then you always know
the age of your design....</font>
<br><font color="#CC33CC">&nbsp; (yearmonthdayhourminute)</font>
<br><font color="#CC33CC">&nbsp;&nbsp; you can change easily&nbsp; the
constant before building your design...</font>
<br><font color="#CC33CC">&nbsp;&nbsp; you can use this as an initialization
value for a register, too of course...</font><font color="#CC33CC"></font>
<p><font color="#CC33CC">You can generate ROMs very efficient (concerning
the resources you need) using the resources of the CLB (distributed ROM)</font><font color="#CC33CC"></font>
<p><font color="#CC33CC">There are several possibilities to do this...</font><font color="#CC33CC"></font>
<p><b><font color="#CC33CC">cul8r, AS (Andreas)</font></b>
<p>Andrew Bridger wrote:
<blockquote TYPE=CITE>Hi,
<br>We are using Xilinx ISE 3.1, XST synthesis targeting a Virtex-E FPGA.&nbsp;
I
<br>would like to know if there is a way to get the system date/time at
<br>synthesis time and put it into type std_logic_vector(say 32 bits?)
into my
<br>code?&nbsp; This would allow me to read back a register inside the
FPGA that
<br>could tell me the date/time synthesis occured.&nbsp; I.e. this is a
form of
<br>development build ID.
<p>The alternative is for me to manually increase a revision number register
<br>each time I synthesize.&nbsp; This works fine but I thought there might
be a more
<br>automated way.
<p>Ideas?</blockquote>
</html>

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url:http://www.blueiguana.com
org:Blue Iguana Networks;Research & Development
adr:;;4019 Clipper Court;Fremont;CA;94538;USA
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email;internet:as@blueiguana.com
title:Dipl.-Ing. / Senior Hardware Engineer
note;quoted-printable:private homesite:=0D=0A=0D=0Ahttp://www.asic.cc=0D=0A=0D=0A=0D=0Aprivate email address:=0D=0A=0D=0Aas@asic.cc
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Article: 32551
Subject: Re: Date/Time at synthesis -> std_logic_vector => just use a ROM
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 29 Jun 2001 23:02:15 +0200
Links: << >>  << T >>  << A >>

Please don't post HTML.

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se


Article: 32552
Subject: Re: obfuscated tools
From: Goran Bilski <goran@xilinx.com>
Date: Fri, 29 Jun 2001 14:27:55 -0700
Links: << >>  << T >>  << A >>
Hi

Thanks but I need a much higher obfuscation then a netlist.
Something like:
    all names on signals,port,enities,.. to be strings of 'O', '0', '1', 'l'
    and also using the fact that VHDL is free-typing so put as much as possible
on the same line.

Göran



Kevin Neilson wrote:

> If you synthesize your VHDL, and have the synthesizer output a VHDL netlist
> (usually used for function simulation), then this VHDL is functionally
> equivalent to your original but highly obfuscated.  It will be more verbose
> and slower, though.  It will make use of primitive libraries, in the case of
> Xilinx, the UNISIM libraries.
>
> -Kevin
>
> "Goran Bilski" <goran@xilinx.com> wrote in message
> news:3B3CA8E2.1B682B6B@xilinx.com...
> > Hi,
> >
> > Do anyone know of a tool that obfuscate VHDL code?
> >
> > Thanks
> > Göran Bilski
> >
> >


Article: 32553
Subject: Re: Newbee and FAQ
From: cyber_spook <pjc@cyberspook.freeserve.co.uk>
Date: Fri, 29 Jun 2001 22:46:39 +0100
Links: << >>  << T >>  << A >>
I think this is what you are looking for:-

http://www.vhdl.org/vi/comp.lang.vhdl/

Cyber_spook_man


Ruud Baltissen wrote:

> Hallo allemaal,
>
> I still do a lot of things with the old Commodore computers. One of my last
> designs enables one to use PC ISA-cards with a C64 or C128:
> http://home.hccnet.nl/g.baltissen/pccard.htm
> http://home.hccnet.nl/g.baltissen/pccard16.gif
>
> This design needs over 50 IC's and I already would be happy to replace at
> least the glue-logic. So I posted a general question about FPGA's to some C=
> users and somebody answered that the FAQ of your newsgroup would answer a
> lot of questions. Where can I find it, please?
>
> Is there any body willing to have a quick look at the schematics and then
> willing to tell what FPGA could replace all IC's. 8237's, the DMA-chips
> don't need to be included.
> What programmer and software do I need to program it?
> Question: can a FPGA drive a bus or do I need additional buffers?
>
> Thanks for any help in any form !!!
>    ___
>   / __|__
>  / /  |_/     Groetjes, Ruud
>  \ \__|_\
>   \___|       http://Ruud.C64.org


Article: 32554
Subject: Re: clock speed in XC95288XL
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Sat, 30 Jun 2001 09:55:25 +1200
Links: << >>  << T >>  << A >>
Erik Widding wrote:
> 
> "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
> news:3B339091.633A1FF8@gmx.de...
> > I have a xc95288-10 in a design and I would like to divide a 155.52 MHz
> > (yes its STM-1) clock signal down to 38.88 MHz (just divide by four).
> > The counter can be a ripple one. But the datasheet says, it is not
> > possible, even if I go to speedgrade -6 (minimum pulse width 3.3 ns).
> > The duty cycle of the 155.52 MHz signal is not perfectly 50%, but
> > something like 40% can be guarantied I think. Do you think it is
> > possible (AND reliable).
> > [...]
> 
> I would suggest that you use a single external D-flop, configured as a
> T-flop to divide by two.  For $0.50, and approximately 0.1 square-inch of
> PCB real estate (assuming SSOP14 package), your problem is solved.

Look at http://www.fairchildsemi.com/pf/NC/NC7SZ74.html

This will run 200MHz min at 3.3V. 
One divides by 2, Two can do a twisted ring/johnson
counter to right where you want to be.

 If you have a separate clock (almost any Freq), you could use a 3rd as
a 
Delta-Modulation D threshold Bias generator, and AC couple the ECL clock
using
this voltage referance.

 - jg

Article: 32555
Subject: Error messages in Xilinx WebPack ISE
From: root@plexus-technologies.com (Dean Malandris)
Date: Sat, 30 Jun 2001 00:30:53 GMT
Links: << >>  << T >>  << A >>
I'm trying to implement the design and create a programming file for a
custom decoder. When I run the "consistency check" inside the
Schematic Editor in WebPACK ISE, I get an error message stating

"I/O net TO has no pin on symbol".

TO is the net name, I have an I/O marker on this net and it's
connected to the output pin of a library symbol. Not sure why it's
giving me this error message. All the other connections I have in the
schematic look the same and yet generate no errors.

Can anyone elucidate?

Article: 32556
Subject: Xilinx WebPACK ISE OBUFT "ngdbuild:467" error.
From: root@plexus-technologies.com (Dean Malandris)
Date: Sat, 30 Jun 2001 01:33:32 GMT
Links: << >>  << T >>  << A >>
I found I was getting an "ngdbuild:467" error when using an OBUFT in a
schematic design in WebPACK for an XC9500 device. I searched the
answers database on the Xilinx site and it had an answer for me:

"  The bug causes XST to not realize that OBUFT is an output buffer;
therefore, XST proceeds to  place an OBUF after the OBUFT. This is an
illegal connection and generates the error in NGDBuild. 

The work-around is to use OBUFE with an inverter on the enable line;
this provides logic equivalent to an OBUFT. XST properly recognizes
the OBUFE as an output buffer.  "

I've done as it suggests and I still get the same error, after
replacing all the OBUFTs with OBUFEs.  Actually I am using OBUFE8 to
replace OBUFT8. I take it the fix-it applies only to single-output
devices?

Can anyone help on this one?

Article: 32557
Subject: Re: Is the Grass Greener for an Engineer in the USA?
From: stuart_clubb@nospam.hotmail.com (Stuart Clubb)
Date: Sat, 30 Jun 2001 01:52:47 GMT
Links: << >>  << T >>  << A >>
Phil,

Thanks for the FAQ compliement. I am going to start building a web
resource for all this "stuff" to help those thinking of making the
move to better analyse the offers and issues they experience.

>My US bank would not give me a credit card after being here for a year,
>but they would give me a fair rate mortgate without a huge deposit after
>we had been here for 2 months (the same bank!).  Similarly, I easily got

It's amazing how different financial institutions have different
requirements/rules. I checked with my bank (www.1sttech.com) and they
say that they'll take me on at a 10% deposit although the H1-B might
be a problem vs a green card. What percentage was your deposit? If you
let us know the institution, maybe I can follow up with them and see
if they will treat me in a similar light. :-)

>a car lease without any fuss after we had been here less than a month!

My car lease was (as you say) donkey work. I'm just trying to drop
some reality into people's dream of the world paved with gold.

>I guess my advice would be that all things are possible when it comes to
>finance, but it depends on getting the right person who is prepared to
>do a little more donkey work for you than the average Joe/Joanne.  This

Indeed, after you do the donkey work you may be grudgingly accepted by
select institutions, but many just plug the numbers into their
risk-averse computers and you get rejected. However, one cannot always
expect to get the best rate even if you have golden credit in the UK.
Factor all this into your salary negotiations and outline this to the
employer. Oh, and if you already have a job, dont jump to accept the
first offer.

Knowledge, as they say,  is power.

Cheers
Stuart

Article: 32558
Subject: XC9500 drive capability
From: vrezayev@hotmail.com (Vitali)
Date: 29 Jun 2001 19:07:28 -0700
Links: << >>  << T >>  << A >>
Hello,

can I double current sink capability by tying two output pins? 
I know it runs on FPGAs (on "senior" XC4000s). How about CPLDs?

Thanks

Vitali.

Article: 32559
Subject: Re: Is the Grass Greener for an Engineer in the USA?
From: Lasse Langwadt Christensen <langwadt@ieee.org>
Date: Fri, 29 Jun 2001 20:20:03 -0700
Links: << >>  << T >>  << A >>
Stuart Clubb wrote:
> 
snip
> 
> 4 - You'll have NO CREDIT HISTORY. You will be turned down for store
> cards based solely on a non-existent credit history (I have been). You
> will be turned down for the numerous interest-free offers you will see
> relating to electrical goods (forget that widescreen TV matey).
> Basically, you will not be able to get finance on anything. The fact
> that you make a shed-load of cash and have no debts just wont
> register, they'd rather lend money to a Mexican fruit picker with a
> recent bankruptcy than YOU. 
snip

what is the logic behind that?  I assume the people that offer credit 
does so to earn money, why would they rather lend money to 
someone that is known to be bad at paying back debts that someone who 
they don't know ?
   
In Denmark it's almost opposite, as long as you are not registered as
being bad at paying your debt and have an income you can get credit 
almost everywhere  

-Lasse 
-- Lasse Langwadt Christensen, 
-- A Dane in Phoenix, Arizona

Article: 32560
Subject: Re: Newbee and FAQ
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Fri, 29 Jun 2001 23:57:18 -0600
Links: << >>  << T >>  << A >>
Eric Smith wrote:
> 
> Phil Hays <spampostmaster@home.com> writes:
> > There isn't much you can do in a TTL package that you can't do in 8 CLBs, and
> > the XC2S150 has 800+ CLBs.  Smaller would probably be more than enough
> 
> This brings up something I still don't have a good feel for.  If a TTL
> pack is equivalent to an average of four Spartan-II CLBs (just to make a
> wild-ass guess), and the XC2S150 has 800 CLBs, how likely is it that I
> can cram a design that had 200 TTL chips into the XC2S150?  In other words,
> how many CLBs are going to go to waste due to insufficient routing
> resources?

Most of the problem is MSI TTL can have a lot of logic that does not
decompose well.While I have only used altera 10K10 <A earlier burch board :-) >
I found multiplexers and wide random logic to eat up the logic cells. Routing
also became a problem when I had over about 75% CLB's used. 
 
> I know that's going to be different depending on floor planning, but
> I haven't yet been able to even come up with a rough rule-of-thumb
> sort of estimate.

In my case my cpu speed (pseudo pipelined cpu) the alu path was the limiting
speed factor. 

> I'm playing with the XC2S200 using the BurchEd board, and I haven't run
> out of space yet, but my designs aren't very big yet either.

Just wait until you design that 64 bit cpu :-).
Ben.
-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
"Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
Now with schematics.

Article: 32561
Subject: Re: Is the Grass Greener for an Engineer in the USA?
From: stuart_clubb@nospam.hotmail.com (Stuart Clubb)
Date: Sat, 30 Jun 2001 06:59:01 GMT
Links: << >>  << T >>  << A >>
>what is the logic behind that?  I assume the people that offer credit 
>does so to earn money, why would they rather lend money to 
>someone that is known to be bad at paying back debts that someone who 
>they don't know ?

OK, I was being a little sarcastic, but basically when applying for
regular low value credit such as when buying a TV or stereo, a credit
score is generated based upon your payment history. It seems that in
the USA, credit houses are so risk averse that a lack of history is a
terrible unknown that they just cant factor into their equation. Being
a foreign national scares them too. So the low paid migrant who's got
a few years credit history may well get "some" credit even with a
bankruptcy, whereas someone like me making a pile of cash every month
with no debts,  would not.

When it comes to larger loans such as mortgages on fixed property,
they may look a little more closely at the individual circumstance.
However, one mortgage broker I contacted had just one lender who would
lend to me in my situation, and the interest rate was 1% above most
everyone else. They also wanted a maximum loan-to-value of 80%. In
other words, they wanted to be able to foreclose from day 1 and still
make a profit by selling the house at a knock-down price.

Needless to say I told them where to stick their stinking money. :-)

>In Denmark it's almost opposite, as long as you are not registered as
>being bad at paying your debt and have an income you can get credit 
>almost everywhere  

Pretty much the same in the UK. Prove you have an income, an address,
and show you dont have too many debts already and you will get small
amounts of credit without too much difficulty.

It seems that America has just automated the process of scoring so
much that anyone who falls outside the expected norms is just rejected
out of hand.

Cheers
Stuart

Article: 32562
Subject: Re: obfuscated tools
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 30 Jun 2001 00:17:06 -0700
Links: << >>  << T >>  << A >>
Goran Bilski <goran@xilinx.com> writes:
>     all names on signals,port,enities,.. to be strings of 'O', '0', '1', 'l'

You might as well rename symbols randomly rather than trying to make them
out of similar-looking characters.  Why?  Because if you do use ohs and zeros,
etc, it's easy enough for someone else to simply rename everything randomly.
You haven't really gained anything.

Article: 32563
Subject: Re: Newbee and FAQ
From: Philip Freidin <philip@fliptronics.com>
Date: Sat, 30 Jun 2001 01:30:58 -0700
Links: << >>  << T >>  << A >>
For intro infor on FPGAs, here are some sites to go look at:

www.optimagic.com
www.fpga-faq.com
www.fpgacpu.org
www.xilinx.com
www.altera.com

The glue logic of your design will probably all fit into a small FPGA.
You might want to get a copy of Xilinx's WebPack software, which is
free at their web site. While limited in functionality, it is more than enough
for a project of this size. Once you get going and get all the TTL into 1
FPGA, there is no reason not to continue, and do the 8237 DMA circuits
too, although that is certainly more ambitious.

From an experimenters point of view, there are some good intro boards
available from Burch and Xess

http://www.BurchED.com.au
http://www.xess.com/FPGA/homepage.html

With regard to programmer software, the WebPack sw is an example of this.
If you stay with RAM programmable FPGAs, the final result of the software
is a bitstream. There are several ways to load this into the FPGA, including
from a PROM (every time the system is turned on, sort of like booting a CPU),
or you can even have your CPU load it from some other source, such as
storing it on a disk.

Have fun

Philip Freidin



On Fri, 29 Jun 2001 13:55:14 +0200, "Ruud Baltissen" <Ruud.Baltissen@abp.nl>
wrote:
>Hallo allemaal,
>
>I still do a lot of things with the old Commodore computers. One of my last
>designs enables one to use PC ISA-cards with a C64 or C128:
>http://home.hccnet.nl/g.baltissen/pccard.htm
>http://home.hccnet.nl/g.baltissen/pccard16.gif
>
>This design needs over 50 IC's and I already would be happy to replace at
>least the glue-logic. So I posted a general question about FPGA's to some C=
>users and somebody answered that the FAQ of your newsgroup would answer a
>lot of questions. Where can I find it, please?
>
>Is there any body willing to have a quick look at the schematics and then
>willing to tell what FPGA could replace all IC's. 8237's, the DMA-chips
>don't need to be included.
>What programmer and software do I need to program it?
>Question: can a FPGA drive a bus or do I need additional buffers?
>
>Thanks for any help in any form !!!
>   ___
>  / __|__
> / /  |_/     Groetjes, Ruud
> \ \__|_\
>  \___|       http://Ruud.C64.org
>
>
>

Philip Freidin
Fliptronics

Article: 32564
Subject: Re: Newbee and FAQ
From: Philip Freidin <philip@fliptronics.com>
Date: Sat, 30 Jun 2001 01:33:08 -0700
Links: << >>  << T >>  << A >>
The schematic on your site, as a GIF, is really nice and crisp. How
did you get from your schematic system to such a nice GIF file?

Philip

On Fri, 29 Jun 2001 13:55:14 +0200, "Ruud Baltissen" <Ruud.Baltissen@abp.nl>
wrote:
>Hallo allemaal,
>
>    .....
>
>http://home.hccnet.nl/g.baltissen/pccard.htm
>http://home.hccnet.nl/g.baltissen/pccard16.gif
>

>  \___|       http://Ruud.C64.org

Philip Freidin
Fliptronics

Article: 32565
Subject: Re: Xilinx System Generator Simulation Problem
From: michland@setltd.com (Michael Tzvetkov)
Date: 30 Jun 2001 03:36:56 -0700
Links: << >>  << T >>  << A >>
"JianYong Niu" <cop00jn@shef.ac.uk> wrote in message news:<9hi5gn$js6$1@hermes.shef.ac.uk>...

Hi, JianYong:

 You should get new version of CoreGen. If you are using SysGen v1.1
you need CoreGen v3.3 with service pack 3 (better SP4). 
Mult_vgen_v2_0 presents there. 

Service packs are free for download from xilinx.com.

> # -- Loading package std_logic_1164
> # -- Compiling entity xlmult_core1
> # -- Compiling architecture behavior of xlmult_core1
> # ERROR: Could not find
> C:/modeltech_xe/xilinx/vhdl/XilinxCoreLib.mult_vgen_v2_0
> # ERROR: xlmult_core1.vhd(34): cannot find expanded name:
> xilinxcorelib.mult_vgen_v2_0
> # ERROR: xlmult_core1.vhd(34): Unknown field: mult_vgen_v2_0.
> # ERROR: xlmult_core1.vhd(59): VHDL Compiler exiting
> # ERROR: C:/Modeltech_xe/win32xoem/vcom failed.
> # Error in macro C:\MATLABR11\work\vcom.do line 26
> # C:/Modeltech_xe/win32xoem/vcom failed.
> #     while executing
> # "vcom -93 xlmult_core1.vhd"
> 
> There is only mult_vgen_v1_0 in xilinxcorelib, but no mult_vgen_v2_0. Where
> can I find that mult_vgen_v2_0?  If it is a library update problem, where
> can I find the update file?
>

Article: 32566
(removed)


Article: 32567
Subject: Re: IOB FF in Synplicity
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Sat, 30 Jun 2001 13:17:10 +0100
Links: << >>  << T >>  << A >>
On Fri, 29 Jun 2001 14:44:27 -0400, Keith R. Williams
<krw@attglobal.net> wrote:

>In article <gr7mjt0b652u7ujjinhehq6r714bdr5n9i@4ax.com>, 
>brian@shapes.demon.co.uk says...
>> On Wed, 27 Jun 2001 09:13:20 -0400, Keith R. Williams
>> <krw@attglobal.net> wrote:
>> 
>> >In article <9hb26c$jav$1@slb6.atl.mindspring.net>, 
>> >austin@da98rkroom.com says...

>> >> map -pr b filename
>> >
>> >I've tried all of the above and it still appears the flops aren't 
>> >getting pushed into the IOBs (this is a XCS40XL-BG256).  Map reports:

>> 
>> map -pr b doesn't always map IOB flops.

>Polarity?  Ouch!  My style is everything inside the package is 
>positive, controls I design (I'm stuck with what I buy) outside the 
>package are negative (hang over from years of TTL design).  Isn't that 
>why I'm using a HDL?  Isn't that why the boss plunked down $50K for the 
>tools? 

No kidding. 
I have Renoir too, and use it to wrap the specials and warts (inc. this
one and only polarity inversion) into IO versions of my blocks instead
of the general-purpose versions. Some people like Renoir, some don't. I
do. It keeps all the structural coding and component interfaces intact,
and there are parts of the problem where I think schematically.
 
>> Modifying the design into one that the synthesiser won't screw up has
>> been, for me, a tedious and iterative process (not helped by the poor
>> diagnostics)
>
>...and I thought HDLs were intended to improve productivity.

IMO - you need both (HDL and schematic), rather than trying to force all
your ideas to fit one paradigm.

But I/O interfaces ... should be very easy for synth tools to treat as
special cases, allowing explicit definitions instead of trying to infer
them from the HDL code.

>> Keith: you could check your design for the abovementioned conditions
>> (not an exhaustive list) and see if fixing them corrects the problem.
>
>Keith has no time for this on my SpartanXL design now. 

Understood...

>> XILINX: 
>> 1) You could improve the MAP diagnostics to say why flops couldn't be
>> mapped ... e.g. 
>> <pin>: ENBFF - not mapped into IOB, shared enable signal.
>> <pin>: OUTFF - not mapped into IOB, shared output signal.
>> etc...
>
>Amen! If I explicitly tell it I want FFs swept into IOB and explicitly 
>code them, I sure want to know, *in neon*, if it can't or won't do what 
>I tell it.

Of course... you already know that map.mrp tells you what has and hasn't
been migrated, at the level of each pin. Just not why...

- Brian


Article: 32568
Subject: Re: Newbee and FAQ
From: Dave Vanden Bout <devb@xess.com>
Date: Sat, 30 Jun 2001 08:21:40 -0400
Links: << >>  << T >>  << A >>
Philip Freidin wrote:

> From an experimenters point of view, there are some good intro boards
> available from Burch and Xess
>
> http://www.BurchED.com.au
> http://www.xess.com/FPGA/homepage.html

Thanks for the mention in your message.  Sorry to be picky here, but this URL is
invalid.  Use this one instead:

http://www.xess.com






--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||



Article: 32569
Subject: Re: Newbee and FAQ
From: Phil Hays <spampostmaster@home.com>
Date: Sat, 30 Jun 2001 14:51:57 GMT
Links: << >>  << T >>  << A >>
Ruud Baltissen wrote:

> Is there any body willing to have a quick look at the schematics and then
> willing to tell what FPGA could replace all IC's. 8237's, the DMA-chips
> don't need to be included.

I'd start by looking at Xilinx Spartan-II.  Altera, Actel and others make
similar parts.

http://www.xilinx.com/partinfo/databook.htm

In a PQ208 package, you get 140 IO's, which will allow you to connect to all
pins of both connectors (other than power and ground, of course!)

There isn't much you can do in a TTL package that you can't do in 8 CLBs, and
the XC2S150 has 800+ CLBs.  Smaller would probably be more than enough


> What programmer and software do I need to program it?

Cable on parallel port, can buy fairly cheap or build your own.  Or you might
design a small CPLD that decodes a Commodore address and handles loading the
FPGA (of course you need to copy the bit file from the design PC to the
Commodore first).  Or you can put a prom on the board.  These are RAM based
FPGA's, they need to be loaded every time the power comes on.

Software at:

http://www.xilinx.com/sxpresso/webpack.htm


> Question: can a FPGA drive a bus or do I need additional buffers?

The newest latest stuff can't talk to 5 Volt logic, but the affordable older
stuff can.  Current drive isn't an issue, most will drive at least 16 mA.


> Thanks for any help in any form !!!

Suggestions:

1) use one clock.  Gated clocks in FPGAs are evil.
2) start simple.  Don't try to build the final design the first go.
3) simulate, simulate, simulate.  It's a lot easier to debug a simulation than
real hardware.



-- 
Phil Hays

Article: 32570
Subject: Where are the BUFE and BUFT symbols in Xilinx WebPACK???
From: www@plexus-technologies.com (Dean)
Date: Sat, 30 Jun 2001 15:33:35 GMT
Links: << >>  << T >>  << A >>
I need to create a byte wide bus multiplexer in an XC9572-PC84 chip. I found
that I can't take a bunch of OBUFE primitives and join their outputs all in
parallel as they're meant to drive an output pad directly and so it's an
illegal connection. 

Fair enough. 

BUT... I can't find the internal tri-state buffer elements I need, BUFE and
BUFT,  in order to build  what I want. Where are these in WebPACK? The
library listing shows I have buffer.lib and io_buffer.lib, but these
primitives don't exist anywhere in these libraries, or in any of the others
created by the install.

Can someone enlighten me please?

Article: 32571
Subject: Re: Converting character to integer in VHDL
From: vhdlcohen@aol.com (VhdlCohen)
Date: 30 Jun 2001 16:37:21 GMT
Links: << >>  << T >>  << A >>
>I have a problem with VHDL: I have looked FAQs and even found 
>similar questions on the web. Still I can't find out how to convert 
>(ascii)characters to integer (or to std_logic_vector).
>
>For example I have following code:
>...
>signal c: character;
>
>-- (This can be seven bit wide vector too).
>signal byte_out: std_logic_vector (7 downto 0);
>...
>
>Here I should put the character c to byte_out but I don't know how to do 
>it...
An easy method for testbench designs is to use the textio read /write 

for example: 
  s := "1234"; -- s is of type string 
 write(L, s);  -- L is of type line 
 read(L, integer_variable);
-- integer_variable will have the value 1234 in integer type. 
If you do not want to go thru both of these steps, you can include those steps
into a function, 
I'll let you write that one!
--------------------------------------------------------------------------
------------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830
http://www.vhdlcohen.com/                 vhdlcohen@aol.com  
Author of following textbooks: 
* Component Design by Example ... a Step-by-Step Process Using 
  VHDL with UART as Vehicle",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
--------------------------------------------------------------------------
------------------------------------------ 


Article: 32572
Subject: free 8 bit cpu core and spartan2
From: "marco" <mpriarone@tiscalinet.it>
Date: Sat, 30 Jun 2001 19:49:28 +0200
Links: << >>  << T >>  << A >>
Hi all,
 has anyone tried to implement one on the free cpu cores available on the
net on a spartan2 with an external sram ?
Thanks
Marco Priarone



Article: 32573
Subject: Re: XC9500 drive capability
From: Peter Alfke <palfke@earthlink.net>
Date: Sat, 30 Jun 2001 18:36:55 GMT
Links: << >>  << T >>  << A >>
Yes, it works. All these output structures are almost the same.
The issue is to what extent the current divides equally between
the two drivers. And if they have the same basic characteristic,
and are adjacent on the die, they track very well.

Peter Alfke, Xilinx Applications

Vitali wrote:

> Hello,
>
> can I double current sink capability by tying two output pins?
> I know it runs on FPGAs (on "senior" XC4000s). How about CPLDs?
>
> Thanks
>
> Vitali.


Article: 32574
Subject: Re: Where are the BUFE and BUFT symbols in Xilinx WebPACK???
From: Philip Freidin <philip@fliptronics.com>
Date: Sat, 30 Jun 2001 11:53:16 -0700
Links: << >>  << T >>  << A >>
On Sat, 30 Jun 2001 15:33:35 GMT, www@plexus-technologies.com (Dean) wrote:
>I need to create a byte wide bus multiplexer in an XC9572-PC84 chip. I found
>that I can't take a bunch of OBUFE primitives and join their outputs all in
>parallel as they're meant to drive an output pad directly and so it's an
>illegal connection. 
>
>Fair enough. 

Yep. these are pin drivers, so the outputs are physically pins (well actually,
pads on the chip) .

>BUT... I can't find the internal tri-state buffer elements I need, BUFE and
>BUFT,  in order to build  what I want.

Did you study the architecture of the data sheet?

     http://www.xilinx.com/partinfo/9572.pdf

or more importantly, the Family architecture discription ?

   http://www.xilinx.com/partinfo/9500.pdf


You will see that this architecture does not have internal tri-states.

>Where are these in WebPACK? The
>library listing shows I have buffer.lib and io_buffer.lib, but these
>primitives don't exist anywhere in these libraries, or in any of the others
>created by the install.

So you should just design a MUX as a replacement for the internal
tri-state bus.

>Can someone enlighten me please?

Hope the above helps you,

Philip
Philip Freidin
Fliptronics



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