Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 33800

Article: 33800
Subject: Re: Which is the best Design Toolchain?
From: jaime.aranguren@ieee.org (Jaime Andres Aranguren Cardona)
Date: 5 Aug 2001 16:00:26 -0700
Links: << >>  << T >>  << A >>
Dear Mr. Schutte

You are right about the fact that each project has a different
approach. But, as a good backgroud toolset, which one would you
recommend?

Thanks a lot,

"Victor Schutte" <victors@mweb.co.za> wrote in message news:<3b6d94a0.0@news1.mweb.co.za>...
> I use Altera's software and use AHDL, Schematic, VHDL and Verilog. Each
> project differs and requires a different angle. Example: My one CPU project
> is very simple in VHDL but my Dual Port RAM network card took less that
> 30minutes to do in schematic. I gained a few ns speed when I redesigned my
> one CPLD address decoder from VHDL to AHDL.  Like I said every project is
> different. Also, I have many "PLD" friends and web contacts all working with
> different packages and languages, so to do everything and understand most
> methods have their advantages.
> 
> For portability I would prefer (1) VHDL and (2)Verilog.
> 
> A nice to have will be to do state machines with truth tables,  like I did
> years ago in Log/IC. VHDL is way is to bulky.
> 
> 
> Victor Schutte
> Zerksus Engineering
> 
> "Jaime Andres Aranguren Cardona" <jaime.aranguren@ieee.org> wrote in message
> news:14a86f87.0108050942.7de276c0@posting.google.com...
> > Hi, everybody.
> >
> > Want to generate opinions, from diverse kind of professionals, about
> > the Design Tools used for FPGA/CPLD/ASIC designs.
> >
> > What is the industry-standard method for design? Is it text based
> > VHDL/Verilog entry, text based test benches generation and graphical
> > simulation? Or do professionals prefer alternate ways, such Finite
> > State Machines (graphical entry), Block Diagrams, Truth Tables and/or
> > Schematics?
> >
> > And what can be considered more "universal" and "standard", between
> > tools like Xilinx's Foundation and Mentor Graphics' Renoir, ModelSim
> > and Leonardo Spectrum?
> >
> > I expect to generate an instructive discussion topic, invlolving
> > people from industry and academic spheres.
> >
> > Best regards,
> >
> > Jaime Andres Aranguren Cardona
> > jaime.aranguren@ieee.org
> > jaime.aranguren@computer.org

Article: 33801
Subject: Re: Building ROM and RAM blocks - Xilinx Foundation Series 3.1i
From: "Erik Widding" <widding@birger.com>
Date: Mon, 06 Aug 2001 00:05:42 GMT
Links: << >>  << T >>  << A >>
"Andy Peters <andy [@] exponentmedia com >" <".> wrote in message
news:VGga7.1228$B.115611@newsread1.prod.itd.earthlink.net...
> Manoj K Krishnan wrote:
> >
> >         Iam trying to build a ROM and RAM module using Xilinx Foundation
> > series 3.1i (VHDL coding) I tried using Core Generator
>
> Get a Real synthesis tool (Synplify or Leonardo) and infer the RAMs.
> The Core Generator simulation models are broken.
>
> -andy

I swear by Synplify.... but it will not (yet) infer the RAM that I use most
often, the true dual port ram with two different port sizes, in Xilinx
Virtex/Spartan-II architecture.  In the signal processing designs that I
have done this part is invaluable, as memories are a really good place to
change data bus widths for free in the Virtex architecture.  You have to
build it yourself, or use the core generator, as it is not inferable through
Synplify.


Regards,
Erik Widding.


--
Birger Engineering, Inc.  --------------------------------  781.481.9233
38 Montvale Ave #260; Stoneham, MA 02180  -------  http://www.birger.com






Article: 33802
Subject: Re: Which is the best Design Toolchain?
From: cjwang_1225@hotmail.com (chris)
Date: 5 Aug 2001 17:34:34 -0700
Links: << >>  << T >>  << A >>
i am in ASIC design and we usually prototype with fpgas. in terms of
fpga tools, i have settled on the following:

design entry:
verilog (using codewright...its a great text editor)

simulation:
 modelsim - best simulator for the price. also allows you to read vcd
files which comes in handy  when importing stimulus vectors from a
logic analyzer.

synthesis:
synplicity - hands down...one of the best and easiest synthesis tools
to work with. there are some things that could be better, but the same
can be said for synopsys and (as far as i know) leonardo.

place and route: 
depends on whose chip i am using. 
Xilinx: biggest chips, many features...i usually prototype with
Virtex-E or Virtex-II chips and when you get that big, its either
xilinx or altera. the xilinx chipscope is quite a useful tool as well
since it lets you view the innards of the fpga. also outputs all
waveforms in vcd format which is quite handy for importing into
modelsim.

Altera: hmmm...haven't used too many of their newer devices since
xilinx got to me first. i am interested in some of their new chips for
proto and also for eval board purposes because of the features they
are integrating. worth a second look in my opinion.


one thing that i am sold on is that most people doing large fpga
designs really should use an ASIC-like methodology such as writing a
testbench for their design, doing a post-synth simulation and also a
post place and route timing simulation. it is so much easier and
quicker to debug in simulation space than in a real lab since all the
signals are just a mouse click away from you. just my two cents. good
luck on the survey.
chris wang

Article: 33803
Subject: Re: Slightly off topic - PCs for running FPGA tools
From: cjwang_1225@hotmail.com (chris)
Date: 5 Aug 2001 17:42:20 -0700
Links: << >>  << T >>  << A >>
i can't give you hard numbers for synthesis and place and route
speeds, but when comparing my co-workers athlon with 512 MB PC133
SDRAM and my Pentium 4, 1.7 GHz with 1 GB RDRAM, i noticed that there
was significant improvement in synthesis and place and route times. we
actually benchmarked the simulation times which was what we were
interested in and the P4 1.7 with rambus outperformed the athlon 1 Ghz
by about 300%. originally, i thought the difference would only be
around 50% or so since the athlon chip 1GHz performance is not that
far away from a pentium 1.7GHz performance. the benchmarks on toms
hardware say that the fast memory only improves performance by about
10% or so, but in our industry, i think we push the memory bandwidth
of our PCs. i pretty much believe that the big boost in simulation
performance was not that my processor was faster, but that my memory
was much faster than the PC133. i am pretty sure that place and route
and synthesis are very memory intensive also, since i always run out
of ram on my laptop whenever i try to synthesize my design.
chris wang

Article: 33804
Subject: Principal FPGA design/verification contractor available
From: "Mike Damiano" <damiano@mediaone.net>
Date: Mon, 06 Aug 2001 02:36:11 GMT
Links: << >>  << T >>  << A >>
Principal Engineer with over 12 years of experience with companies
including Lockheed (BAE), Cabletron Systems, and additional
telecom/networking companies.

My experience includes designs using Xilinx FPGAs, with my last design
being a Virtex-XV1000.
Other designs include Altera, Actel, and Lattice FPGAs and CPLDs.

General design experience in network protocols, including gigabit ethernet,
and various memory interfaces.

Experience in all Xilinx tools, including FPGA editor, Coregen, and Timing
Analyzer.
Experience in Altera, Actel, and Lattice design tools.
Experience in Synplicity, Exemplar Leonardo, and Synopsys Synthesis tools.
Experience in design verification using Verilog and Vera. 
Experience in system (chip, board, and system)  verification, test, debug,
and integration.

I reside in the New England (North of Boston) area and am available
on-site.  
If desired, I can work from home using my high speed Internet connection
for companies not in the New England area.
Willing to travel as necessary.

If interested, please call me at 603-661-5615.

Thanks,
Mike Damiano

Article: 33805
Subject: Core Generation 2.1i
From: LUUTHANHTRUNG <ttcminh@dee.hcmut.edu.vn>
Date: Sun, 5 Aug 2001 20:27:13 -0700
Links: << >>  << T >>  << A >>
Hi,
Now I 'm using Xilinx Foundation 2.1i intergrated The Core Generation 2.1i.
I don't know how to use the command " Get_models" in the Core. Please tell me more clearly.
WHen I use OUTPUT file *.v ( Verilog behavioral models extracted from the core generator directory tree ) for input HDL Editor to check syntax , the errors always appear. I don't know why ?
All your helps will be appreciated .
Your sincerely,
LUUTHANHTRUNGHi,
Now I 'm using Xilinx Foundation 2.1i intergrated The Core Generation 2.1i.
I don't know how to use the command " Get_models" in the Core. Please tell me more clearly.
WHen I use OUTPUT file *.v ( Verilog behavioral models extracted from the core generator directory tree ) for input HDL Editor to check syntax , the errors always appear. I don't know why ?
All your helps will be appreciated .
Your sincerely,
LUUTHANHTRUNGHi,
Now I 'm using Xilinx Foundation 2.1i intergrated The Core Generation 2.1i.
I don't know how to use the command " Get_models" in the Core. Please tell me more clearly.
WHen I use OUTPUT file *.v ( Verilog behavioral models extracted from the core generator directory tree ) for input HDL Editor to check syntax , the errors always appear. I don't know why ?
All your helps will be appreciated .
Your sincerely,
LUUTHANHTRUNG

Article: 33806
Subject: Core Generation 2.1i
From: LUUTHANHTRUNG <ttcminh@dee.hcmut.edu.vn>
Date: Sun, 5 Aug 2001 20:28:34 -0700
Links: << >>  << T >>  << A >>
Hi,
Now I 'm using Xilinx Foundation 2.1i intergrated The Core Generation 2.1i.
I don't know how to use the command " Get_models" in the Core. Please tell me more clearly.
WHen I use OUTPUT file *.v ( Verilog behavioral models extracted from the core generator directory tree ) for input HDL Editor to check syntax , the errors always appear. I don't know why ?
All your helps will be appreciated .
Your sincerely,
LUUTHANHTRUNG

Article: 33807
Subject: Re: Duty cycle problem with Virtex-II
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Sun, 05 Aug 2001 20:29:25 -0700
Links: << >>  << T >>  << A >>
Sune,

For the best duty cycle, use the DCM with duty cycle correction turned ON, and
use the CLK0 to the DDRFF clk input for the top FF, and the CLK180 output for
the bottom DDFFF clk input.  Tie the top DDRFF D hi, and the bottom DDRFF D
low.  The use of the DDR FF allows for precise clock forwarding >400 MHz (> 800
Mb/s).

The reason why the hotline did not respond is that we are presently working on
the duty cycle issue in the FPGA Lab.  We found a bad lot of 2V1000 ES material
that had a servere frequency sensitivity.  It is unlikely anyone outside of
Xilinx received this lot (still tracking the shipments).

IBIS simulations are key to see if the IO itself can faithfully reproduce a
50/50 duty cycle.

For the best symmetry, the DCI feature is an exellent way to keep the pull up
and pull down matched to 50 ohms (best symmetry).  The LVDS output must be used
above about 150 MHz, again due to having the best performance.  Some tests
indicate that DCI versions of HSTL may operate at very high frequencies (>150
MHz).

Some folks have also confused the jitter with "bad" duty cycle.  150 ps of
jitter at 333 MHz is 10% of the DDR period (1.5 ns).  Examining the cycle to
cycle performance shows between 50 and 53 % duty cycle correction (only one tap
adjustment  of ~ 40 ps is allowed on a delay line every N*256 clock, where N is
the "jitter frequency" set by the jitter filter attribute).

The little 2V40 board also had the very first ES material, which had a slightly
off target process for the IO transistors (another good reason to use DCI -
fixes the process issue).

Hope this long winded reply helps,

(I was on vacation, or else I would have answered sooner).

Austin Lesea
FPGA Lab Manager
Xilinx, SJ

"Sune G. Krohn" wrote:

> I can't get a signal out of Xilinx Virtex-II 2V100 and 2V40 with a correct
> duty cycle.
>
> I only see this problem in 1.5 and 2.5 voltages mode.
>
> I also see the problem on Xilinx Virtex-II Evaluation Kit with a 2V40.
>
> As output I use OBUF_LVCMOS15_F_16 for 1.5 V and OBUF_LVCMOS33_F_16.
>
> With a frequency about 100MHz is the duty cycle about 35/65. In the test I
> run the clock through a FF to make a 50/50 duty cycle and with no luck.
>
> It is always the high pulse that a shorter than the low, even if I invert
> the signal.
>
> We have asked Xilinx's Technical Support Office United Kingdom every day for
> two weeks and they can't answer the question they just ask irrelevant
> questions. For instance, they ask my to do an IBIS simulation on their
> Evaluation Kit with their chip.
>
> Is there any one that have seen a 50/50 duty cycle on a Xilinx Virtex-II
> 2V100 and 2V40 with about 100MHz and 1.5V I/O ?
>
> Is an Altera a better choice for high speed (150MHz) double data rate
> signals with 1.5 voltage, is there any one that can recommend an FPGA for
> this job ?


Article: 33808
Subject: Re: Slightly off topic - PCs for running FPGA tools
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Mon, 06 Aug 2001 00:48:56 -0400
Links: << >>  << T >>  << A >>
chris wrote:
> 
> i can't give you hard numbers for synthesis and place and route
> speeds, but when comparing my co-workers athlon with 512 MB PC133
> SDRAM and my Pentium 4, 1.7 GHz with 1 GB RDRAM, i noticed that there
> was significant improvement in synthesis and place and route times. we
> actually benchmarked the simulation times which was what we were
> interested in and the P4 1.7 with rambus outperformed the athlon 1 Ghz
> by about 300%. originally, i thought the difference would only be
> around 50% or so since the athlon chip 1GHz performance is not that
> far away from a pentium 1.7GHz performance. the benchmarks on toms
> hardware say that the fast memory only improves performance by about
> 10% or so, but in our industry, i think we push the memory bandwidth
> of our PCs. i pretty much believe that the big boost in simulation
> performance was not that my processor was faster, but that my memory
> was much faster than the PC133. i am pretty sure that place and route
> and synthesis are very memory intensive also, since i always run out
> of ram on my laptop whenever i try to synthesize my design.
> chris wang

Thanks for the info Chris. I have found that the P$R times far exceed
the Synthesis times, so we don't worry too much about Synthesis. 

I am not surprised that you are seeing faster times on the 1.7 P4 than
the Athlon, especially with the smaller, slower PC133 memory. I have
read that the RDRAM is not a lot faster than the DDR 266 memory since
they both have long latency times and that dominates at the faster bus
speeds. 

But for me, the P4 is not part of the decision since it is not and
likely will never be available in laptops. 

One thought about simulation times, I have used Modelsim and noticed
that they have several different versions with claimed speed
differences. It occurred to me that it would be very expensive for them
to offer two or more different lines of code in the different products.
So it is very likely that they are running the exact same code core in
all of their products. The difference is in a switch which tells the
software how fast to run. This kicks in a speed reduction routine in the
slower versions of the code. Depending on how they implement the speed
reduction, you will see very different results in benchmarks on
different machines. This is just my theory, I have not tested this or
asked Modelsim if this is true. But it only makes sense since there
would be no advantage to them to maintaining two lines of distinct code. 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 33809
Subject: Urgent-Simulation with Leo. Spec
From: raokk@rocketmail.com (Krishnakumar Rao)
Date: 5 Aug 2001 22:51:14 -0700
Links: << >>  << T >>  << A >>
I am using Leonardo Spectrum (Version: v20001a2.75 (Release
Production, compiled Aug 29 2000 at 12:35:44)). I have done Post
Synthesis Simulation for Xilinx Virtex devices using Unisim VHDL
Library. But using this library I am unable to do post synthesis
simulation for other Xilinx family devices. Can someone tell me
whether it is possible to do Post Synthesis Simulation for Xilinx
Spartan and 4000 series devices. If so please let me know how this can
be done ?

Article: 33810
Subject: Re: May I connect two pins to the same net?
From: Lasse Langwadt Christensen <langwadt@ieee.org>
Date: Mon, 06 Aug 2001 06:02:50 GMT
Links: << >>  << T >>  << A >>
Paul Teagle wrote:
> 
> "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
> news:3B6E5599.31971F18@gmx.de...
> > vr schrieb:
> > >
> > > > the behaviour of the undefined pins (DRIVING a signal) fooled us a
> lot.
> > > > :-(
> > >
> > > Bit me too. Who expected such weirdness?
> > >
> > > Perhaps this was explained some place else but is there an easy way to
> > > tell Max+Plus II to make unused I/Os tri-stated(inputs)? Or an easy way
> to
> > > assign un-used I/Os to VCC/GND?
> >
> > Altera suggest to define all unused pins as inputs. Then, if you dont
> > use them in your VDHL, the will be tristated.
> > It works, but its still weird.
> >
> 
> I think the reason as to why the Max+Plus defines unused pins as outputs is
> that otherwise you would have floating CMOS inputs - and they would tend to
> half rail and consume excessive currents, low noise immunity etc etc. The
> Hi-Z refers to the output pins. Inputs are by nature high impedance.
> 
> That's the case on the 10K devices. Maybe the 20K family (I've never used
> them) has internal bus keeper resistors and thus they are pulled up/down
> internally, and the Quartus s/w knows this and thus defaults to the safer
> "input" configuration.

why not just default to a tristate output, possibly with pullup, 
no floating inputs and no risk of driving something unintensionally  

-Lasse
-- Lasse Langwadt Christensen, 
-- A Dane in Phoenix, Arizona

Article: 33811
Subject: Re: I needs a saturable adder.
From: gah@ugcs.caltech.edu (glen herrmannsfeldt)
Date: 6 Aug 2001 06:38:12 GMT
Links: << >>  << T >>  << A >>
> I need a saturable adder like the ALU in DSPs.
> I thought maybe you could just sign-extend the two input
> busses, add them, then detect if the result has overflowed
> the input bus width. If so, the result could be saturated
> to max-neg or max-pos.
>
> AHDL seems a bit limited for handling signed numbers. I'm
> learning some VHDL because it seems to have more constructs
> and knows about signed/unsigned numbers.

I once did a Xilinx design with a saturating adder.  In most cases,
I only had to worry about underflow, not overflow.  At the end
of the carry chain, with one FG I could detect the underflow, and
then use the otherwise unused input on the rest of the FG to
generate the saturated value.  In the one case with an overflow,
the I passed the signal on to the following stage, which had an
extra input available.

That was a max(a,b), the maximum of two inputs, also done by using
the value at the end of the carry chain as an input to the other FG's.

I had these as Xilinx macros that were substituted after the varilog
was compiled.  Either the underflow saturating adder, or max(a,b)
would do 2n bits in n+1 CLB's, using the fact that the carry chain
works independently of the FG lookup values.

-- glen

Article: 33812
Subject: Re: Which is the best Design Toolchain?
From: Tobias Russ <tobias.russ@mixed-mode.de>
Date: Mon, 06 Aug 2001 09:32:02 +0200
Links: << >>  << T >>  << A >>
Hi Jaime,

here are my personal opinions to your topic:
First thing: As description language use VHDL or Verilog, because they
are mostly inter operable between tools. I prefer the text based entry
for my self. This gives me a maximum on independence of tools. But I
think a block based graphical entry, with HDL descriptions of the blocks
is an good alternative (if the generated HDL code is good).
A really universal code and design method is hard to find, because if
you want to use the special features of a device or a tool you always
get in conflict with inter operability (like using the FLI of Modelsim
for testbenches, or instantiating a PLL in an FPGA). 
The problem with the tools from the FPGA vendors (like Quartus or
Foundation) is that if you use their design entry methods (graphical)
you are stuck to this tool and vendor. 
So my conclusion is use text based entry with an good editor (like
Xemacs with VHDL-Mode).

Tobias Ru

Jaime Andres Aranguren Cardona wrote:
> 
> Hi, everybody.
> 
> Want to generate opinions, from diverse kind of professionals, about
> the Design Tools used for FPGA/CPLD/ASIC designs.
> 
> What is the industry-standard method for design? Is it text based
> VHDL/Verilog entry, text based test benches generation and graphical
> simulation? Or do professionals prefer alternate ways, such Finite
> State Machines (graphical entry), Block Diagrams, Truth Tables and/or
> Schematics?
> 
> And what can be considered more "universal" and "standard", between
> tools like Xilinx's Foundation and Mentor Graphics' Renoir, ModelSim
> and Leonardo Spectrum?
> 
> I expect to generate an instructive discussion topic, invlolving
> people from industry and academic spheres.

Article: 33813
Subject: Re: Why did Zephram spool outside all the users? We can't post procedures unless Brion will grudgingly dig afterwards.
From: "ŷǷ" <postmaster@[127.0.0.1]>
Date: Mon, 06 Aug 2001 07:56:37 GMT
Links: << >>  << T >>  << A >>
Greetings,

What you are seeing is a Usenet Flood from a person(s) calling himself
Hipcrime (aka: Dippy, Dipslime, Dipshit, ect...)  It is being done to
disrupt posting in the newsgroup NEWS.ADMIN.NET-ABUSE.EMAIL (NANAE).
Hipcrime has been flooding NANAE for a long time, and most people from that
group have developed filters to block the floods.  But. he is cross-posting
the floods to several other groups, in hopes that people will reply to the
message, and then NANAE gets flooded with the replies to Hipcrimes's posts.

So please ignore the post from Hipcrime, and let him throw his little
tantrum.  Eventually he will be caught and dealt with.

Regards,
Anthony
---
Use twansenne@homtail.com
to reply to me directly.
---
FYI...
For more info on Hipcrime...
http://www.whew.com/On-Line_Spam/hipcrime_FAQ.shtml
http://extra.newsguy.com/~rchason/

Nfilter website to filter newsgrop spam/floods...
http://www.nfilter.org/index.html

And another little tid bit...
http://www.geocities.com/hcfaq/


"Rick Filipkiewicz" <rick@algor.co.uk> wrote in message
news:3B6D58A4.CEC7A8B9@algor.co.uk...
>
>
> Austin Clarkson wrote:
>
> > Let's propagate for the filthy structures, but don't disrupt the
> > soft operators.  Joie will smartly delete beside Russ when the
> > violent plotters put against the moronic cybercafe.  Well, routers
> > defeat on lazy rooms, unless they're discarded.  A lot of solid
> > ugly screens will stupidly prepare the iterations.  He will negotiate
> > sneakily if Andrew's machine isn't usable.  We quickly recycle
> > behind opaque shiny highways.  Owen will proliferate the inner
> > programmer and keep it inside its network.  Who defiles usably, when
> > Norbert questions the actual RAM behind the satellite?  If you'll
> > tolerate Quinton's /dev/null with TCP/IPs, it'll wistfully jump the
> > admin.  Steven stops, then Fred regularly gets a official interrupt
> > about Wally's field.  Why did Bill load the desktop about the
> > dense subroutine?  What will we build after Jonnie opens the
> > weak data bus's PERL?  While analysts generally distribute, the
> > Pascals often interface over the specialized inputs.  Gavin wants to
> > sell neatly, unless Frank collaborates fax machines behind Georgette's
> > postmaster.  The outer client rarely causes Gilbert, it knows
> > Simone instead.  If you will corrupt Yolanda's FBI at texts, it will
> > steadily disconnect the procedure.  I generate closed newbies
> > within the untamed major bit bucket, whilst Roxanne familiarly
> > pushs them too.  To be old or erect will moan secret networks to
> > hatefully spool.  When doesn't Mikie dump finitely?  My important
> > ROM won't take before I inflate it.  Will you slump against the
> > web page, if Petra wrongly digs the terminal?  When Zamfir's
> > lower interface floats, Neil beats in abysmal, foolish modules.
>
> What the f*****g hell is all this bollocks about ? Would you & it please
> return to the dingy cave from whence you came.
>
>
>



Article: 33814
Subject: Cordic NCO questions
From: dottavio@ised.it (Antonio)
Date: 6 Aug 2001 01:22:38 -0700
Links: << >>  << T >>  << A >>
Good Morning, I'm producing a CORDIC NCO and I've the following
problems/ question, could you help me on some of this ???

1) The sine and cosine produced spans between -1 and +1 , it is the
case to use an additional bit for the integer part only to represent
-1 and +1 , may I trascure this and use only bits for the fractional
part ??

2) For the accumulator whose values spans between 0 and 6.28 I use 32
bit, it is better to represent 6.28 as all ones and 0 as all zeroes or
I've to use 3 bit for the integer part and 29 bits for the fractional
part, what you suggest ??

Article: 33815
Subject: General question on VHDL code
From: dottavio@ised.it (Antonio)
Date: 6 Aug 2001 01:27:09 -0700
Links: << >>  << T >>  << A >>
Good Morning some question about VHDL :

1) In a project I've to use always the same clock edge  ??? For a
XCV1000 BG560 -4 which is better , the negative or the positive ??

2) Xilinx suggest to use the positional associations in the port map
and not the named association, why ??

3) The "IF" structure produce a more speed design respect to the
"case" structure ??

Thank you, Antonio D'Ottavio

Article: 33816
Subject: Re: Which is the best Design Toolchain?
From: "tb" <primax@jubiipost.dk>
Date: Mon, 6 Aug 2001 10:29:15 +0200
Links: << >>  << T >>  << A >>
Forget Xilinx's Foundation and Mentor and all that.

go to www.ALTERA.COM

And use the free software it's easy
and powerfull

regards
tb

"Jaime Andres Aranguren Cardona" <jaime.aranguren@ieee.org> wrote in message
news:14a86f87.0108050942.7de276c0@posting.google.com...
> Hi, everybody.
>
> Want to generate opinions, from diverse kind of professionals, about
> the Design Tools used for FPGA/CPLD/ASIC designs.
>
> What is the industry-standard method for design? Is it text based
> VHDL/Verilog entry, text based test benches generation and graphical
> simulation? Or do professionals prefer alternate ways, such Finite
> State Machines (graphical entry), Block Diagrams, Truth Tables and/or
> Schematics?
>
> And what can be considered more "universal" and "standard", between
> tools like Xilinx's Foundation and Mentor Graphics' Renoir, ModelSim
> and Leonardo Spectrum?
>
> I expect to generate an instructive discussion topic, invlolving
> people from industry and academic spheres.
>
> Best regards,
>
> Jaime Andres Aranguren Cardona
> jaime.aranguren@ieee.org
> jaime.aranguren@computer.org



Article: 33817
Subject: Re: May I connect two pins to the same net?
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Mon, 06 Aug 2001 10:30:17 +0200
Links: << >>  << T >>  << A >>
vr schrieb:
> 
> > the behaviour of the undefined pins (DRIVING a signal) fooled us a lot.
> > :-(
> 
> Bit me too. Who expected such weirdness?
> 
> Perhaps this was explained some place else but is there an easy way to
> tell Max+Plus II to make unused I/Os tri-stated(inputs)? Or an easy way to
> assign un-used I/Os to VCC/GND?

Altera suggest to define all unused pins as inputs. Then, if you dont
use them in your VDHL, the will be tristated.
It works, but its still weird.

-- 
MFG
Falk



Article: 33818
Subject: Re: Homemade Xilinx parallel cable problem + new question
From: Nicolas Matringe <nicolas.matringe@IPricot.com>
Date: Mon, 06 Aug 2001 10:33:07 +0200
Links: << >>  << T >>  << A >>
Kolja Sulimma a crit :
> 
> Many of the problems with the xilinx parallel download cable
> III are due to a bug in the Hardware Debugger software.
> At the end of the programming process all the signals are
> tristated, but are simultaneously set to a "0" value.
> This produces a race condition that can cause the PROG signal
> to go low again.
> Xilinx claims to have fixed this in answer record 6545. This
> is not true, as you can easily verify with a DSO.

Hi
My problem came from the lengrh of the cable. I shortened the FPGA-side
cable and it now works perfectly.
Thanks for all the suggestions

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 33819
Subject: Re: May I connect two pins to the same net?
From: martin.j.thompson@trw.com
Date: 06 Aug 2001 09:37:25 +0100
Links: << >>  << T >>  << A >>
"Peter Ormsby" <faepetedeletethis@mediaone.net> writes:

<snip>
> As far as device support, the latest release of Quartus supports
> almost everything except MAX3000 and MAX7000 (yes, it supports FLEX
> 10K and ACEX 1K).  Here's the link (device support is almost at the
> bottom of this page):
> 
> http://www.altera.com/products/software/quartus2/qts-index.html
> 

Funny - before my posting, I just made a quick check *and again just
now) but I didn;t go as far into it. On
http://www.altera.com/products/software/sfw-index.html it still says
just FLEX6000 for Quartus, with 10K and 1K under MP2.

Ho hum - I'll check the detailed info next time!

Cheers,
Martin


Article: 33820
Subject: Polyphase and VHDL questions
From: dottavio@ised.it (Antonio)
Date: 6 Aug 2001 01:40:00 -0700
Links: << >>  << T >>  << A >>
Good Morning ,
here are some question concerning a polyphase filter I'm realizing,
could you help me on this ??

1) At the output of the polyphase there is a mux that choise one of
the six fir output (..this polyphase interpolate 6) , it is supplied
with a counter modulo 6, I've the clock only on the counter and not on
the mux, is this right by your point of view ??

2) this is the code for the mux :

library	ieee;
use ieee.std_logic_1164.all;

entity commutatore_6 is
	port(in_0, in_1, in_2, in_3, in_4, in_5 :	in std_logic_vector(11
downto 0);
		sel			:	in  std_logic_vector(2 downto 0);
		out_comm	:	out std_logic_vector(11 downto 0));
end commutatore_6;

architecture comm_arch of commutatore_6 is
begin				  
			with sel select
				out_comm <=	in_0 when "000",	
			  				in_1 when "001",	
							in_2 when "010",	
							in_3 when "011",	
							in_4 when "100",	
							in_5 when "101",	
							"XXXXXXXXXXXX" when others ;
end comm_arch ;



how I can insert a reset that produce out_comm = "000000000000" when
reset = 1 ??

3) for the counter output corrisponding to the sel of the multiplier,
it is better to use one hot encoding like in state machine or it is
correct in the way I made, three bits for 6 states ???

4) To insert the coefficients in the polyphase is better to use the
function conv_std_logic or directly to map the binary rappresentation
of the coefficient in the VHDL code ??

5) Last and strong question :
with this polyphase I interpolate and produce also SRRC filtering but
someone told me that this is not a flexible architecture, it is better
to add also a CIC that it's a programmable interpolator, but how I can
interpolate 3 , 4 , and 6 using a cascade of a polyphase filter
(..that must interpolate at least 2 and ) and a CIC filter ??

Article: 33821
Subject: Re: Spartan II and asynchronous memory interface
From: Steven Derrien <sderrien@irisa.fr>
Date: Mon, 06 Aug 2001 11:06:19 +0200
Links: << >>  << T >>  << A >>


Rob Finch wrote:
> 
> I know this is a really dumb question but, is the sram module connected to a
> pair of module ports that will work with the sram ? Several of the ports
> will 'almost' work except they have an input only signal on one of the pins.
> Which I believe ends up being connected to the OE of the ram. Are you using
> the constraints editor to set the pin locations ? I am using a B3 Spartan2+
> board and the only port the sram module can be connected to is the J6, J9
> pair. 

We just checked, abnd the module is connected to J6 and J9.

> Also I have written a little test hardware that tests the ram using a
> checkerboard pattern, and it's not found any errors. I could mail it to you
> if you're interested. 

Yes, please that would help us a lot !!

> I've only tested at 8MHz so far, but as other posts
> point out, it's not necessarily the clock frequency that causes a problem.

We'll perform additional check to see if it works at higher frequencies.

Steven

> 
> "Steven Derrien" <sderrien@irisa.fr> wrote in message
> news:3B697EF9.E5BDF155@irisa.fr...
> > Hi,
> >
> > We are curently trying to port the XR16/Xsoc project (www.fpgacpu.org)
> > to a VHDL targeted to the BurchEd Spartan II board
> > (http://www.burched.com)
> >
> > We plan to make our work freely available, but are currently stuck on
> > a problem. The design is a 16 CPU-SOC which interfaced to a parallel
> > port.
> >
> > We have somes on-chip blockrams which serves as ROM, and off-chip
> > asynchronous
> > SRAM whiwh serves as main memory. Our problem is that we get frequent
> > errors when accessing the off-chip SRAM banks. Generally a single bit
> > wrong in a 16 bit data word every 200-300 access.
> >
> > All simulation (RTL,gate-level,post place and route) went fine.
> > Right now, our system is clocked at 1Mhz far below its maximum
> > frequency.
> > Besides, the SRAM Write Enable command output signal is registered
> > (although not in a IOB register) to avoid glitches which could cause
> > wrong write operations.
> >
> > All IOB are configured with SLOW slew-rate and drive 12mA (default IOB
> > config)
> >
> > We have been beating our heads on this problem for almost a week now,
> > are there any experts around there to offer some tips/ideas/advices ?
> >
> > Thanks,
> >
> > Steven

Article: 33822
Subject: Re: Slightly off topic - PCs for running FPGA tools
From: "Ulf Samuelsson" <ulf@atmel.dot.com>
Date: Mon, 6 Aug 2001 11:30:10 +0200
Links: << >>  << T >>  << A >>


> One thought about simulation times, I have used Modelsim and noticed
> that they have several different versions with claimed speed
> differences. It occurred to me that it would be very expensive for them
> to offer two or more different lines of code in the different products.
> So it is very likely that they are running the exact same code core in
> all of their products. The difference is in a switch which tells the
> software how fast to run. This kicks in a speed reduction routine in the
> slower versions of the code. Depending on how they implement the speed
> reduction, you will see very different results in benchmarks on
> different machines. This is just my theory, I have not tested this or
> asked Modelsim if this is true. But it only makes sense since there
> would be no advantage to them to maintaining two lines of distinct code.
>
>

AFAIK, the more advanced/expensive versions will apply more optimization
to the simulation algorithm, which will make them run faster.

--
Best regards,
ulf at atmel dot com
The contents of this message is intended to be my private opinion and
may or may not be shared by my employer Atmel Sweden




Article: 33823
Subject: how to give timing constraint in an hierarchy des
From: Manjunathan <manjunathan_s1@yahoomail.com>
Date: Mon, 6 Aug 2001 03:04:27 -0700
Links: << >>  << T >>  << A >>
Hello everybody,

     i would like to know how to give timing constraint in an hierarchy design ?

    i have top level module as TOP.VHD.

    inside the toplevel i have component like BLOCK1,BLOCK2 and BLOCK3.

   how to give timing contraint INSIDE block1, block2 and block three when we are implementing the TOP level? 

   is it possible to give constraint through UCF file?

Thanks in Advance,

Regards,

Manjunath

Article: 33824
Subject: Re: May I connect two pins to the same net?
From: "Paul Teagle" <pteagle@bigpond.net.au>
Date: Mon, 06 Aug 2001 10:58:19 GMT
Links: << >>  << T >>  << A >>

"Lasse Langwadt Christensen" <langwadt@ieee.org> wrote in message
news:3B6E3318.A358A38D@ieee.org...
> Paul Teagle wrote:

<snip>
>
> why not just default to a tristate output, possibly with pullup,
> no floating inputs and no risk of driving something unintensionally
>
> -Lasse
> -- Lasse Langwadt Christensen,
> -- A Dane in Phoenix, Arizona

If you look at a schematic of the input/output pins, you will see that a
logic input is always connected to the physical pin; it can't be turned off.
If the pin is used as an input by the logic design, then the appropriate
switch in the device will be enabled and the input signal will drive
internal resources. The point here is that whatever input amplifier circuit
there is on the pins is always connected and active.

The circuit that can drive the pins as outputs can be disabled, or passed
thru a tri-state buffer. If the pin is used as an output exclusively, then
the output level will be enough to drive the corresponding input circuit
into saturation, ie, not floating. If you have nothing on that net on the
PCB, this input must be driven to prevent the inputs misbehaving.

One can run into problems if there are multiple devices that can drive out
onto a net, but sometimes *nothing* drives the net. Any FPGAs with
bidirectional pins can then react to this floating bus in the same way as a
floating net. This necessitates a pull down resistor somewhere on the net.

If I have space on a PCB, and not using some pins of a FPGA, I route the
spare pins to (eg) an array of 4 high value resistors, in a 0812 package,
the other end of which I tie to ground. If I don't use the pins, the s/w
defaults them to outputs, they drive a high value resistor, so virtually no
current is used. If I define them as inputs, they then have a pull down, and
everything is again OK. I can also access these spare lines for extra debugs
or extra signals during prototyping, and not take up too much real estate.
Using these lines as extra test connectors are also good value.

Having logic level "keepers" is much more elegant, though; saves boggins of
resistors cluttering things up.

--
Paul T.
CAE Inc.






Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search