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Messages from 34825

Article: 34825
Subject: Re: Selection of a suitable FPGA board
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 10 Sep 2001 12:47:50 +0100
Links: << >>  << T >>  << A >>


Ray Andraka wrote:

> The resistors work by limiting the input current when 5v is used.  This works fine for
> dedicated input.   For bidirectional I/O, you need that series resistor to limit
> currents when something else is driving the bus.  On the output side, the guaranteed
> high level output from the virtexE is marginal for connection to 5v TTL.  Driving a
> marginal high  through a resistor onto a loaded bus is asking for trouble.
>
> I am pretty sure you won't meet 5v PCI specs with a virtexE.  Perhaps Austin Franklin
> could add a bit to this discussion.  He's done far more with PCI using FPGAs  than most
> of the people on this newsgroup.
>

I've just done a few sums but I'm not a PCI guru or even a board one but here goes:

The basis is my case where we have 2 on-board PCI devices & 4 slots. Assumptions are:

- on board device pin capacitance = 10pF.
- Plug-in board capacitance = 15pF to allow for the socket pin.
- Max PCI bus trace length is 15''.
- Clock skew should be very low since we use separate clocks for each PCI device.

on this basis:

o A V-E PCI Tco(max) = 8.9 nsec.

o Now the real problem. The PCI is an unterminated bus and relies on the 1st reflection to
get an input to see a logic `1'. The spec defines the propagation delay as the time from
Tco(max) until all inputs have achieved Vth and not rung-back below Vih. For 5V signalling
Vth = 2.4V and Vih = 2.0 but the 3.3V Vth = 0.6Vcc =~ 1.98V. Therefore to guarantee a logic
high at the 5V cards with 3.3V source will need 2 reflections.

o Assuming trace propagation of 180ps/inch this gives, worst case, (3* 15) * .18 = 8.1nsec,
within the max Tprop spec.

Does this simple-minded analysis make sense ? or am I just trying to make myself feel good
?





Article: 34826
Subject: ModelSim Licensing SW Installation Opens Computer to Hacking?
From: "David Feustel" <dfeustel@mindspring.com>
Date: Mon, 10 Sep 2001 12:05:21 GMT
Links: << >>  << T >>  << A >>
I now wonder whether the Flexlm software used to license
Modelsim may open to internet hacking attacks any computer
on which the license is installed. (Check your ports)

Can anyone comment on this?

Thanks.



Article: 34827
Subject: Re: Spartan II JTAG configuration
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Mon, 10 Sep 2001 14:23:33 +0200
Links: << >>  << T >>  << A >>
Aare Tali schrieb:
> 
> Hi all,
> 
> I'm playing with XC2S200-PQ208, WebPack 3.3W8 and homemade parallel
> cable (74HC125 x 2). I ground PROGRAM pin, DONE goes low. I program
> the chip without verification, DONE goes high. Verify fails always in
> same place (frame 2000+). Docs (ds001_2.pdf, page 13) say that if DONE
> goes high device should be configured OK. Does all that mean that even
> if bitstream was received OK, the chip is fried and cannot be
> programmed?

I dont get your problem. When DONE goes high, everything should wor
fine.
 
> How important is to have 12 sets of 0.1/0.01uF caps, one on each
> power/ground pair? What else could go wrong? I have nothing else

Dont mess around with the decoupling. This is REALLY asking for trouble.
Even if you design runs only on 1khz clock frequency, the fast edges of
the FPGA can (and WILL) cause big current surges.
What kind of noard do you have ? Homemade or professional Prototype
board?

> connected to the chip, just JTAG, M0-M2 jumpers, PROGRAM pullup and
> DONE LED, and all power/ground pins. I/O is floating.

-- 
MFG
Falk



Article: 34828
Subject: Re: Level sensitive latches in Xilinx Virtex
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Mon, 10 Sep 2001 14:36:21 +0200
Links: << >>  << T >>  << A >>
Chris Softley schrieb:
> 

> machine generates that glitch - but this should not be a problem for a
> true level sensititive latch since the enable signal is always back on
> in plenty of time.

Hmm, we had a really bad error when using latches inside a 95288XL.
Since it has no latch capability, the latch was created using the
asynchronous SET and RESET inputs of a FF (data and clock input
grounded). The enable input of this "latch" was glitch sensitive !!!!!
because the data input and enable input were decoded into SET and RESET.

ARGGGGG. :-(

-- 
MFG
Falk



Article: 34829
Subject: Re: Actel FPGA glitches
From: Ray Andraka <ray@andraka.com>
Date: Mon, 10 Sep 2001 12:38:02 GMT
Links: << >>  << T >>  << A >>
NOt sure which it is.  If the outputs directly FROM flip flops and you have a glitch, there
is a signals integrity problem.  If you've got combinatorial logic between the flip-flop
and the output, then you are probably suffering from timing differences on the paths to the
output.  These will be dependent on your routing solution, temperature, voltage etc.  If
you need the outputs to be glitch free, then register the signals in the chip with no
further combinatorial stuff after the register.  Alternatively you can do a hazard analysis
on your combinatorial stuff, making sure you put the cover terms in to avoid glitches.
This can be difficult with FPGAs because the gates are not always what you think, and the
FPGA mappers generally do not keep cover terms in your logic.

Paul McCallion wrote:

> They are being driven by combinatorial logic, but are driving flip-flops.
>
>  Ray Andraka <ray@andraka.com> wrote in message news:<3B99677B.4D6262DE@andraka.com>...
> > What is driving the outputs?  Are they being driven directly by
> > flip-flops (as opposed to combinatorial logic or tristates)?
> >
> > Paul McCallion wrote:
> >
> > > Hi,
> > > Has anyone seen any glitch problems with Actel's A42MX series? I have
> > > seen 10nS glitches on outputs for several minutes after power on and
> > > with the application of freezer spray to the FPGA.
> > >
> > > Paul

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34830
Subject: Re: ModelSim Licensing SW Installation Opens Computer to Hacking?
From: Petter Gustad <newsmailcomp1@gustad.com>
Date: 10 Sep 2001 15:12:52 +0200
Links: << >>  << T >>  << A >>
"David Feustel" <dfeustel@mindspring.com> writes:

> I now wonder whether the Flexlm software used to license
> Modelsim may open to internet hacking attacks any computer
> on which the license is installed. (Check your ports)
> 
> Can anyone comment on this?

Make sure you deny access to the ports in your firewall setup. If not
somebody else could use your license.

Petter
-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 34831
Subject: Re: Clock division in Xilinx Vertex-E.
From: "Gyunseog Yang" <gsyang@lycos.co.kr>
Date: Mon, 10 Sep 2001 22:48:58 +0900
Links: << >>  << T >>  << A >>
I think it'd be a problem of tool version. I'm using 'Xilinx Foundation 3.1i
with service pack 2' and Synopsys 'FPGA Express(version 3.5)'

Because the both methods proposed by ulises and ray show no change.

When I used "INST clkdll_16 CLKDV_DIVIDE = 4.0;" in my UCF, there was no
error through synthesis and implementation procedure. But the timing
simulation result showed the default result (divided by 2).

In the case when I added the attributes "attribute CLKDV_DIVIDE: string;"
and "attribute CLKDV_DIVIDE of clkdll_16: label is "4.0"; " in my VHDL code,
there was also no error all through the procedure. but shows the result of
division by 2.
You can see the same tip at
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=
1&getPagePath=7419

Really would it be a problem of tool version?

I have installed the service pack 7, but the pack has some problem that stop
the implementation route at the first step. So I returned to service pack2.

regards.





Article: 34832
Subject: Xilinx Foundation Base(DS-ISE-XB2). Exactly what do you get?
From: Dave Colson <dscolson@rcn.com>
Date: Mon, 10 Sep 2001 09:50:15 -0400
Links: << >>  << T >>  << A >>
Hello,

I bought this software. But I am not sure exactly what came with it as
far as
synthesis tools.

I believe I have XST and FPGA Express. What about Synplify and Leonardo?

The web says that that comes with it, or does it.


Also, is FPGA Express "crippled" like ModelSim is i.e. intentionally
made slow. It
takes 30 mins. to do a synthesis on a Spartan II 150. XST only take s
couple of mins.

If this is so, why don't they say that this is the case?

Thank you for your help.

David Colson



Article: 34833
Subject: Re: Powering up a multi virtex fpga board
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 10 Sep 2001 08:07:18 -0700
Links: << >>  << T >>  << A >>


jfh,

There is no problem with reliability, or causing a failure.  2 amperes is a
normal operating current in many designs.

The maximum current is not very useful.  If you follow app note 158, and have
a current limited (NOT foldback, NOT trip, NOT power limited) power supply,
and the minimum amount of current is available (ie 2 ampere limit), then the
device is guaranteed to turn on, clean out, and configure at -40 C (2 amperes
is the industrial number for -40C).

If you don't need to supply more than the minimum, why would you want to?

500 mA up to a V600E, and 1 ampere up to a V2000E for commercial grade.

 http://www.xilinx.com/partinfo/ds022-3.pdf  (page 2 of 23)

If you must have a trip, foldback, or power limit, delay the onset of the
trip, foldback, or limit by 50 ms so that the device may initialize.  The
transient current lasts less than 5 ms, right around 1 Vdc for the Virtex E,
and around 1.3 V for Virtex on Vccint.

The time limits (2 ms to 50ms) is where we test every part.  If you power up
outside of this region, it is terra incognito (unknown land).  Longer than 50
ms you may have problems with power supply linearity (the devices want to see
the voltage generally increasing).  Shorter than 2 ms, and the minimum
current is larger.  Inside this region, and everything works.

The ramp is measured by placing a purely resistive load on your power supply
af a value consistent with the minimum current requirement.  The power should
rise from 0 Vdc to Vccint(min) is the time specified.  It should be generally
rising (no dips allowed).

Virtex II requires only that the leakage current be overcome (no transient
currents on Vccint).  We still recommend a current limited power supply, and
we still test every device in the 2 to 50 ms power on window.

 http://www.xilinx.com/partinfo/ds031-3.pdf  (page 4 of 30)

Any further questions on power on, email me at:  austin@xilinx.com

Austin


jfh wrote:

> Hi,
>
> I am working on a board involving several virtex type fpgas and
> I am worried about the min 2 amps needed for power-up of each fpga
> as well as the ramp of the core voltage. Has anyone some experience
> about powering up a multi fpga board with the power constraints ot the
> virtex (min 2A and a ramp of 2ms to 50ms from 0 to Vccint) ? What about
> the fact that the virtex datasheet doesn't mention anything about the max
> of the power consumption at power up ? Doees that mean that the number of
> amps if not limited can be destructive ?
> Thank you.
>
> J.F




Article: 34834
Subject: Re: To mix frequency with a FPGA
From: John_H <johnhandwork@mail.com>
Date: Mon, 10 Sep 2001 15:51:32 GMT
Links: << >>  << T >>  << A >>
There are two different "mixing" definitions used here.
Typical audio mixers are per Ray's suggestions resulting in two
frequencies, ft and fn.
Typical frequency mixers would produce two sidebands at ft +/- fn for
sinusoidal inputs.

To mix the two sqaure waves in the second sense (which may not be what you
want), you'd multiply rather than add per Ray's suggestion.  The rest
follows smoothly.

(+1)*(+1) = +1
(-1)*(+1) = -1
(+1)*(-1) = -1
(-1)*(-1) = +1

if (-1) is interpreted as zero and (+1) as one, you have a nice "chopped"
output.  You would get very similar results running two sqare waves into
commercial frequency mixers.


Ray Andraka wrote:

> mixing sound is done by adding.  In this case you need to add two 1 bit
> values and then limit the sum to 1 bit.
>
> olivier JEAN wrote:
>
> >  I must mix 2 square wave form to generate 1 square wave form with
> > fm = ft +/- fn.


Article: 34835
Subject: DSP design kit.
From: Roman Rumian <rumian@agh.edu.pl>
Date: Mon, 10 Sep 2001 18:25:23 +0200
Links: << >>  << T >>  << A >>
Hi,

can anybody recommend Spartan/Virtex FPGA based board which can be used for
audio(video?)  signal processing algorithms implementation/education ?

Thanks

Roman Rumian


Article: 34836
Subject: Data cache for fpga-cpu using Xilinx BlockRam
From: Steven Derrien <sderrien@irisa.fr>
Date: Mon, 10 Sep 2001 19:29:02 +0200
Links: << >>  << T >>  << A >>
Hello,

I was ondering if someone had ever tried to implement a data cache using 
blockrams on a Virtex/SpartanII like FPGAs. (for a soft-core cpu) ?

Any hints/HDL code/advices ?

Thanks,

Steven

Article: 34837
Subject: Re: Give me some information!
From: "Amirul Khan" <amirul_khan@yahoo.com>
Date: Mon, 10 Sep 2001 17:41:44 +0000 (UTC)
Links: << >>  << T >>  << A >>
"John" <jiangz00@mails.tsinghua.edu.cn> wrote in message
news:ee72386.-1@WebX.sUN8CHnE...

> hi 
> 
> Do have someeone have some fpga 
> 
> web or newsgroup or faq site 
> 
> address familiar with the 
> 
> comp.arch.fpga. pls tell me! 
> 
> thanks a lot


You can try:

http://www.amis.com/pdf/netrans.pdf
http://www.mindspring.com/~tcoonan/FAQ.html
http://www.amis.com/trans/brochure/index.html



-- 
Posted from cr131423-a.rchrd1.on.wave.home.com [24.42.104.24] 
via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 34838
Subject: Xilinx Virtex II Embedded Multiplier - Pipeline Register?
From: "pete dudley" <padudle@spinn.net>
Date: Mon, 10 Sep 2001 19:07:13 -0600
Links: << >>  << T >>  << A >>
Hello All,

Does anyone know whether there is really an internal pipeline register
inside the Virtex II embedded multiplier?

I have an application that is very multiplier intensive and I need to run at
125MHz. Without internal pipelining it is just about impossible to meet this
clock rate. I have been told there is a register inside those multipliers
but that they are not supported in the 3.1i tools. I received my 4.1i tools
today and tried to turn on the pipeline register by specifying maximum
pipelining in the core generator but the timing report still  indicates no
internal pipelining.

When I look at the multiplier blocks using FPGA Editor I can see that it has
a clock input. What's the story?

  Thanks,

--
Pete Dudley

Arroyo Grande Systems




Article: 34839
Subject: Re: Data cache for fpga-cpu using Xilinx BlockRam
From: "Rob Finch" <robfinch@sympatico.ca>
Date: Mon, 10 Sep 2001 23:26:47 -0400
Links: << >>  << T >>  << A >>
Yes, I'm attempting this. Actually, I'm implementing a unified instruction /
data cache using the dual-port feature of the block rams. One port for data
and one for code. Simultaneously accessed ports allows for a true Harvard
architecture for the cpu. A unified cache will give you a slightly lower
miss rate.
One of the tricky bits is reads are registered on the clock edge so the read
address has to be available before the clock edge, assuming you're going to
clock read data into the soft core on the next clock edge. On a read or
write miss you have to keep track of the address that was used so the cache
can be updated.
One problem with a cache is invalidating it, which is required on a process
switch or reset. There is no dedicated hardware to perform a block reset of
the valid bit, which means you must supply logic to do this (a counter +
mux). It would be nice if one of the block rams had a reset signal that
could set all the bits to zero.
It's tricky to get the cache to work fast and pipelining is tricky as well.
Consider that a ready signal to the cpu can't be valid until the result of
the tag match is ready, which is after the read is registered (clocked).
Also the cpu ready signal has to drive a lot of logic (high fanout). I have
about 6 or 7 logic levels between starting a cache access until data gets to
the cpu. There is also a lot of routing (routing is about 80% of time used).
Right now I'm stuck at about 40MHz through the cache, while the soft cpu
itself can run at 55MHz+. It might be possible to improve this with
additional pipelineing but it gets to be complex.
If you're using fast sram for memory, it might not be worth implementing a
cache as the sram will probably run upwards of 40MHz. (Unless you want to
implement the cache as an academic exercise).
A faster alternative to a cache would be to use the block ram as high speed
memory. Stuff all the data and code that you want available at high speed in
this memory. For a simple system you often know which routines and data are
time critical.
I'm developing using a SpartanII -5 and WebPack software.

Rob
http://www.birdcomputer.ca

"Steven Derrien" <sderrien@irisa.fr> wrote in message
news:3B9CF85E.1BE69072@irisa.fr...
> Hello,
>
> I was ondering if someone had ever tried to implement a data cache using
> blockrams on a Virtex/SpartanII like FPGAs. (for a soft-core cpu) ?
>
> Any hints/HDL code/advices ?
>
> Thanks,
>
> Steven



Article: 34840
Subject: Re: DSP design kit.
From: "Felix Bertram" <fbertram@gmx.net>
Date: Tue, 11 Sep 2001 08:53:06 +0200
Links: << >>  << T >>  << A >>
Roman,

when chosing an FPGA board, you should watch out for the following things:
* FPGA family. Is it a recent family? Generally speaking, outdated devices
are smaller, slower and more expensive than recent families. Look for
Spartan-II, Virtex-E or Virtex-II based boards.
* Capacity. Is the device large enough? A larger device helps during
development, as you can start proving your concept before optimizing. A
larger device helps during debugging as you can easily add some helper
circuits.
* Configuration. How is configuration performed? Does the board provide
Flash memory for non-volatile configuration?
* Download. How is the download performed? Is the download cable included?
Is it compatible to the Xilinx JTAG Programmer or Hardware Debugger?
* Expansion. How can the board be expanded? How many user I/Os are
available? How many clocks are available? Do the connectors share pins with
other peripherals? Do all connectors follow the same pinout?
* Software. Which software is required for development? Is the device
supported by the free Xilinx WebPACK software?

We just introduced our new Spartan-II based FPGA development system. It
provides an XC2S200-5 FPGA along with an XC18V02 Flash PROM for non-volatile
configuration. Download circuitry compatible to Xilinx Parallel Cable III is
included on the board. For easy expansion, the board offers four expansion
connectors with a total of 124 I/Os. The board ships with our Buttons &
Lights expansion board, which offers four 7-segment displays, eight push
buttons, a VGA connector and a USB receptacle. You can easily attach your
audio/ video circuitry to one of the remaining three connectors. We are
providing comprehensive application notes and tutorials with the board for
our customers in the educational and training field. Refer to the following
link for further information:
http://www.trenz-electronic.de/prod/proden6.htm

Best regards

Felix
_____
Dipl.-Ing. Felix Bertram
Trenz Electronic
Duenner Kirchweg 77
D - 32257 Buende
Tel.: +49 (0) 5223 49 39 755
Fax.: +49 (0) 5223 48 945
Mailto:f.bertram@trenz-electronic.de
http://www.trenz-electronic.de


"Roman Rumian" <rumian@agh.edu.pl> wrote in message
news:3B9CE973.6C3FC8C7@agh.edu.pl...
> Hi,
>
> can anybody recommend Spartan/Virtex FPGA based board which can be used
for
> audio(video?)  signal processing algorithms implementation/education ?
>
> Thanks
>
> Roman Rumian




Article: 34841
Subject: Spartan configuration
From: Edwin Pijpers <epij@oce.nl>
Date: Tue, 11 Sep 2001 08:55:34 +0200
Links: << >>  << T >>  << A >>


Is it possible to use a combination of Spartan and SpartanII devices in
the same serial configuration chain?? or do I get problems with the CRC
check.

Edwin Pijpers



Article: 34842
Subject: QPSK modulator with no multipliers
From: dottavio@ised.it (Antonio)
Date: 10 Sep 2001 23:59:36 -0700
Links: << >>  << T >>  << A >>
Good Morning
I'm designing a QPSK Modulator using an NCO, do you know where I can
found some documentation about a schema of it with no multiplier and
no NCO, someone tried to explain it to me, but until now I didn't
understand how it works and so I can't produce a valid schema for it.
Thanks in any case ...

Antonio D'Ottavio

Article: 34843
Subject: Re: Give me some information!
From: srinivasan_v@india.com (Srinivasan Venkataramanan)
Date: 11 Sep 2001 01:57:24 -0700
Links: << >>  << T >>  << A >>
Hi John,
    Try http://www.fpga-guru.com and the links therein.

Good Luck,
Srinivasan
John <jiangz00@mails.tsinghua.edu.cn> wrote in message news:<ee72386.-1@WebX.sUN8CHnE>...
> hi 
> 
> Do have someeone have some fpga 
> 
> web or newsgroup or faq site 
> 
> address familiar with the 
> 
> comp.arch.fpga. pls tell me! 
> 
> thanks a lot

Article: 34844
Subject: Timing constraints
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Tue, 11 Sep 2001 11:24:20 +0200
Links: << >>  << T >>  << A >>
Could someone quickly tell me exactly the operation of the clock to pad
timing constraint. Is this the minimum period that valid data should be at
the pad?

adrian




Article: 34845
Subject: Using falling and rising clock mistery.
From: Michal Rutka <rutka@lucent.com>
Date: 11 Sep 2001 13:04:46 +0200
Links: << >>  << T >>  << A >>
Hello all,

I've put such an example through Leonardo:

--- cut here ---
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY ala IS
  
  PORT (
    clk : IN  std_logic;
    o   : INOUT std_logic;
    o_n : INOUT std_logic);

END ENTITY ala;

ARCHITECTURE x OF ala IS

BEGIN  -- ARCHITECTURE x

  a: PROCESS (clk) IS
  BEGIN  -- PROCESS a
    IF clk'event AND clk = '1' THEN  -- rising clock edge
      o <= NOT o;
    END IF;
  END PROCESS a;

  b: PROCESS (clk) IS
  BEGIN  -- PROCESS a
    IF clk'event AND clk = '0' THEN  -- falling clock edge
      o_n <= NOT o;
    END IF;
  END PROCESS b;

END ARCHITECTURE x;
--- cut here ---

After synthesis I've noticed that this circuit have the same maximum
frequency as a circut in which process 'b' is triggered on the positive
edge. Is this flaw of Leonardo? How other synthesis tools handle it?

Regards,

Michal

Article: 34846
Subject: Re: Using falling and rising clock mistery.
From: Nicolas Matringe <nicolas.matringe@IPricot.com>
Date: Tue, 11 Sep 2001 13:33:04 +0200
Links: << >>  << T >>  << A >>
Michal Rutka a écrit :
> 
> Hello all,
[...]
> After synthesis I've noticed that this circuit have the same
> maximum frequency as a circut in which process 'b' is
> triggered on the positive edge. Is this flaw of Leonardo? How
> other synthesis tools handle it?

Hi
It depends on wher 'o' comes from. If it's just an input, ther's no
problem. If it's the output of another FF (clocked by the same clock
signal) then you should notice that the max frequency is half the
frequency you get when using the same edge for all FFs.

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 34847
Subject: FPGA Evaluation Board for image processing
From: Dave Moore <dave.m.moore@baesystems.com>
Date: Tue, 11 Sep 2001 13:15:44 +0100
Links: << >>  << T >>  << A >>
Hi All,
    I'm investigating the possible use of an FPGA based system for high
bandwidth realtime image processing. What I'm really after is an
evaluation board, that's capable of sampling SXGA (1280x1024) video at
60Hz, performing processing upon the captured image and splitting it out
through a video output (analogue or digital).

Any ideas of a possible source for such a card/board?.

Regards,
Dave



Article: 34848
Subject: Re: Data cache for fpga-cpu using Xilinx BlockRam
From: "Erik Widding" <widding@birger.com>
Date: Tue, 11 Sep 2001 12:17:18 GMT
Links: << >>  << T >>  << A >>
"Rob Finch" <robfinch@sympatico.ca> wrote in message
news:nsfn7.12796$2r.1150073@news20.bellglobal.com...
> Yes, I'm attempting this. Actually, I'm implementing a unified instruction
/
> data cache using the dual-port feature of the block rams. One port for
data
> and one for code. Simultaneously accessed ports allows for a true Harvard
> architecture for the cpu.
> [...]
> Right now I'm stuck at about 40MHz through the cache, while the soft cpu
> itself can run at 55MHz+. It might be possible to improve this with
> additional pipelineing but it gets to be complex.

If you are having a speed problem, you should probably be using two pual
port rams, one for instruction and one for data.  Then use the second port
on each of the memories as the interface to your external memory.  If you
have a cache miss, you will have to insert one wait state, so that you can
read the memory location that was just fetched.  Further, if every time you
have a miss, you fetch four or
eight data/instruction words, then it is likely that you will suffer fewer
misses.


Regards,
Erik Widding.

--
Birger Engineering, Inc.  --------------------------------  781.481.9233
38 Montvale Ave #260; Stoneham, MA 02180  -------  http://www.birger.com




Article: 34849
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