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Messages from 36950

Article: 36950
(removed)


Article: 36951
Subject: Re: Simple Logic State Analyser
From: c_oflynn@yahoo.com (Colin O'Flynn)
Date: 27 Nov 2001 04:50:13 -0800
Links: << >>  << T >>  << A >>
Hi,

  Do you want a timing Logic Anaylzer of a State logic anaylzer? A
timing logic anaylzer puts out the up and down pulses and tells you
when they happen, so it is like (in some distant ways) a 16 channel
scope. Or do you want just a state, which is a numerical list that
would look like this:

0000  -    010101011010
0001  -    111100011000
0010  -    101010101010

The first number is the clock cycle it is on, and the second number is
the digital inputs. The state logic anaylser would probably be fairly
simple, the timing logic anaylser might be harder. I'd imagine you
would need some sort of high-speed RAM, and the FPGA or CPLD would
basically address the RAM and dump the current data into it. Normally
logic anaylsers can run off of an internal clock (for the timing mode)
and an external clock (for the state mode). Once it fills the ram with
samples (say a few thousand) you could upload that data to a computer
or display it on an LCD.

   Just some thoughts :)

       -Colin



"Gunther May" <g.may@tu-bs.de> wrote in message news:<1006799757.761316@jupiter.schunter.etc.tu-bs.de>...
> Dear FPGA experts,
> 
> does someone have got a design for a simple logic analyser, for example a
> PC-controlled circuit?
> I am a student and I  would like to have such a device with at least 16
> inputs and 50MHz sample rate.
> In the internet, I found a nice design which was unfortunately based an
> older PLD which is not available any more.
> 
> Thank you very much!
> Gunther May

Article: 36952
Subject: Re: Device Support in Webpack
From: "Hicks" <hicksthe@egr.msu.edu>
Date: Tue, 27 Nov 2001 09:53:02 -0500
Links: << >>  << T >>  << A >>
LogiBlox and Coregen are very similar in what they are trying to accomplish.
LogiBlox is an older tool but in my opinion it is easier to use.  LogiBlox
tends to target older devices and simpler functional units.  Coregen targets
newer devices such as the Virtex2 and more complex functions (as well as the
simpler functions).  Instantiation of Coregen functions requires a little
more code that LogiBlox functions.  Probably no big deal either way _if_
what you want (FPGA and/or function) is supported.
Theron
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3C0318DB.2F80346A@yahoo.com...
> Theron Hicks wrote:
> >
> > I have used the webpack for the virtex2-40 series device.  Web pack does
not
> > support logiblox, coregen, and FPGA editor.  With those exceptions I
found
> > it to be quite usable.  The so-called modelsim limitation is not
entirely
> > true.  Modelsim is crippled in that as the simulations get more and more
> > lines of code the simulator gets bogged down.  It does not stop
entirely.  I
> > have used it to simulate a virtex2-40 with 95% of the chip utilized.
The
> > worst thing I can say about the modelsim is that the models for DCM's
and
> > other similar virtex2 specific devices are not simulatable at the
behavioral
> > or post-translate levels.  Thus to simulate a DCM one has to at least
map
> > the device to get a simulation result.  If you are just using standard
VHDL
> > then model-sim webpack works great.
>
>
> Theron,
>
> Thanks for the reply. This is useful info.
>
> I am aware of the ModelSim behavior. I did a project with it a little
> over a year ago and it got to be a real pain at 500 lines of code. It
> was not a gradual change in simulation time, but was about a 5x to 10x
> reduction in speed once you reached the 500 line limitation. This made
> it MUCH harder to get any real work done. Since it is not clearly
> indicated in the documentation, it snuck up behind me in the middle of
> this small project. Now I know better than to try to use any of the demo
> tools for a project, even when they look useful.
>
> IIRC, logiblox lets you instantiate complex elements like counters,
> adders, bus muxes and the like, right? I am not familiar with coregen. I
> will read up on it at the Xilinx web site. FPGA editor is important. I
> take it there are no replacement modules for Logiblox and FPGA editor in
> WebPack? It would be a pain to work without these functions.
>
>
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX



Article: 36953
Subject: Virtex Orcad Library
From: "Lou Ricci" <lricci@ma.ultranet.com>
Date: Tue, 27 Nov 2001 10:07:01 -0500
Links: << >>  << T >>  << A >>
Does anyone know where to find board level Orcad schematic symbols for the
Xilinx Virtex devices?

Thanks



Article: 36954
Subject: Re: wget of WebPack
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 27 Nov 2001 15:33:42 +0000
Links: << >>  << T >>  << A >>


Petter Gustad wrote:

> In case somebody is struggling with a not-internet-exporer-for-windows
> web browser (like myself, using Opera under Linux) to download WebPack
> - Here is how you can download it using wget:
>
> wget --http-user USER --http-passwd PASS http://www.xilinx.com/webpack/41wp2/WebPACK_41wp20_full_installer.exe
>
> Where USER is your Xilinx registered username and PASS is your
> selected password.
>

Great piece of info. Turns out that I've got wget on my BSDI system as well - the wonders of GNU part 947.

Question: How big is the full WebPACK installation ? Is it possible use wget to just filter out e.g. the JTAG
programmer stuff ?





Article: 36955
Subject: Re: Virtex Orcad Library
From: Keith R. Williams <krw@btv.ibm.com>
Date: Tue, 27 Nov 2001 10:52:28 -0500
Links: << >>  << T >>  << A >>
In article <9u09kj$c95$1@bob.news.rcn.net>, lricci@ma.ultranet.com 
says...
> Does anyone know where to find board level Orcad schematic symbols for the
> Xilinx Virtex devices?

I've found it better to create my own.  By creating a "heterogeneous" 
component I can separate the hundreds of pins into several smaller 
symbols and place them in the schematic where they make sense. For 
instance, I have one portion of a component that is the PowerPC bus, 
another for the SRAM, another for power/ground, etc.  I did the same 
thing for my PCI interface chip, even though PLX did have an OrCad 
symbol for it. This makes the schematics far easier to read than having 
one massive blob with hundreds of I/O none of which are in the "right" 
place.

----
  Keith 

Article: 36956
Subject: Alliance
From: "Fabio Bertone" <fabiobeta@libero.it>
Date: Tue, 27 Nov 2001 15:59:49 +0000 (UTC)
Links: << >>  << T >>  << A >>
I'm searching information about this software. I suppose I can use it to
simulate Xilinx FPGA.
How can I get it?(download?)

Thanks
Fabio


-- 
Posted from didlinux.polito.it [130.192.39.231] 
via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 36957
Subject: Xilinx JTAG programmer: how to generate SVF
From: vbica <vbica@qualcomm.com>
Date: Tue, 27 Nov 2001 08:17:15 -0800
Links: << >>  << T >>  << A >>
Hi, I downloaded the JTAG programmer software from Xilinx. I want to generate SVF files to program an XC18V00 series configuration PROM. I tell the programmer I want to generate SVF. Then I select the device, and run some operations on it. I do not have a cable or device actually connected to the PC; I just want to get the SVF file that would program it. It doesn't appear to work. I tried blank check and erase commands, and the SVF contains exactly the same code, regardless of which operation I try. The code that gets generated doesn't contain any of the expected instructions, either. Is this because I'm not actually hooked up to a device? Should this work?

TIA, Vito

Article: 36958
Subject: Re: FFT with Distributed Arithmatic
From: Tom Dillon <tdillon@dilloneng.com>
Date: Tue, 27 Nov 2001 16:21:55 GMT
Links: << >>  << T >>  << A >>
Our FFT IP Core uses the built in multipliers when available as it=20
greatly reduces the lut usage.=20

I wouldn't get hung up on the math part of the FFT as we found the data =

flow portion much more difficult, especially if you are trying to go=20=

fast.

How fast does your 8K point FFT need to be?

Regards,

Tom Dillon
Dillon Engineering, Inc.
www.dilloneng.com


>>>>>>>>>>>>>>>>>> Original Message <<<<<<<<<<<<<<<<<<

On 11/26/2001, 1:22:20 AM, Hananiel Sarella=20
<hsarella@honeybee.ececs.uc.edu> wrote regarding FFT with Distributed=20=

Arithmatic:


> Hello folks,
>            Im trying to implement large FFTs on Xilinx vertex II FPGAs=
. I=20
have a couple of questions.
> 1. There are multipliers on chip with 5ns delays. There  is a paper by=
=20
lez mintzer "large ffts on fpgas" which describes how to code one fft=20=

butterfly with DA tables. The pipeline delay in this case is less than t=
he=20
multiplier delay and there are more multiplies per stage delay.
>   Can some one tell me which is better?
> 2. Im writing synthesizeable structural VHDL code for the butterfly=20=

processor. Im having to write code for controlling this for say, 8192 po=
int=20
FFT. Is this the way people do it. Like say guys writing xilinx cores. O=
r=20
is there a better way you can suggest.

> Thanks a lot,
> Hananiel

Article: 36959
Subject: Re: SPI implementation details
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Tue, 27 Nov 2001 18:12:56 +0100
Links: << >>  << T >>  << A >>
"VR" <nospam@nonexistantdoooomain.com> schrieb im Newsbeitrag
news:9tv468$9u6$1@news.utdallas.edu...
> If I were to use implementation technique #2, does the possibility exist
> of my existing circuit being forced to run at a lower clock rate? Are
there
> other caveats to either design choice?

If you have a  free clock buffer, use the first solution. Its consumes less
power (althrough this is not a problem here I think) and less ressources. If
you run out of clock buffers, use the second solution.
--
MfG
Falk






Article: 36960
Subject: URL for ordering Xilinx ise webpack 4.1i cdrom
From: "David Feustel" <dfeustel@mindspring.com>
Date: Tue, 27 Nov 2001 17:35:10 GMT
Links: << >>  << T >>  << A >>
Is there a URL or phone number for ordering the
Xilinx ISE 4.1i webpack on cdrom?

Thanks.



Article: 36961
Subject: XST design flow for XC4010XL
From: "Bernd Scheuermann" <scheuermann@aifb.uni-karlsruhe.de>
Date: Tue, 27 Nov 2001 18:53:18 +0100
Links: << >>  << T >>  << A >>
Hi,

when creating a new project in Foundation ISE 4, I selected XC4010XL as
device and I searched for XST design flow for that chip. Unfortunately, only
EDIF and FPGA Express are offered, even though XST should be available
according to the help tool:

"For XST, you can synthesize the following families. Virtex, VirtexE,
Virtex2, Virtex2P, Spartan, Spartan2, Spartan2E, SpartanXL, XC4000E,
XC4000EX, XC4000L, XC4000XL, XC4000XLA, XC9500, XC9500XL, XC9500XV,
CoolRunner XPLA3, CoolRunner II."

Do you have an explanation for that?

Thanx a lot!!!



Bernd

--
* Bernd Scheuermann, Institute AIFB, University of Karlsruhe, Germany
* e-mail: scheuermann@aifb.uni-karlsruhe.de



Article: 36962
Subject: Re: Simple Logic State Analyser
From: "Gunther May" <g.may@tu-bs.de>
Date: Tue, 27 Nov 2001 19:01:04 +0100
Links: << >>  << T >>  << A >>
Hello,

I meant exactly what you call a timing logic analyser (I was not sure about
the English word, sorry).
It does not need to have an own display (this would probably get quickly
very expensive); the possibility to load it up to a PC would be sufficient.
Dos somebody have such a circuit/PLD software? You would make me a great
favour!

Thank you very much,
Gunther



Article: 36963
Subject: Re: Xilinx JTAG programmer: how to generate SVF
From: Mike <none@null.net>
Date: Tue, 27 Nov 2001 10:11:48 -0800
Links: << >>  << T >>  << A >>
Vito, 

You may want to check out the Xilinx support website (support.xilinx.com).  If you search on "SVF", the very first hit is titled "3.1i JTAG Programmer - How do I create an SVF file?"

HTH,

Mike

Article: 36964
Subject: Re: FFT with Distributed Arithmatic
From: Hananiel Sarella <hsarella@honeybee.ececs.uc.edu>
Date: 27 Nov 2001 13:27:48 -0500
Links: << >>  << T >>  << A >>

Thanks for the reply.                                      
Ray Andraka <ray@andraka.com> writes:

> Hananiel Sarella wrote:
> 
> > Hello folks,
> >            Im trying to implement large FFTs on Xilinx vertex II FPGAs. I have a couple of questions.
> > 1. There are multipliers on chip with 5ns delays.
> 
> Check the latest data sheets.  Those multipliers are not nearly that fast.
The virtex II 1.5 device(grade -6)  multiplier has a switching charecteristic of 5.6 ns on the pin 35. if im using less than than 18 bits for input I thought it will clock even faster. What am I missing?
> 
> > There  is a paper by lez mintzer "large ffts on fpgas" which describes how to code one fft butterfly with DA tables. The pipeline delay in this case is less than the multiplier delay and there are more multiplies per stage delay.
> 
> The DA approach is inherently serial, although it can be paralleled up to get a fully parallel implementation.  For the fully parallel case, the resource usage is close to parity with a design built from multipliers, and in most cases so is the latency/speed.  Where virtexII has the

  I do not understand "close to parity". its not just LUTs, we are (at least in virtex II) using up three different kinds of resources in each case-Multipliers, BlockRams and LUTs. Using DA, only the shift registers and scaling accumulator need LUTs. Whereas the normal multiplier implementation may not use any lookup and need more LUTs. And if I assume lookup is free, because of the amount of blockram available, isnt it more advantageous to use DA. How come if its only as fast, papers like "the fastest (fixed point)FFT in the west" (xilinx web site) claim DA helps acheive high FFT throughputs? Im a bit confused on this. 

> dedicated multipliers, you will use many less LUTs by using the multipliers...although that advantage is not as clear if you are using the multipliers and fabric at the highest possible speed.  There are other ways to skin the FFT cat too.  Even with the dedicated multipliers it may
> be advatageous to use alternative algorithms to reduce the hardware complexity.

Can you give some pointers/suggestions here? Where can i find such algorithms or give me a hint. 
 
> 
> >
> >   Can some one tell me which is better?
> > 2. Im writing synthesizeable structural VHDL code for the butterfly processor. Im having to write code for controlling this for say, 8192 point FFT. Is this the way people do it. Like say guys writing xilinx cores. Or is there a better way you can suggest.
> 
> I'm not sure what you are referring to as "code"  VHDL is code, as is microcode for a state machine.  The cores are structurally instantiated, although many have been translated to a java script.
> 
    I was thinking it was tedious to code the state machine in VHDL. I dont have a lot of experience with big VHDL designs. And I was talking about core designers not users.
thanks again.     
> >
> >
> > Thanks a lot,
> > Hananiel
> 
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
> 
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
> 
> 

-- 
------------------------------------------------/--oOOo-------------
Hananiel Sarella,                               \__/_niversity
Research Assistant,                               /       
Advanced computing Lab.                           \__/incinnati


Article: 36965
Subject: Re: Creating a jitter free clock
From: John_H <johnhandwork@mail.com>
Date: Tue, 27 Nov 2001 18:39:01 GMT
Links: << >>  << T >>  << A >>
A 1 part per billion device is asking a huge amount from a timebase.  The questions that need to be answered to determine what you really *need* includes:
  Do you need the timing edges to be that hyper-clean or do you derive information from the clock?
  Specifically, if a very stable time pulse were available can you use a "correction" to a slighly sloppier timebase?
  Do you really need the accuracy of 1ppb or is the issue more one of precision (resolution/repeatability)?

Allan variance covers the lower frequency drift aspects of oscillators.  You can get $100 ovenized oscillators that have good characteristics but provide the Allan variance numbers.  (You might want to read up on high precision stuff like what you can find at
http://www.allanstime.com/AllanVariance/ ).

You might check out the oscillator manufacturer www.mti-milliren.com since these folks have produced more cost effective high precision solutions than some folks I've seen.  A white paper 2-3 years ago had some very high precision numbers that might be more along the
lines of what you need.

The overall theme:  to have a very high precision you need some absolute reference, either local (1ppb oscillator) or distributed (GPS or similar distributed timebase).  If you have access to a reference you can often make corrections in your measurements.

There are techniques that are used in measurement that use identical devices to measure each other allowing an assumption that the measured error values are off by 3dB.  Phase noise measurements are one application of the self-testing method.  Don't overlook other
possible solutions in the pursuit of extreme precision.

- John_H


Adrian wrote:

> Hi,
>
> I'm using a programmable clock which has an accuracy of 1 part per million. i.e. I can set f = 1.000000 MHz. However, I need a clock with a resolution of 1 part per billion ie. f can be set to 1.000000000 MHz and does not vary over a period of at least 5 minutes.
>
> Is there anything I can add to my FPGA design to achieve this? Clock will be running at approximately 32MHz.
>
> thanks
> adrian


Article: 36966
Subject: Re: FFT with Distributed Arithmatic
From: Hananiel Sarella <hsarella@honeybee.ececs.uc.edu>
Date: 27 Nov 2001 13:41:39 -0500
Links: << >>  << T >>  << A >>
Tom Dillon <tdillon@dilloneng.com> writes:

  Im trying to write a general benchmark for Reconfigurable environments. ACS honeywell are the latest available and they have a behavioural code. Actually I need to get it as fast as possible. But my main constraint is FFT is a scalability benchmark. I should be able to spread them over multiple chips and the design needs to be scalable. I want to the biggest possible thing in three chips virtexII 3000 chips asap. I guess I have no clue what im trying to do here. 
thanks,
hananiel 

> Our FFT IP Core uses the built in multipliers when available as it=20
> greatly reduces the lut usage.=20
> 
> I wouldn't get hung up on the math part of the FFT as we found the data =
> 
> flow portion much more difficult, especially if you are trying to go=20=
> 
> fast.
> 
> How fast does your 8K point FFT need to be?
> 
> Regards,
> 
> Tom Dillon
> Dillon Engineering, Inc.
> www.dilloneng.com
> 
> 
> >>>>>>>>>>>>>>>>>> Original Message <<<<<<<<<<<<<<<<<<
> 
> On 11/26/2001, 1:22:20 AM, Hananiel Sarella=20
> <hsarella@honeybee.ececs.uc.edu> wrote regarding FFT with Distributed=20=
> 
> Arithmatic:
> 
> 
> > Hello folks,
> >            Im trying to implement large FFTs on Xilinx vertex II FPGAs=
> . I=20
> have a couple of questions.
> > 1. There are multipliers on chip with 5ns delays. There  is a paper by=
> =20
> lez mintzer "large ffts on fpgas" which describes how to code one fft=20=
> 
> butterfly with DA tables. The pipeline delay in this case is less than t=
> he=20
> multiplier delay and there are more multiplies per stage delay.
> >   Can some one tell me which is better?
> > 2. Im writing synthesizeable structural VHDL code for the butterfly=20=
> 
> processor. Im having to write code for controlling this for say, 8192 po=
> int=20
> FFT. Is this the way people do it. Like say guys writing xilinx cores. O=
> r=20
> is there a better way you can suggest.
> 
> > Thanks a lot,
> > Hananiel


Article: 36967
Subject: Re: Some question on Synplify
From: sunny <sunrise@sunrise.at>
Date: Tue, 27 Nov 2001 10:54:34 -0800
Links: << >>  << T >>  << A >>
Instead of generating a clock you could generate a clock enable. Thatīs very easy. You only would need two flops, one inverter and one and gate. The enable signals generated by using that circuit has a pulse length of exactly one clock cycle. Just try it

Article: 36968
Subject: Re: Creating a jitter free clock
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Tue, 27 Nov 2001 11:02:15 -0800
Links: << >>  << T >>  << A >>
I remember vaguely that the color subcarrier frequency driven by active network television is extremely accurate, even better than 1 part per billion. This was before the days of GPS, which may be even better. Just a thought.
But jitter is the real devil...

Peter Alfke


>


Article: 36969
Subject: Re: Creating a jitter free clock
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 27 Nov 2001 11:05:44 -0800
Links: << >>  << T >>  << A >>
Just as a comment,

For the best courses on Frequency and Time, go to the NIST website in Boulder, Colorado.

 http://www.boulder.nist.gov/blconf.htm

They have seminars and courses offered that offer the "degree" of 'Father Time.'

They explain all about Allan variances, and the other newer variances used more commonly by the telecoms industry.

They cover the cyrstal oscillators, the resonators, the rubidium passive cells, and the cesium active resonators.

The also cover GPS, and how it is derived, and how time and frequency can be transported as a reference.

What you will find is there is nothing that hasn't already been researched hundreds of times, and stability, absolute accuracy, and long term drift are all mutually exclusive (there is no oscillator with all three attributes).

Since you can not average or integrate frequencies to derive a better frequency (physically impossible), all you can do is average time bases (dividing down the frequencies), to get accurate time marks for measurements.

Measurements of weeks or days are required for 1E-10 accuracy, and timebases to do this must be at least 1E-12, which means you have two cesiums, and a GPS steered Rubidium, or some combination of sources that are good for absolute accuracy, and some that are good for
stability.

(From someone who designed and built Stratum 1, 2, 3E, systems for SONET/SDH for 15 years.)

Austin


John_H wrote:

> A 1 part per billion device is asking a huge amount from a timebase.  The questions that need to be answered to determine what you really *need* includes:
>   Do you need the timing edges to be that hyper-clean or do you derive information from the clock?
>   Specifically, if a very stable time pulse were available can you use a "correction" to a slighly sloppier timebase?
>   Do you really need the accuracy of 1ppb or is the issue more one of precision (resolution/repeatability)?
>
> Allan variance covers the lower frequency drift aspects of oscillators.  You can get $100 ovenized oscillators that have good characteristics but provide the Allan variance numbers.  (You might want to read up on high precision stuff like what you can find at
> http://www.allanstime.com/AllanVariance/ ).
>
> You might check out the oscillator manufacturer www.mti-milliren.com since these folks have produced more cost effective high precision solutions than some folks I've seen.  A white paper 2-3 years ago had some very high precision numbers that might be more along the
> lines of what you need.
>
> The overall theme:  to have a very high precision you need some absolute reference, either local (1ppb oscillator) or distributed (GPS or similar distributed timebase).  If you have access to a reference you can often make corrections in your measurements.
>
> There are techniques that are used in measurement that use identical devices to measure each other allowing an assumption that the measured error values are off by 3dB.  Phase noise measurements are one application of the self-testing method.  Don't overlook other
> possible solutions in the pursuit of extreme precision.
>
> - John_H
>
> Adrian wrote:
>
> > Hi,
> >
> > I'm using a programmable clock which has an accuracy of 1 part per million. i.e. I can set f = 1.000000 MHz. However, I need a clock with a resolution of 1 part per billion ie. f can be set to 1.000000000 MHz and does not vary over a period of at least 5 minutes.
> >
> > Is there anything I can add to my FPGA design to achieve this? Clock will be running at approximately 32MHz.
> >
> > thanks
> > adrian


Article: 36970
Subject: Re: Creating a jitter free clock
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 27 Nov 2001 11:14:22 -0800
Links: << >>  << T >>  << A >>
Peter,

The Color Burst frequency is supposed to be synchronized to a national standard, but it never was in the US.  It is synchronized in Europe.

Thus, here in the US, we have a "free" good reference, that isn't traceable to anything.

It has been replaced world - wide with GPS receivers that correct and update other oscillators.

Most CMDA cellular basestations use GPS for their timebase.

GPS with slective availability off (its present state) is +/- 10 nS at any given moment, but averaged over time is better than ~1E-13, or never worse than 100 nS from UTC, ever.

 http://www.laruscorp.com/models_5850-2000.htm

The typical GPS steered ovenized quartz oscillator goes for $5,000 to $10,000.  Oh, and you need to place the anntenna where it can see the sky.

Austin

Peter Alfke wrote:

> I remember vaguely that the color subcarrier frequency driven by active network television is extremely accurate, even better than 1 part per billion. This was before the days of GPS, which may be even better. Just a thought.
> But jitter is the real devil...
>
> Peter Alfke
>
> >


Article: 36971
Subject: Got enough mebibytes of RAM ?
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Tue, 27 Nov 2001 11:54:17 -0800
Links: << >>  << T >>  << A >>

--------------18100D926F273F6F69A7CDE8
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353"
Content-Transfer-Encoding: 7bit

We all need a laugh now and then.
This one is good for a serious smile, whatever that is.

http://physics.nist.gov/cuu/Units/binary.html

Peter Alfke

--------------18100D926F273F6F69A7CDE8
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
We all need a laugh now and then.
<br>This one is good for a serious smile, whatever that is.
<p><u><A HREF="http://physics.nist.gov/cuu/Units/binary.html">http://physics.nist.gov/cuu/Units/binary.html</A></u>
<p>Peter Alfke</html>

--------------18100D926F273F6F69A7CDE8--


Article: 36972
Subject: DSP on FPGA Opinions Needed->Earn $100
From: Dave Millman <dsp@tactics.com>
Date: Tue, 27 Nov 2001 12:26:04 -0800
Links: << >>  << T >>  << A >>
(This is the second and final posting for this research project. Thank
you to the engineers who have already responded, but we need more
opinions!)

DSP on FPGA Opinions Needed->Earn $100

An EDA company is researching user's requirements for implementing DSP
on FPGAs. If you have completed a signal processing design on FPGAs, or
are now working on one, we'll pay you $100 to participate in a 30-minute

telephone interview.

During the interview, we will ask you to discuss:

   * How many DSP on FPGA designs you have done
   * Why you chose to use FPGAs instead of standard DSP chips
   * What tools are you using and how well they are working
   * How current tools could be improved

If you are interested, send an email to dsp@tactics.com with this
information:

   * Your name
   * The phone number to reach you
   * The best time to reach you at that phone number

If you have any questions, please feel free to send them to the same
address. PLEASE DO NOT RESPOND ON THE NEWS GROUP!

In return for your time and opinions, we will send $100 to all
participants who complete the interview. We are an engineering market
research firm that has been retained by an EDA company to help them
develop new tools. Your opinions will be delivered straight to the team
developing the new product. In the end, the result will be better tools
that work the way you want them to.

Thank you for your time.


Article: 36973
Subject: Re: Creating a jitter free clock
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Wed, 28 Nov 2001 09:32:13 +1300
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
> 
> Peter,
> 
> The Color Burst frequency is supposed to be synchronized to a national standard, but it 
> never was in the US.  It is synchronized in Europe.

It may be that the PAL system allows better overall performance.

> 
> Thus, here in the US, we have a "free" good reference, that isn't traceable to anything.
> 
> It has been replaced world - wide with GPS receivers that correct and update other oscillators.
> 
> Most CMDA cellular basestations use GPS for their timebase.
> 
> GPS with slective availability off (its present state) is +/- 10 nS at any given moment, 
> but averaged over time is better than ~1E-13, or never worse than 100 nS from UTC, ever.

In a 'normal' GPS system, how accessible is this frequency locked
reference ?

> 
>  http://www.laruscorp.com/models_5850-2000.htm
> 
> The typical GPS steered ovenized quartz oscillator goes for $5,000 to $10,000.  Oh, and you need to place the anntenna where it can see the sky.

 The original post asked for 10E-9, over 5 minutes. 
 However, it did not specify tolerable phase jitter, or if this need was
an 
absolute precision, or a relative precision.

 Take a look at the top end frequency counters, from Philips/Fluke/HP,
and check their
specs of stability over time and temperature.
 That will give numbers for high class XTAL oscillators.
IIRC the Philips FreqCtr I have here, is good to 10E-9 over short times.

 Colour burst freq is accessible, and provides a very good high
frequency 
( Typ 8.8867MHz in PAL systems ) that can be used to check a local
timebase against.

 Put a Freq Counter in the corner of the FPGA, and you can check your
local clock
stability over around a second, to one part in 10E9.

-jg

Article: 36974
Subject: Re: Creating a jitter free clock
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 27 Nov 2001 13:23:59 -0800
Links: << >>  << T >>  << A >>
Jim,

In your typical GPS receiver, there are no accessible oscillators, or time base references.  Some have an external 1 pps time tick.  This actually can
be used to measure a ~50 MHz 'naked rubidium' cell over thousands of seconds to get 1E-10 or better.

You then can use a FPGA based DDFS to get the output frequency you want (ie 10 MHz, or 1 MHz).  You "steer" or correct the DDFS, you NEVER adjust the
oscillator.  Adjusting ANY oscillator destroys its short term stability, and introduces massive errors!

The problem is also the commercial receiver has too much jitter to be useful.

Motorola sells OEM GPS receivers specifically designed for time and frequency use, and they are what I used.  Another manufacturer that I liked better
was Odetics.

Austin

Jim Granville wrote:

> Austin Lesea wrote:
> >
> > Peter,
> >
> > The Color Burst frequency is supposed to be synchronized to a national standard, but it
> > never was in the US.  It is synchronized in Europe.
>
> It may be that the PAL system allows better overall performance.
>
> >
> > Thus, here in the US, we have a "free" good reference, that isn't traceable to anything.
> >
> > It has been replaced world - wide with GPS receivers that correct and update other oscillators.
> >
> > Most CMDA cellular basestations use GPS for their timebase.
> >
> > GPS with slective availability off (its present state) is +/- 10 nS at any given moment,
> > but averaged over time is better than ~1E-13, or never worse than 100 nS from UTC, ever.
>
> In a 'normal' GPS system, how accessible is this frequency locked
> reference ?
>
> >
> >  http://www.laruscorp.com/models_5850-2000.htm
> >
> > The typical GPS steered ovenized quartz oscillator goes for $5,000 to $10,000.  Oh, and you need to place the anntenna where it can see the sky.
>
>  The original post asked for 10E-9, over 5 minutes.
>  However, it did not specify tolerable phase jitter, or if this need was
> an
> absolute precision, or a relative precision.
>
>  Take a look at the top end frequency counters, from Philips/Fluke/HP,
> and check their
> specs of stability over time and temperature.
>  That will give numbers for high class XTAL oscillators.
> IIRC the Philips FreqCtr I have here, is good to 10E-9 over short times.
>
>  Colour burst freq is accessible, and provides a very good high
> frequency
> ( Typ 8.8867MHz in PAL systems ) that can be used to check a local
> timebase against.
>
>  Put a Freq Counter in the corner of the FPGA, and you can check your
> local clock
> stability over around a second, to one part in 10E9.
>
> -jg




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