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Messages from 37275

Article: 37275
Subject: ISA bus adr decoder with GAL16V8D
From: miemchan@yahoo.com.au (Miem Chan)
Date: 5 Dec 2001 22:39:19 -0800
Links: << >>  << T >>  << A >>
I'm new to GAL and CUPL.
I want to build an ISA bus adr decoder with GAL16V8D to say decode
adr. 0x1B0 on the PC's I/O space.

1) Would some one show me how to do it?
2) How to program GAL16V8D ?
3) Is it possible to read the configuration from a programmed GAL16V8D
?
4) Thanks.

Miem Chan
miemchan@yahoo.com.au

Article: 37276
Subject: IEEE 1149.1 boundary scan and HIGHZ opcode
From: "AH" <akha@attbi.com>
Date: Thu, 06 Dec 2001 07:09:51 GMT
Links: << >>  << T >>  << A >>
Hello,

Does anyone know if the optional HIGHZ instruction will put the TMS pin into
high-z of the TAP?  Also,  when the JTAG controller is in reset state,  is
the TMS pin in high-z?

Thanks,

Andy




Article: 37277
Subject: Re: IEEE 1149.1 boundary scan and HIGHZ opcode
From: "AH" <akha@attbi.com>
Date: Thu, 06 Dec 2001 07:17:21 GMT
Links: << >>  << T >>  << A >>
My bad,  I meant TDO pin put into reset.  I feel even dumber now..

Andy


"AH" <akha@attbi.com> wrote in message
news:3REP7.2011$Yy.252425@rwcrnsc53...
> Hello,
>
> Does anyone know if the optional HIGHZ instruction will put the TMS pin
into
> high-z of the TAP?  Also,  when the JTAG controller is in reset state,  is
> the TMS pin in high-z?
>
> Thanks,
>
> Andy
>
>
>



Article: 37278
Subject: ISP via JTAG
From: "AH" <akha@attbi.com>
Date: Thu, 06 Dec 2001 08:32:09 GMT
Links: << >>  << T >>  << A >>
Hi,

I have another sort of silly question.  Say I have a Xilinx XC95xxXL already
mounted on a pcb.  Is it possible to program it via the JTAG interface to
disable it's JTAG pins?  Would that mean the pins are disabled forever? (or
at least until I remove it from the pcb and reprogram?)

Thanks,
Andy



Article: 37279
Subject: $EXPORT=NO(exp_EDIF) for CoreGen Component, schematic entry
From: ekkho@students.wisc.edu (enny)
Date: 6 Dec 2001 01:17:52 -0800
Links: << >>  << T >>  << A >>
Hi, 

I am generating CoreGen Direct Digital Synthesis and enter them for
schematic flow. When I implement the design using Implementation tool
of Foundation 3.1 i, exp_EDIF reported that
  Macro 'DDS' not exported, property $EXPORT=NO
  Macro 'NDDS' not exported, property $EXPORT=NO

After that, I tried to change the property of the macro symbol in the
schematic, and actually made the $EXPORT = YES, however the
implementation which I run again, still give the same result.

Does anyone has idea on how to fix this problem. Thanks a lot in
advance

enny

Article: 37280
Subject: Re: Triscend E5 vs Atmel FPSLIC
From: "Ulf Samuelsson" <ulf@atmel.REMOVE.com>
Date: Thu, 6 Dec 2001 10:32:16 +0100
Links: << >>  << T >>  << A >>
They are really focusing on different markets.
The FPSLIC is focusing on single chip solutions with
embedded memory and the Triscend is focusing
on larger multichip applications.

--
Best Regards
Ulf at atmel dot com
These comments are intended to be my own opinion and they
may, or may not be shared by my employer, Atmel Sweden.

"Boris" <byxiao@public.cz.js.cn> skrev i meddelandet
news:9uian5$qin$1@mail.cn99.com...
> Have anyone use the Triscend E5 or Atmel FPSLIC in their design?
> Which one is better choice?
> Thank you for your advice.
>
> Sincerely yours,
> Xiao
>



Article: 37281
Subject: Has anyone successfully used opencores PCI?
From: "Sul Weh" <sweather1999@yahoo.com>
Date: Thu, 06 Dec 2001 09:37:31 GMT
Links: << >>  << T >>  << A >>
Also, why would one choose to use opencores instead of the Xilinx logicore
PCI?

thanks

SW



Article: 37282
Subject: Timing Constraints Spartan, divided Clk
From: tobias@scharnberg-online.com (Tobias)
Date: 6 Dec 2001 01:53:56 -0800
Links: << >>  << T >>  << A >>
Hello!
I have a problem with Timing Constraints. This is the first time I am
working with them and I am not quite sure what I am doing.. I am
dividing my CLK of 33MHz by two using the CLK divider from Xilinx
Foundation LogiBLOX generator. Then I use a secondary CLK buffer to
distribute the CLK.
I would like to use Constraints on the Ports in the Constraint editor,
but I can only choose my 33 MHz CLK as a relative to CLK Pad net. I
cannot choose my "new" divided CLK and therefore I get a warning that
my timing constraints are ignored. How can I change this?!

Thanks for reading and your Help! 
Tobias

Article: 37283
Subject: Re: Installing ISE 4.1i
From: Falser Klaus <kfalser@IHATESPAMdurst.it>
Date: Thu, 6 Dec 2001 11:30:28 +0100
Links: << >>  << T >>  << A >>
In article <9uis0f$89h$1@news.rz.uni-karlsruhe.de>, 
scheuermann@aifb.uni-karlsruhe.de says...
> Hi,
>...
> 
> 1) The FLEX license mechanism doesn't seem to work properly. I received the
> license file by e-mail, installed it to a directory on the server machine
> and set the environment variable. Starting the FLEX license manager on a
> client, entering setup parameters, pressing control-start, everything is
> fine. But pressing Control-Stop, a message appears "Server Stop Failed".
> Pressing Control-Status, another message appears "Unable to obtain status
> due to missing lmgr325c.dll"; pressing Advanced-Diagnostics, again a message
> "Unable to perform diagnostics due to missing lmgr325a.dll" (same messages
> are shown on the server machine). I searched for these 2 dll-files on both
> machines, server and client: no success. What can I do to fix that problem?
> 
>
You need to start the Demon (using the control panel) only on the Server 
machine.
On your client machine only the LM_LICENSE_FILE environment variable 
must be set correctly. 

LM_LICENSE_FILE=2200@<name of the server machine> 

Hope this helps.
-- 
Klaus Falser
Durst Phototechnik AG
kfalser@IHATESPAMEdurst.it

Article: 37284
Subject: Call for papers on CCMs for high-performance computing
From: joaoferreira@my-deja.com (=?ISO-8859-1?Q?Jo=E3o_Ferreira?=)
Date: 6 Dec 2001 04:57:38 -0800
Links: << >>  << T >>  << A >>
Please find below the announcement of the 5th International Meeting on
High Performance Computing for Computational Science, that will be held in
Porto, Portugal in June 2002. The organizers would like to encourage the
submission of papers on the use of CCMs for high-performance scientific computing.

*******************************************************************************
                            VECPAR'2002

                   5th International Meeting on 
          High Performance Computing for Computational Science

                          June 26-28, 2002
            Faculdade de Engenharia da Universidade do Porto,
                               Porto
                              Portugal

                   http://www.fe.up.pt/vecpar2002


                  Call for papers for a session on


         Reconfigurable Custom Computing for Scientific Applications

********************************************************************************

Dear colleague,


VECPAR'2002 will be the fifth edition of a series of conferences, organised 
since 1993 by the Faculty of Engineering of the University of Porto. The 
conference was previously entitled Vector and Parallel Processing, and its 
renaming reflects best its nature, aimed at an enlarged scientific community 
made up of mathematicians, physicists, engineers, i.e. all branches of science 
reverting to computer simulations for analysis of complex systems and phenomena, 
computational science in short.

The increasing computing power offered by custom computing machines implemented 
with current million-gate reconfigurable devices, provides a competitive 
alternative to software applications running on conventional high-performance 
computers. For this session we would like to invite you to submit papers that 
show the use of custom computing machines as real alternatives to conventional 
computing platforms in the various fields of scientific computing. 

For information on how to submit a paper, please visit the conference web site 
at http://www.fe.up.pt/vecpar2002

Article: 37285
Subject: Re: Where can I find the implemention of block float multiplier?
From: Ray Andraka <ray@andraka.com>
Date: Thu, 06 Dec 2001 13:02:01 GMT
Links: << >>  << T >>  << A >>
You need to understand what block floating  point means.  A block floating
point  means that all the points of a set share a common exponent.  This is
commonly done in FFTs because the FFT can have a fairly high dynamic range,
especially with longer transforms.  It is a compromise between fixed point
and floating point implementations (the hardware cost is little more than
the fixed point case, but it allows a much larger dynamic range)

Usually what is done, is the computations for a pass through the FFT
hardware are done in fixed point with the precision increased as  needed to
handle the growth, then between passes, the data is all shifted by the same
amount so that there are no redundant sign bits on the sample with the
largest magnitude.  The amount of shift is saved as the exponent for that
pass.  This way the data at the input for each pass is set up for the
maximum dynamic range with a fixed width hardware path. The exponents from
each pass are summed to obtain the block exponent for the FFT.

deerlux wrote:

> I want to implement FFT in FPGA with block float dataword format.Who can
> tell me where there is introduction of block float calculator?

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 37286
Subject: Re: Timing Constraints Spartan, divided Clk
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Thu, 06 Dec 2001 15:27:31 +0200
Links: << >>  << T >>  << A >>
Tobias wrote:
> 
> Hello!
> I have a problem with Timing Constraints. This is the first time I am
> working with them and I am not quite sure what I am doing.. I am
> dividing my CLK of 33MHz by two using the CLK divider from Xilinx
> Foundation LogiBLOX generator. Then I use a secondary CLK buffer to
> distribute the CLK.
> I would like to use Constraints on the Ports in the Constraint editor,
> but I can only choose my 33 MHz CLK as a relative to CLK Pad net. I
> cannot choose my "new" divided CLK and therefore I get a warning that
> my timing constraints are ignored. How can I change this?!

  What I can recommend right now is, to write the
  constraints directly to UCF file, rather than
  using Constraints Editor. Do you have this chance?
  In this case, you have the complete freedom
  of constraining what you want.

> Thanks for reading and your Help!
> Tobias

  Utku

Article: 37287
Subject: Re: quartus post simulation setup problem
From: nchrysos@ics.forth.gr (Nick)
Date: 6 Dec 2001 05:33:58 -0800
Links: << >>  << T >>  << A >>
Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3C0EB1F6.160D02BC@flukenetworks.com>...
> Brian Philofsky wrote:
> 
> > I don't know.  I would be a little more cautious.  Is this path crossing clock
> > domains?  
> 
> I was assuming a synchronous design.
> He said it was an internal register.



It is an internal register.


 
> > Is clock skew being accounted for? Not sure exactly how Quartus
> > accounts for this but is especially important if you are not using global clock
> > resources (i.e. using more than 4 clocks).  
> 
> Yes, in either case.
> 

I am using 2 clocks. Both are global, and this path actual uses both
clocks.
The second clock is derived from the first ( twice period)
always @(posedge clk) s_clk = ~s_clk;

> > Are you (Nick) clocking on both edges of the clock?  
> 
> I hope not.
> 

Yes i do in one circumstance, is this so bad...? What i wanted to do
is to provide a state like the following
clk  101
s_clk


> > Does any part of the path originate from an I/O?  Is the path to a clock
> > enable?  Seems I have heard about problems with Quartus where in certain
> > circumstances would not properly report timing to register clock enables.
> 
> Reference please?
> 
> > I am not saying there is necessarily a problem here but I also would not blindly
> > disregard this as it may manifest itself as an intermittent problem later.  If it
> > was me, I would want to get to the bottom of the problem.  If you were targeting
> > Xilinx, I could give you some suggestions to help debug this issue but...
> 
> Is this a sales call?
> 
>            --Mike Treseler

I think the problem is actually there when i download on the device, i
see strange thinks on the logical analyzer, much like those i see on
the post compile simulation

Article: 37288
Subject: Re: Where can I find the implemention of block float multiplier?
From: Tom Dillon <tdillon@dilloneng.com>
Date: Thu, 06 Dec 2001 15:15:11 GMT
Links: << >>  << T >>  << A >>
Check out the most configurable and fastest FFT around? It can handle an=
y=20
width fixed or floating point data. If all you want it block floating=20=

point, which is really scaled fixed point, it can handle that also.

http://www.dilloneng.com/ipcores/fft/index.html

Tom Dillon
Dillon Engineering, Inc.
www.dilloneng.com


>>>>>>>>>>>>>>>>>> Original Message <<<<<<<<<<<<<<<<<<

On 12/5/2001, 10:10:54 PM, "deerlux" <deerlux@hotmail.com> wrote regardi=
ng=20
Where can I find the implemention of block float multiplier?:


> I want to implement FFT in FPGA with block float dataword format.Who c=
an
> tell me where there is introduction of block float calculator?

Article: 37289
Subject: using UNIX Environment variables in "ncvlog -file option" - Help!
From: "Srinivasan Venkataramanan" <srinivasan@siliconsystems.co.in>
Date: Thu, 6 Dec 2001 21:11:29 +0530
Links: << >>  << T >>  << A >>
Hi,
  I want to use

ncvlog -file ncvlog.args

where my ncvlog.args file contains:

// Options
-messages

// Files to be compiled
$ROOT/src/file1.v

// End

Now the problem is for some reason ncvlog doesn't like usage of UNIX
Environment variables in this context (it says no such file and
exits), I tried to look up in the cdsdoc but no avail. Is this
possible? If not would cadence (TIA - Martin, if you happen to see
this post) care to support this?

TIA,
Srinivasan

--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India, Visit: http://www.simputer.org)
"I don't Speak for Intel"





Article: 37290
Subject: Synplify to Actel clkbuf problems
From: tenelson@lanl.gov (Tony Nelson)
Date: 6 Dec 2001 08:34:23 -0800
Links: << >>  << T >>  << A >>
Hi,

I'm synthesizing a design in Synplify with no pin constraints, then
importing that edif into the Actel tools for PAR.  When I import a pin
constraint file into the Actel tools, it gives an error, because it
assigned a clock to an Actel HCLKBUF instead of a CLKBUF, which is
what that pin provides.  Are there any Synplify constraints that force
a specific signal to be a CLKBUF?  In Leonardo Spectrum this is quite
easy:

set_attribute .work.controller.struct.clk_15MHZ -name PAD -value
CLKBUF -port

Are there any comparable Synplify attributes to do the same thing?

Thanks,
Tony Nelson

Article: 37291
Subject: Re: Multiple Drivers & illegal connection
From: vhdlcohen@aol.com (VhdlCohen)
Date: 06 Dec 2001 16:44:08 GMT
Links: << >>  << T >>  << A >>
>I am using Leonardo Spectrum to synthesize my design.
>However in the PPR stage (Mapping) the following error message occurs :
>ERROR:NgdBuild:455 - logical net 'CLK_R' has multiple drivers
>ERROR:NgdBuild:466 - input pad net 'CLK_R' has illegal connection
>
>Can you give me some advices to solved this problem ?

Looks like you have two or more blocks sourcing CLK_R output. 
This is OK for simulation, but not for synthesis. 
---------------------------------------------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830  
http://www.vhdlcohen.com/                 vhdlcohen@aol.com  
Author of following textbooks: 
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8 
* Component Design by Example ",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

Article: 37292
Subject: Re: quartus post simulation setup problem
From: nchrysos@ics.forth.gr (Nick)
Date: 6 Dec 2001 09:13:55 -0800
Links: << >>  << T >>  << A >>
Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3C0EB1F6.160D02BC@flukenetworks.com>...


Well thanks...the Quartus II could be a solution but i cannot get it
this software...

anyway I did not have a clear answer about the problem ,since it
appears
regardless of the clock frequency that i use. 

What kind of setup violation is this?

Is there anything that i can do?
I only use the positive edge(changed it),  the problem is on internal
register ( no pins involved), it involves clock enable signals, it
involves two clock domains that are synchronized 2x ( no phase
difference).
The simulation problem appears also on the APEX, as far as i can see
from the logical  analyzer.
thanks for your interest..
Nick


> Brian Philofsky wrote:

> > I don't know.  I would be a little more cautious.  Is this path crossing clock
> > domains?  
> 
> I was assuming a synchronous design.
> He said it was an internal register.
> 
> > Is clock skew being accounted for? Not sure exactly how Quartus
> > accounts for this but is especially important if you are not using global clock
> > resources (i.e. using more than 4 clocks).  
> 
> Yes, in either case.
> 
> > Are you (Nick) clocking on both edges of the clock?  
> 
> I hope not.
> 
> > Does any part of the path originate from an I/O?  Is the path to a clock
> > enable?  Seems I have heard about problems with Quartus where in certain
> > circumstances would not properly report timing to register clock enables.
> 
> Reference please?
> 
> > I am not saying there is necessarily a problem here but I also would not blindly
> > disregard this as it may manifest itself as an intermittent problem later.  If it
> > was me, I would want to get to the bottom of the problem.  If you were targeting
> > Xilinx, I could give you some suggestions to help debug this issue but...
> 
> Is this a sales call?
> 
>            --Mike Treseler

Article: 37293
Subject: Re: quartus post simulation setup problem
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Thu, 06 Dec 2001 10:15:04 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------A61659F3ADC6A727D284A037
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit



Nick wrote:

> Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3C0EB1F6.160D02BC@flukenetworks.com>...
> > Brian Philofsky wrote:
> >
> > > I don't know.  I would be a little more cautious.  Is this path crossing clock
> > > domains?
> >
> > I was assuming a synchronous design.
> > He said it was an internal register.
>
> It is an internal register.

It sounds like it is crossing clock domains from what you say below.  I will explain why this might be important
to know there.



> > > Is clock skew being accounted for? Not sure exactly how Quartus
> > > accounts for this but is especially important if you are not using global clock
> > > resources (i.e. using more than 4 clocks).
> >
> > Yes, in either case.
> >
>
> I am using 2 clocks. Both are global, and this path actual uses both
> clocks.
> The second clock is derived from the first ( twice period)
> always @(posedge clk) s_clk = ~s_clk;

OK.  This could be an indication of your problem.  The second clock would arrive at the destination register the
value of the register clock-to-out plus the clock global routing delay after the clock arrives at the source
register.  This is causing a positive clock skew for this path.  If the data path delay is close to that amount of
skew you will have a timing problem and that could be what is showing up in the simulation.

There are a few ways to address this problem but probably the best way in my opinion is to use the clock enable of
the "slower" registers to enable the register every other clock cycle rather than defining these two clock
domains.  If you use the clock enable, all registers will be on the same global routing and thus skew should no
longer be an issue.  Use your own judgment what is the best way to go about this however that is one suggestion.


> > > Are you (Nick) clocking on both edges of the clock?
> >
> > I hope not.
> >
>
> Yes i do in one circumstance, is this so bad...? What i wanted to do
> is to provide a state like the following
> clk  101
> s_clk

Not bad but needs to be accounted for in timing analysis.  This is not a "sales call" as some may think but in the
Xilinx software, positive and negative edge clocked registers are automatically accounted for if a PERIOD
constraint is defined however is not if a FROM:TO or MAXDELAY is for the data path.  Also the Xilinx devices allow
clock inversion at the CLB thus not causing possible issues with clock skew when doing this.  I am not familiar
enough with the Quartus software or the Altera devices to make statements like that but what I can tell you is to
be sure that your timing analysis does cover this situation if it exists in your design or it too may come back to
you as a possible problem.  I have seen it happen to very talented engineers before.



> > > Does any part of the path originate from an I/O?  Is the path to a clock
> > > enable?  Seems I have heard about problems with Quartus where in certain
> > > circumstances would not properly report timing to register clock enables.
> >
> > Reference please?
> >
> > > I am not saying there is necessarily a problem here but I also would not blindly
> > > disregard this as it may manifest itself as an intermittent problem later.  If it
> > > was me, I would want to get to the bottom of the problem.  If you were targeting
> > > Xilinx, I could give you some suggestions to help debug this issue but...
> >
> > Is this a sales call?
> >
> >            --Mike Treseler
>
> I think the problem is actually there when i download on the device, i
> see strange thinks on the logical analyzer, much like those i see on
> the post compile simulation

Even more reason not to ignore the simulation and use it as a tool to help fix your problems.

Good luck,

--  Brian



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Article: 37294
Subject: Re: Newbie: FPGA or microcontroller for MPEG4 decoding?
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Thu, 6 Dec 2001 18:21:15 +0100
Links: << >>  << T >>  << A >>
"Quigley" <quigley2001@hotmail.com> schrieb im Newsbeitrag
news:755f9eb4.0112051948.26d505b@posting.google.com...
> Hi All,
>
> Just been reading about the different uses for FPGA's and was
> wondering if anyone knows if MPEG4 decoding is well suited for a FPGA,
> or is a more traditional microprocessor/controller better?

After all it can be done with an FPGA or an DSP but unlikely with
"Traditional" microcontrollers like 8051/C165/ 683xx etc. which are not very
well suited for MPEG4 decoding. Depending on your expirience and/or amout of
time you would like to invest into learning, the one or the other solution
will be better.

> (also, are there FPGA 'beginner' boards for PC's available, or do I
> have to devote a career to them first? :) )

Yes, there are lots of them. Do a simple google search. Or got to

www.aufzu.de

where they have good links to FPGA stuff. Its german, but I think you will
get the point.

--
MfG
Falk




Article: 37295
Subject: Re: ISP via JTAG
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Thu, 6 Dec 2001 18:24:24 +0100
Links: << >>  << T >>  << A >>
"AH" <akha@attbi.com> schrieb im Newsbeitrag
news:d2GP7.2209$ER5.241292@rwcrnsc52...
> Hi,
>
> I have another sort of silly question.  Say I have a Xilinx XC95xxXL
already
> mounted on a pcb.  Is it possible to program it via the JTAG interface to
> disable it's JTAG pins?  Would that mean the pins are disabled forever?
(or
> at least until I remove it from the pcb and reprogram?)

AFAIK NO.
--
MfG
Falk





Article: 37296
Subject: Re: Timing Constraints Spartan, divided Clk
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Thu, 6 Dec 2001 18:28:05 +0100
Links: << >>  << T >>  << A >>
"Utku Ozcan" <ozcan@netas.com.tr> schrieb im Newsbeitrag
news:3C0F7243.1782551F@netas.com.tr...
> Tobias wrote:
> >
> > Hello!
> > I have a problem with Timing Constraints. This is the first time I am
> > working with them and I am not quite sure what I am doing.. I am
> > dividing my CLK of 33MHz by two using the CLK divider from Xilinx
> > Foundation LogiBLOX generator. Then I use a secondary CLK buffer to
> > distribute the CLK.
> > I would like to use Constraints on the Ports in the Constraint editor,
> > but I can only choose my 33 MHz CLK as a relative to CLK Pad net. I
> > cannot choose my "new" divided CLK and therefore I get a warning that
> > my timing constraints are ignored. How can I change this?!
>
>   What I can recommend right now is, to write the
>   constraints directly to UCF file, rather than
>   using Constraints Editor. Do you have this chance?
>   In this case, you have the complete freedom
>   of constraining what you want.

But then the are ignored too, I think. The problem is, since the 16.5 Mhz
Clock is generated inside the FPGA, there is no direct setup/hold relation
for input pins. A way out of this mess may be to define timing groups an to
constrain them.
--
MfG
Falk






Article: 37297
Subject: Xilinx CPLD pin mapping with Foundation F3.1i
From: jeremyw@erlangtech.com (Jeremy Whatley)
Date: 6 Dec 2001 09:55:32 -0800
Links: << >>  << T >>  << A >>
I am attempting to implement a design in an XC95288XL CPLD.  I have
specified constraints to lock down the pin assignments.

When I run the implementation flow, my constraints are followed with a
few exceptions.  Some of the signals are mapped to apparently random
pins instead of to the assigned pins.  The assigned pins for these
signals are listed as "TIE" in the fitting report file.  According to
the report file, "TIE" indicates that the pin must be tied either high
or low (ie. not left floating).  There are other pins that are not
used by my design which are also listed as "TIE".

Does anyone know why this happens?  Is there a way to get around it,
or do I need to modify my constraints?  This design is still
pre-layout, so changing the pin assignments is not a problem.  I would
like to understand what is going on though.

Jeremy Whatley
jeremyw@erlangtech.com
Erlang Technology, Inc.

Article: 37298
Subject: XC6200
From: jhmorris47@hotmail.com (Jason)
Date: 6 Dec 2001 10:23:15 -0800
Links: << >>  << T >>  << A >>
Is there anything that is comparable to the Xilinx XC6200 RPU?

Jason

Article: 37299
Subject: Re: where is designed FPGA for apple II computer...?
From: gah@ugcs.caltech.edu (glen herrmannsfeldt)
Date: 6 Dec 2001 18:26:21 GMT
Links: << >>  << T >>  << A >>
"Kiyoung SON" <elcielo0@hitel.net> writes:

>designed FPGA for Apple II computer...
>I want it...

I know that people are working on FPGA implementations of
the PDP-8, PDP-11, and PDP-10.  Even the PDP-8 may be more
complicated than the 6502.

Now, how much of an Apple II can one put on an FPGA?

I would expect external RAM, but the video, serial and disk 
controller maybe could be included.

I think, though, it could be done in C and run on any current
processor instead.  Unless you need a 200MHz Apple II, I can't
see why you would want an FPGA version.

-- glen



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