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Messages from 33775

Article: 33775
Subject: how to replicate the Logic through VHDL attribut ?
From: Manjunathan <manjunathan_s1@yahoomail.com>
Date: Sat, 4 Aug 2001 01:38:27 -0700
Links: << >>  << T >>  << A >>
Hello everybody,

     i would like to know, how to replicate the logic through VHDL attributes in Xilinx foundation series 3.1i tool.

   for example ,
library IEEE;
use IEEE.std_logic_1164.all;

entity test23 is
    port (
        clk: in STD_LOGIC;
        a: in STD_LOGIC;
        b: in STD_LOGIC;
        c: out STD_LOGIC;
        d: out STD_LOGIC
    );
end test23;

architecture test23_arch of test23 is
signal a1 , a2 : std_logic ;

     
  
begin
a1 <= a and b ;
a2 <= a and b ;
 process(clk)
   begin
   
     if clk='1' and clk'event then 
     
        c <= a1 ;
        d <= a2  ;
        
    end if ;
    
 end process ;       
end test23_arch;

in this design i need to have two AND gates(for reducing the fanout).

but if i synthesis the code in xilinx tool it optimize the code to one LUT(AND gate) instead of two LUT's(2 AND gate).

how to acheive this ?

Thanks in Advance,
Regards,
Manjunath

Article: 33776
Subject: Re: Homemade Xilinx parallel cable problem + new question
From: Kolja Sulimma <kolja@sulimma.de>
Date: Sat, 04 Aug 2001 11:13:19 +0200
Links: << >>  << T >>  << A >>

Many of the problems with the xilinx parallel download cable III are due to a
bug in the Hardware Debugger software.
At the end of the programming process all the signals are tristated, but are
simultaneously set to a "0" value.
This produces a race condition that can cause the PROG signal to go low again.
Xilinx claims to have fixed this in answer record 6545. This is not true, as you
can easily verify with a DSO.

Whether this is a problem or not depends on the rise and fall times of your
parralel port, the suply voltage on the 74HC125, the length of the cable, the
capacitance on the 74HC125 outputs (see the capacitors in the schematic). We use
both Xilinx original cables and home brew cables in a lab course where te
students use their own computers. This way we have tested the cables at about 40
different computers and we can clearly state that both cables work on some
computers and do not work with others.

Adding schmitt triggers to the cable helps, but does not solve the problem.
Eevntually Xilinx will have to fix the software bug....

Kolja Sulimma

BTW:
This is why XESS has no problems downloading their boards: They have their own
download software.


Article: 33777
Subject: Re: multi-context FPGA
From: Kolja Sulimma <kolja@sulimma.de>
Date: Sat, 04 Aug 2001 11:44:34 +0200
Links: << >>  << T >>  << A >>
Atmels FPSLIC products at least have the ability to load a second
configuration while the FPGA is operating and then switch to the new
configuration in a single cycle.
AFAIK the old configuration is lost in this process and you must reload
it before switching back.

This means that you can not do all the fancy things that you could do
with MITs DPGA, but it has some useful applications anyway.

Maybe you remeber RAW in Geneva. A company called somthing like NEORAM
presented a chip that could hold multiple configurations and switch
between them in a few hundred cycles. Never heard of them again...

Kolja Sulimma

Reiner Hartenstein wrote:

> Hi, colleague,
>
> are there multi context FPGAs on the market
> having 2 or 4 banks of configuration memory ?
>
> Reiner


Article: 33778
Subject: Re: how to replicate the Logic through VHDL attribut ?
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Sat, 4 Aug 2001 10:56:09 +0100
Links: << >>  << T >>  << A >>
You need to look in the help file for your synthesiser.
The attribute you need to attach to c and to d will be
something like 'keep' or 'preserve'

"Manjunathan" <manjunathan_s1@yahoomail.com> wrote in message
news:ee71cf6.-1@WebX.sUN8CHnE...
> Hello everybody,
>
>      i would like to know, how to replicate the logic through VHDL attributes
in Xilinx foundation series 3.1i tool.
>
>    for example ,
> library IEEE;
> use IEEE.std_logic_1164.all;
>
> entity test23 is
>     port (
>         clk: in STD_LOGIC;
>         a: in STD_LOGIC;
>         b: in STD_LOGIC;
>         c: out STD_LOGIC;
>         d: out STD_LOGIC
>     );
> end test23;
>
> architecture test23_arch of test23 is
> signal a1 , a2 : std_logic ;
>
>
>
> begin
> a1 <= a and b ;
> a2 <= a and b ;
>  process(clk)
>    begin
>
>      if clk='1' and clk'event then
>
>         c <= a1 ;
>         d <= a2  ;
>
>     end if ;
>
>  end process ;
> end test23_arch;
>
> in this design i need to have two AND gates(for reducing the fanout).
>
> but if i synthesis the code in xilinx tool it optimize the code to one LUT(AND
gate) instead of two LUT's(2 AND gate).
>
> how to acheive this ?
>
> Thanks in Advance,
> Regards,
> Manjunath



Article: 33779
Subject: Re: Alliance tools going away?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Sat, 04 Aug 2001 11:14:37 +0100
Links: << >>  << T >>  << A >>


Petter Gustad wrote:

> Phil Hays <spampostmaster@home.com> writes:
>
> > Kamal Patel wrote:
> > >
> > > That is correct Robert.  The ISE GUI ...
> >
> > I hope that batch files still will work.
>
> I hope so too (I assume you mean all the individual command line
> tools). The only GUI program I use is floorplanner. However, I would
> love to see the tools available under Linux rather than a GUI with a
> talking chip (cousin of the MS paper-clip)...
>
> Petter
> --
> ________________________________________________________________________
> Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

O.k. Xilinx persons on CAF:

o (original question) Will it still be possible to run the command line
tools in ISE after the demise of Alliance ?

o Will it be possible to buy a version of Foundation ISE *without* FPGA
Express for the same price as the Alliance-up-to-XCV1000 package (~$1400) ?

Even better would be a version that dumps the overall GUI altogether for
those of us that never use it.  A ``serving suggestion''  that would greatly
increase the flexibility of the tool:

o Use the ``Tcl'' scripting language like the rest of the EDA industry's
tools - even Synopsys. [Better yet than that would be Perl but the EDA world
seems to have settled on Tcl ... HoHum].

At a stroke this would remove any real need for an overarching GUI except
for those processes that are inherently visual - Floorplanner, FPGAEditor.
It also allows the creation of arbitrary synth+P&R scripts (even integrate
a  post-synth simulation run ...). e.g. the MPPR option to PAR would just be
replaced with a ``for'' loop.

... and of course for those benighted souls who insist on a
push-the-big-green-button approach the ISE GUI would be written in Tcl's
graphical companion ``Tk''.







Article: 33780
Subject: Re: Clock skew with Xilinx DLLs...
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Sat, 04 Aug 2001 17:44:38 +0200
Links: << >>  << T >>  << A >>
Ray Andraka schrieb:
> 
> that fast route is a max of 0.17ns in a -4 part.  The Tcko and Tsu/Th values are based on worst case, so a typical chip is going to go much faster.

Hmmm.

> 
> We toggled the output flip flops in adjacent IOBs by the two clocks.  This gives you the shortest connection between the clock net and the pad.  By using adjacent IOBs, we assumed similar Tcko for both flip-flops.
> There is no routing variability introduced because the output flop to pad is a dedicated route (through a tristate buffer).  We did this in several locations around the chip.

;-))
Its always nice to gain knowledge from a master.
Thanks a lot.

-- 
MFG
Falk



Article: 33781
Subject: Re: Choosing a verilog synthesis tool (Altera/Xilinx)
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Sat, 04 Aug 2001 10:18:02 -0600
Links: << >>  << T >>  << A >>
"Andy Peters
> 
> Paul Smart wrote:
> >
> > I have done most of my work with Xilinx devices using the Xilinx FPGA
> > editor. I would like to get some advice on selecting a single verilog
> > synthesis tool that works well with both Altera and Xilinx.
> 
> Get a coin.  Flip it.  One side: choose Leonardo.  The other: choose Synplify.
> 
> Note that absence of a three-sided coin prevents you from choosing FPGA Express.

Nope - if the coin rolls on its edge then take  FPGA Express. :-)

-- 
Standard Disclaimer : 97% speculation 2% bad grammar 1% facts.
"Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
Now with schematics.

Article: 33782
Subject: Where's SpartanXL in WebPack?
From: "Chris_S" <cs@nospam.com>
Date: Sat, 4 Aug 2001 12:21:06 -0700
Links: << >>  << T >>  << A >>
Hi:

I just downloaded the Xilinix WebPack. I want to try some designs on
SpartanXL parts.  However, when I open the WebPack Navigator and start a new
project, all I see is Spartan-II parts, and the other CPLD stuff.  There is
no Spartan or SpartanXL listed as available devices.  I downloaded ALL of
the web pack modules.

Where is the place&route (fitter) for the SpartanXL family?

Thanks Chris.




Article: 33783
Subject: Re: finite defect statistics
From: "mulp" <michaelpettengill@earthlink.net>
Date: Sun, 05 Aug 2001 00:26:46 GMT
Links: << >>  << T >>  << A >>
"Rick Collins" <spamgoeshere4@yahoo.com> wrote in message
news:3B6B926B.82B210B7@yahoo.com...
> BTW, if 1 pp 5000 is not an acceptable noticed defect rate, what is? I
> have never worked in high volume manufacturing and I would like to know
> what are typical failure rates for complex ICs.

Returning to the original thread from whence this thread came:
=====
From: B. Joshua Rosen (bjrosen@polybus.com)
Subject: Re: Xilinx/Altera "behavioral" verilog
Newsgroups: comp.arch.fpga, comp.lang.verilog
Date: 2001-07-29 10:35:07 PST
"The FPGA vendors do some of this but they are limited
by the amount of time that they can tie up a chip tester for. Generally
the vendor tests runs in under a second, in my experience it takes about
20 minutes to really test an FPGA. If you are selling low volume high
value equiptment that contains a large number of FPGAs and loads many
different patterns into them, like and ASIC emulator, then this degree
of testing is necessary."

From: Andy Botterill (csm@plymouth2.demon.co.uk)
Subject: Re: Xilinx/Altera "behavioral" verilog
"Many thanks for such a detailed answer. I come from an ASIC
manufacturing background so the absence of scan would worry me. So there
is a 1 in 5000 chance of detecting a faulty FPGA? This is equivalent to
200 dppm which is a good quality level."

From: Paul Smart (pablo*@*maine.rr.com)
Subject: Re: Xilinx/Altera "behavioral" verilog
Newsgroups: comp.arch.fpga, comp.lang.verilog
Date: 2001-07-30 10:28:59 PST
"Die steps and new generation devices see higher failure rates
initially, and then scale back over time (product maturity?).

"Many  of the failed components cannot be verified as rejects by the
manufacturer (the manufacturers test methods missed the problem). This
applies to both X and A, my customer is a large user of both.

----------
"My ideal first goal would be to have the verilog output from the tools
be  directly usable with existing ASIC ATPG tools, specifically those
that can work with non scan designs. It is not a final solution, but
it is a step in the right direction.

"DFT tools for FPGA might be the next step. Given that this problem
does not significantly affect all users of FPGAs, I don't know how
reasonable it is to expect such tools to become a reality in the near
future.

"My end goal is to test and remove as many defects as possible at the
component level, before my customer places them on a board. It remains
to be seen how we will get there."
====

It's also interesting to compare this thread with the thread titled
"FPGAs in Safety Involved Applications".

I find this topic interesting because I've run into the same issues with
complex system test:

How much testing and how much self checking is enough?



Article: 33784
Subject: FPGA - VHDL Design Tools (Was: 4 (8) bit Microporcessor Implementation)
From: jaime.aranguren@ieee.org (Jaime Andres Aranguren Cardona)
Date: 4 Aug 2001 17:40:25 -0700
Links: << >>  << T >>  << A >>
Hi all!

Thanks a lot for the replies, gurus. Yuu are right, I was confused.
The compiler should "translate" from an assembly file to the
programmable .hex file.

But the new question is, perhaps more general, and regarding the
design tools.
What represents the best choice for a development environment: Xilinx
Foundation 3.1i or Renoir 99? The first one is vendor specific, and
the second one is perhaps more industry standard, as long as I know.

Would you please give suggestions about which one to use?

Thanks a lot


"Andy Peters <andy [@] exponentmedia" <".> com"> wrote in message news:<sDCa7.1826$cd1.226381@newsread1.prod.itd.earthlink.net>...
> Jaime Andres Aranguren Cardona wrote:
> 
> > - Should write our own compiler ("our" assembler -> bitsteram)
> 
> Your assembler won't be able to write out a Xilinx bitstream.  Why not
> do what the single-chip micros do, and have a program EPROM (or EEPROM,
> or whatever)?  The "program" should exist independent of the FPGA
> implementation of the processor.  Just make sure your CPU accesses the
> EPROM when reset. :)
> 
> The neat thing about rolling the CPU into an FPGA is that your "CPU" can
> have external-device chip selects that do exactly what you want them to,
> and as many as you want (within reason, of course).  And you can tailor
> external bus cycles to whatever hardware you're talking to: slow EPROM,
> fast SRAM, whatever.
> 
> -andy

Article: 33785
Subject: Re: Virtex-II prototyping board
From: Foolish <foolish@foolish.com>
Date: Sat, 04 Aug 2001 20:36:23 -0700
Links: << >>  << T >>  << A >>
Check www.dinigroup.com from time to time.  I don't think they have
a prototyping board that fits your expectations, but they may soon have
one. 

I know a company who's very satisfied with their older Virtex1000
prototype board (6 XCV-1000's mounted on a PCI card.  Kind of expensive,
though, I think it was $10k-$20k USD.)

> > Since the XC2V6000 devices are about $8000 US each through distribution,
> maybe
> > contracting someone to make a board for you to your own specifications is
> a
> > cost effective way to achieve your goal.
> 
> i) It is always better (and cheaper) to use of-the-shelf stuff when you need
> small quantities. Making my own board is the fall back.
> 
> ii) The board is to be used as part of a general hardware acceleration
> platform so the specifications are very simple (lots of connections between
> the FPGAs).
> 
> iii) The price for XC2V6000-4FF1152 is less than 3000US$ if you buy it from
> Insight.
> 
> Cheers,
> 
> Rotem.
> 
> >
> >
> > Rotem Gazit wrote:
> >
> > > I'm looking for a prototyping board containing 3 (or more) XC2V6000
> FPGAs.
> > >
> > > Thanks,
> > >
> > > Rotem.
> >
> 
> Rotem Gazit
> 
> MystiCom LTD
> 
> mailto:rotemg@mysticom.com
> 
> http://www.mysticom.com/

Article: 33786
Subject: Re: May I connect two pins to the same net?
From: vr <searchingforaneasywayto@makeunusedinptustri.com>
Date: Sun, 5 Aug 2001 06:25:48 +0000 (UTC)
Links: << >>  << T >>  << A >>
> the behaviour of the undefined pins (DRIVING a signal) fooled us a lot.
> :-(

Bit me too. Who expected such weirdness?

Perhaps this was explained some place else but is there an easy way to
tell Max+Plus II to make unused I/Os tri-stated(inputs)? Or an easy way to
assign un-used I/Os to VCC/GND?

I suppose one could add a pin in a GDF and then stick a tri-buffer on
it(or whatever, but this seems slight painful.

Thanks,
VR.

Article: 33787
Subject: Re: May I connect two pins to the same net?
From: "Paul Teagle" <pteagle@bigpond.net.au>
Date: Sun, 05 Aug 2001 11:38:14 GMT
Links: << >>  << T >>  << A >>

"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
news:3B6E5599.31971F18@gmx.de...
> vr schrieb:
> >
> > > the behaviour of the undefined pins (DRIVING a signal) fooled us a
lot.
> > > :-(
> >
> > Bit me too. Who expected such weirdness?
> >
> > Perhaps this was explained some place else but is there an easy way to
> > tell Max+Plus II to make unused I/Os tri-stated(inputs)? Or an easy way
to
> > assign un-used I/Os to VCC/GND?
>
> Altera suggest to define all unused pins as inputs. Then, if you dont
> use them in your VDHL, the will be tristated.
> It works, but its still weird.
>

I think the reason as to why the Max+Plus defines unused pins as outputs is
that otherwise you would have floating CMOS inputs - and they would tend to
half rail and consume excessive currents, low noise immunity etc etc. The
Hi-Z refers to the output pins. Inputs are by nature high impedance.

That's the case on the 10K devices. Maybe the 20K family (I've never used
them) has internal bus keeper resistors and thus they are pulled up/down
internally, and the Quartus s/w knows this and thus defaults to the safer
"input" configuration.

Paul T.
CAE Inc.



Article: 33788
Subject: Re: Why did Zephram spool outside all the users? We can't post
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Sun, 05 Aug 2001 15:31:00 +0100
Links: << >>  << T >>  << A >>


Austin Clarkson wrote:

> Let's propagate for the filthy structures, but don't disrupt the
> soft operators.  Joie will smartly delete beside Russ when the
> violent plotters put against the moronic cybercafe.  Well, routers
> defeat on lazy rooms, unless they're discarded.  A lot of solid
> ugly screens will stupidly prepare the iterations.  He will negotiate
> sneakily if Andrew's machine isn't usable.  We quickly recycle
> behind opaque shiny highways.  Owen will proliferate the inner
> programmer and keep it inside its network.  Who defiles usably, when
> Norbert questions the actual RAM behind the satellite?  If you'll
> tolerate Quinton's /dev/null with TCP/IPs, it'll wistfully jump the
> admin.  Steven stops, then Fred regularly gets a official interrupt
> about Wally's field.  Why did Bill load the desktop about the
> dense subroutine?  What will we build after Jonnie opens the
> weak data bus's PERL?  While analysts generally distribute, the
> Pascals often interface over the specialized inputs.  Gavin wants to
> sell neatly, unless Frank collaborates fax machines behind Georgette's
> postmaster.  The outer client rarely causes Gilbert, it knows
> Simone instead.  If you will corrupt Yolanda's FBI at texts, it will
> steadily disconnect the procedure.  I generate closed newbies
> within the untamed major bit bucket, whilst Roxanne familiarly
> pushs them too.  To be old or erect will moan secret networks to
> hatefully spool.  When doesn't Mikie dump finitely?  My important
> ROM won't take before I inflate it.  Will you slump against the
> web page, if Petra wrongly digs the terminal?  When Zamfir's
> lower interface floats, Neil beats in abysmal, foolish modules.

What the f*****g hell is all this bollocks about ? Would you & it please
return to the dingy cave from whence you came.




Article: 33789
Subject: About those "babble" posts here.
From: hmurray-nospam@megapathdsl.net (Hal Murray)
Date: Sun, 05 Aug 2001 17:12:49 -0000
Links: << >>  << T >>  << A >>
> What the f*****g hell is all this bollocks about ? Would you & it please
> return to the dingy cave from whence you came.

Note that the reply was sent to:
  Newsgroups: news.admin.net-abuse.email,comp.arch.fpga


Here is some info copied from another newsgroup I scan...


A net-vandal of several years -- known as HipCrime -- is currently
conducting a Denial of Service attack on news.admin.net-abuse.email.
He's been flooding that group with as many as 40,000 posts *per day*
for the last few weeks using a program that generates babble much like
the Noam Chomsky babble-bot.

One of his tricks is to cross-post his stuff into several groups and
to set the follow-up to nanae only.  Thus, any response (whether
clever, obscene, annoyed, or genuinely curious) just goes back to
nanae and adds to the garbage there.

If you see these posts in other groups that you frequent, it would be
helpful if you'd post a warning similar to this one."

FYI, his posts have been turning up in many, many newsgroups"



For the newbies, a brief heads-up on HipCrime
http://extra.newsguy.com/~rchason


-- 
These are my opinions, not necessarily my employeers.  I hate spam.


Article: 33790
Subject: Which is the best Design Toolchain?
From: jaime.aranguren@ieee.org (Jaime Andres Aranguren Cardona)
Date: 5 Aug 2001 10:42:51 -0700
Links: << >>  << T >>  << A >>
Hi, everybody.

Want to generate opinions, from diverse kind of professionals, about
the Design Tools used for FPGA/CPLD/ASIC designs.

What is the industry-standard method for design? Is it text based
VHDL/Verilog entry, text based test benches generation and graphical
simulation? Or do professionals prefer alternate ways, such Finite
State Machines (graphical entry), Block Diagrams, Truth Tables and/or
Schematics?

And what can be considered more "universal" and "standard", between
tools like Xilinx's Foundation and Mentor Graphics' Renoir, ModelSim
and Leonardo Spectrum?

I expect to generate an instructive discussion topic, invlolving
people from industry and academic spheres.

Best regards,

Jaime Andres Aranguren Cardona
jaime.aranguren@ieee.org
jaime.aranguren@computer.org

Article: 33791
Subject: Slightly off topic - PCs for running FPGA tools
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Sun, 05 Aug 2001 14:38:40 -0400
Links: << >>  << T >>  << A >>
I am looking for a laptop which will be my "everything" PC including
running FPGA design software. It seems that laptops are nearly up to the
task with the possible exception of  the memory. I am looking at AMD
Athlon powered units and they don't seem to have much memory and it is
not very fast. Desktop units use 266 DDR memmory while these laptops use
SDRAM 100. The laptops also only support up to 512 MB while desktops go
up to 3 GB. 

Am I correct in thinking that the difference in both speed and quantity
will affect my P&R times severely? Does anyone have an estimate of the
performance hit for using PC100 memory vs. DDR266? 

The Athlon seems to have a bit more cache, 128K vs 32K of L1 cache in
the PIII. Is this expected to be noticable? I guess this would just be
lumped into the overall speed difference between the Athlon and the
PIII. 

It does seem that AMD can't shake the low end image they have in the
laptop market. The Athlon is the screamer chip in laptops and yet the
PIIIs are in the high end units with the bells and whistles such as the
higher resolution LCDs and the larger memories. 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 33792
Subject: Re: Which is the best Design Toolchain?
From: "Victor Schutte" <victors@mweb.co.za>
Date: Sun, 5 Aug 2001 20:47:20 +0200
Links: << >>  << T >>  << A >>
I use Altera's software and use AHDL, Schematic, VHDL and Verilog. Each
project differs and requires a different angle. Example: My one CPU project
is very simple in VHDL but my Dual Port RAM network card took less that
30minutes to do in schematic. I gained a few ns speed when I redesigned my
one CPLD address decoder from VHDL to AHDL.  Like I said every project is
different. Also, I have many "PLD" friends and web contacts all working with
different packages and languages, so to do everything and understand most
methods have their advantages.

For portability I would prefer (1) VHDL and (2)Verilog.

A nice to have will be to do state machines with truth tables,  like I did
years ago in Log/IC. VHDL is way is to bulky.


Victor Schutte
Zerksus Engineering

"Jaime Andres Aranguren Cardona" <jaime.aranguren@ieee.org> wrote in message
news:14a86f87.0108050942.7de276c0@posting.google.com...
> Hi, everybody.
>
> Want to generate opinions, from diverse kind of professionals, about
> the Design Tools used for FPGA/CPLD/ASIC designs.
>
> What is the industry-standard method for design? Is it text based
> VHDL/Verilog entry, text based test benches generation and graphical
> simulation? Or do professionals prefer alternate ways, such Finite
> State Machines (graphical entry), Block Diagrams, Truth Tables and/or
> Schematics?
>
> And what can be considered more "universal" and "standard", between
> tools like Xilinx's Foundation and Mentor Graphics' Renoir, ModelSim
> and Leonardo Spectrum?
>
> I expect to generate an instructive discussion topic, invlolving
> people from industry and academic spheres.
>
> Best regards,
>
> Jaime Andres Aranguren Cardona
> jaime.aranguren@ieee.org
> jaime.aranguren@computer.org



Article: 33793
Subject: Re: Why did Zephram spool outside all the users? We can't post procedures unless Brion will grudgingly dig afterwards.
From: Mark Ferguson <admin@whew.com>
Date: Sun, 05 Aug 2001 19:11:04 GMT
Links: << >>  << T >>  << A >>
Information on this newsgroup flooder.

http://www.whew.com/On-Line_Spam/hipcrime_FAQ.shtml

Austin Clarkson wrote:
> 
> Let's propagate for the filthy structures, but don't disrupt the
> soft operators.  Joie will smartly delete beside Russ when the
> violent plotters put against the moronic cybercafe.  Well, routers
> defeat on lazy rooms, unless they're discarded.  A lot of solid
> ugly screens will stupidly prepare the iterations.  He will negotiate
> sneakily if Andrew's machine isn't usable.  We quickly recycle
> behind opaque shiny highways.  Owen will proliferate the inner
> programmer and keep it inside its network.  Who defiles usably, when
> Norbert questions the actual RAM behind the satellite?  If you'll
> tolerate Quinton's /dev/null with TCP/IPs, it'll wistfully jump the
> admin.  Steven stops, then Fred regularly gets a official interrupt
> about Wally's field.  Why did Bill load the desktop about the
> dense subroutine?  What will we build after Jonnie opens the
> weak data bus's PERL?  While analysts generally distribute, the
> Pascals often interface over the specialized inputs.  Gavin wants to
> sell neatly, unless Frank collaborates fax machines behind Georgette's
> postmaster.  The outer client rarely causes Gilbert, it knows
> Simone instead.  If you will corrupt Yolanda's FBI at texts, it will
> steadily disconnect the procedure.  I generate closed newbies
> within the untamed major bit bucket, whilst Roxanne familiarly
> pushs them too.  To be old or erect will moan secret networks to
> hatefully spool.  When doesn't Mikie dump finitely?  My important
> ROM won't take before I inflate it.  Will you slump against the
> web page, if Petra wrongly digs the terminal?  When Zamfir's
> lower interface floats, Neil beats in abysmal, foolish modules.


--
Regards Mark
Spam in the News *updated* http://www.whew.com/On-Line_Spam/News/
Stop junk mail in it's tracks http://www.whew.com/USPS/
The DMM http://www.whew.com/USPS/domestic_mail_manual/

Article: 33794
Subject: Re: finite defect statistics
From: "Austin Franklin" <austin@dark87room.com>
Date: Sun, 5 Aug 2001 15:46:01 -0400
Links: << >>  << T >>  << A >>
> I may be talking out of my hat, but it seems that most posters are
> missing one point. We all my have done a lot of designs and we may have
> worked with a lot of chips, but Joshua's application exercises many
> chips with many different designs each and every time. If he does not
> find the "hidden" defects, his customers will find them. In your
> designs, you may have a few iterations of a given design, but you likely
> have many, many fewer than 100. Even those will have a lot of
> commonality. So if you don't exercise all of your boards with a lot of
> different and possibly "exotic" designs, you may not see anything like
> the defect rates Joshua is talking about.

I'm not missing what he said...I just don't buy it, since it hasn't been
proven with any reasonable certainty.  There has been no mention of the
errors being hard...and that makes me suspicious.  I really only buy things
like this when they stand up to peer review (or make sense ;-), and since I
can't see the tests, the conditions, or the failures.

These "errors" he is seeing may be caused by some uncharacterized issue,
like I stated in another post, or some tool problem allowing
routes/conditions that should not be done.  Not actual part failure.  I
don't know, and I am not willing to accept conclusions as such without
proper information.  The subject that he (Joshua) brought it up IS
interesting..  I am not saying that this is the case here, but I found quite
a number of times, in similar circumstances, that a claim is made, and the
conclusion is erroneous.




Article: 33795
Subject: Webpack Default Browser
From: "Dave Feustel" <dfeustel1@home.com>
Date: Sun, 05 Aug 2001 20:18:48 GMT
Links: << >>  << T >>  << A >>
When I start up the Xilinx Webpack Project Navigator,
the first message I get is that the default browser is not
present and that some functions may not be available.

I can't find any option in the Project Navigator menus for
changing the default browser to IE. Is there a way to do that?

Thanks,

Dave Feustel



Article: 33796
Subject: Re: Where's SpartanXL in WebPack?
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Sun, 5 Aug 2001 21:29:26 +0100
Links: << >>  << T >>  << A >>
> Where is the place&route (fitter) for the SpartanXL family?

WebPack doesn't support the older Spartan chips, only the Spartan-II.

Leon



Article: 33797
Subject: Re: Why did Zephram spool outside all the users? We can't post procedures unless Brion will grudgingly dig afterwards.
From: armageddon@dial.pipex.com (Chris Suslowicz)
Date: Sun, 05 Aug 2001 21:35:24 +0100
Links: << >>  << T >>  << A >>
In article <3B6D58A4.CEC7A8B9@algor.co.uk>,
Rick Filipkiewicz <rick@algor.co.uk> wrote:

>
>Austin Clarkson wrote:
>
>> Let's propagate for the filthy structures, but don't disrupt the

<Snip rest of machine generated post>
<Remove crosspost to nanae, we've got zillions of 'em!)
 
>What the f*****g hell is all this bollocks about ? Would you & it please
>return to the dingy cave from whence you came.

It's a machine-generated flooding attack on news.admin.net-abuse.email
(nanae) by a spammer and sociopath calling itself 'Hipcrime'.

The *current* methods are:

a) flood nanae with garbage posts via open news servers. (easily filtered)
b) flood nanae with rogue cancels (still easily defeated)
c) flood nanae with supersede messages (ditto)
d) flood *other* newsgroups with garbage, crossposted to nanae.
e) flood *other* newsgroups with garbage, but set followups to nanae.

The idea behind (d) and (e) is that innocent bystanders will not realise
what is going on, and will follow up to the message, thus attacking nanae
by proxy.

What you have here is case (d) - probably (you didn't include headers, but
it *is* crossposted to nanae).

Solutions:

1) complain to your ISP (or News server operator) and ask them to block the abuse.
2) killfile messages crossposted to the news.admin hierarchy - they are offtopic.
3) killfile anything with followups set to news.admin groups

Hope this explains things a little.

Chris.



Article: 33798
Subject: Re: Spartan II and asynchronous memory interface
From: "Rob Finch" <robfinch@sympatico.ca>
Date: Sun, 5 Aug 2001 16:55:44 -0400
Links: << >>  << T >>  << A >>
I know this is a really dumb question but, is the sram module connected to a
pair of module ports that will work with the sram ? Several of the ports
will 'almost' work except they have an input only signal on one of the pins.
Which I believe ends up being connected to the OE of the ram. Are you using
the constraints editor to set the pin locations ? I am using a B3 Spartan2+
board and the only port the sram module can be connected to is the J6, J9
pair. Also I have written a little test hardware that tests the ram using a
checkerboard pattern, and it's not found any errors. I could mail it to you
if you're interested. I've only tested at 8MHz so far, but as other posts
point out, it's not necessarily the clock frequency that causes a problem.

"Steven Derrien" <sderrien@irisa.fr> wrote in message
news:3B697EF9.E5BDF155@irisa.fr...
> Hi,
>
> We are curently trying to port the XR16/Xsoc project (www.fpgacpu.org)
> to a VHDL targeted to the BurchEd Spartan II board
> (http://www.burched.com)
>
> We plan to make our work freely available, but are currently stuck on
> a problem. The design is a 16 CPU-SOC which interfaced to a parallel
> port.
>
> We have somes on-chip blockrams which serves as ROM, and off-chip
> asynchronous
> SRAM whiwh serves as main memory. Our problem is that we get frequent
> errors when accessing the off-chip SRAM banks. Generally a single bit
> wrong in a 16 bit data word every 200-300 access.
>
> All simulation (RTL,gate-level,post place and route) went fine.
> Right now, our system is clocked at 1Mhz far below its maximum
> frequency.
> Besides, the SRAM Write Enable command output signal is registered
> (although not in a IOB register) to avoid glitches which could cause
> wrong write operations.
>
> All IOB are configured with SLOW slew-rate and drive 12mA (default IOB
> config)
>
> We have been beating our heads on this problem for almost a week now,
> are there any experts around there to offer some tips/ideas/advices ?
>
> Thanks,
>
> Steven



Article: 33799
Subject: Webpack DOS shelling
From: "Rob Finch" <robfinch@sympatico.ca>
Date: Sun, 5 Aug 2001 17:20:55 -0400
Links: << >>  << T >>  << A >>
Many times when I run Webpack and it shells out to DOS to perform an
operation, the DOS shell hangs. It's really ugly then to shut down Webpack.
The stop process command doesn't work and Webpack won't allow you to exit
while a process is running. Has anyone else experienced this problem, and
how did you resolve it ?

Thanks
Rob    http://www.birdcomputer.ca






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