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Messages from 34650

Article: 34650
Subject: Re: FPGA: time_sim.sdf does not have the setup times f
From: "Nisreen Taiyeby" <nisreen@blr.paxonet.com>
Date: Sat, 1 Sep 2001 01:02:17 -0700
Links: << >>  << T >>  << A >>
The flops are in the IOB and I have checked it in the floorplanner too. But the problem is that the .sdf file does not give the setup time for iob flop , instead it give 271ps, the setup time for a cLB flop.

regards.
Nisreen

Article: 34651
Subject: Re: How to connect a clock to a non-clock pad ?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Sat, 01 Sep 2001 10:35:55 +0100
Links: << >>  << T >>  << A >>


"A. I. Khan" wrote:

> Hi all !
>
> I need to use more than 4 clocks in my design. The synthesis tool
> (Foundation series) complains about the resource (clock) while I try for
> implementing my design since there are 4 dedicated clock inputs ONLY
> (Virtex-E , V1000).
>
> I would greatly appreciate if anyone can advise me how to solve this
> problem and how to connect a clock to a non-clock pad so that I can get
> rid of the extra clock(s).
>
> Thanks in advance,
>
> --  Khan

By default most synth tools automatically detect clock nets and assign
whatever global buffers are available to them. In your case you have to
decide which clocks are less important and turn this off.

I don't know how you do this in XST, for Synplify I can set an attribute

define_attribute {clk} syn_noclockbuf {1}

in the constraints file or

...
input clk /*synthesis syn_noclockbuf=1 */;
....

in the source.

Having done that you should apply a "USELOWSKEWLINES" constraint to those
clocks without dedicated buffers. I *think* PAR does this automatically but
its best to be explicit.

Finally you should place the non-dedicated clock pins near the secondary
clock network driving buffers.





Article: 34652
Subject: Prom : Question on Configuration
From: "Harry Chung" <wkchung@ee.cuhk.edu.hk>
Date: Sat, 1 Sep 2001 03:01:20 -0700
Links: << >>  << T >>  << A >>
Hi,
    I try to configurate a FPGA by a XC18V04 and I would like to download the bitstream file to the Prom by a universal programmer. Then, what kind of file should I provide to the programmer, *.mcs, *.exo or *.hex?

   Moreover, if I power on the system, what is the typical time required for a complete configuration of FPGA by prom? Or how long should DONE become HIGH?

Thank you very much,
Harry

Article: 34653
Subject: Re: FPGA : USB in an FPGA, has anyone done it before?
From: "David Feustel" <dfeustel@mindspring.com>
Date: Sat, 01 Sep 2001 16:09:39 GMT
Links: << >>  << T >>  << A >>
Is there any price / availability info on the chip described?

"Muzaffer Kal" <muzaffer@dspia.com> wrote in message news:tg3ootgm3b2gnkktgbvtdqjp083kn772hn@4ax.com...
> "Dave Feustel" <dfeustel@mindspring.com> wrote:
>
> >Felix,
> >
> >I've been looking for a 32/16/8 bit peripheral parallel interface using USB 2.0.
> >I haven't found any at all. All I've been able to find is ATA IDE interfaces
> >which I don't think I can twist into what I want. An FPGA implementation
> >would be very handy.
>
> You can check this url for such a part:
> http://www.softmixedsignal.com/usb2.html
>
> Muzaffer



Article: 34654
Subject: Re: Defending Austin Franklin
From: Kolja Sulimma <kolja@prowokulta.org>
Date: Sat, 01 Sep 2001 19:39:04 +0200
Links: << >>  << T >>  << A >>


> Like who?  And what engineering tools run on it? (Linux)

The whole Magma Asic Tool chain: www.magma-da.com

> Does Xilinx run on Linux?

There is Alliance for Linux. I am not sure how hard it is to get the Xilinx
support running.

> Does, Viewlogic run on Linux?
> Does PADS run on Linux?

Eagle does. Target also...

> Linux is good, I have nothing against it...but support for it is far far far
> less than is for Windows.

You are right, but nowadays support for Linux is certainly far far far far
better than support for Solaris.
But anyway there are a lot more EDA tools for Solaris than there are for
Windows.

There are certainly good reasons to support either windows or unixes.
What I really do not understand is why many Unix  based tool chains do not
support Linux.
A command line tool should be posix compliant and run more or less immediatly
under another linux flavor. And porting the Tclk/Tk interfaces of Cadence or the
like should not be that hard either.

Kolja Sulimma




Article: 34655
Subject: Re: Defending Austin Franklin
From: Simon Gornall <simon@unique-id.com>
Date: Sat, 01 Sep 2001 22:14:44 +0000
Links: << >>  << T >>  << A >>
Ben Franchuk wrote:
> 
> With Linux people don't want to pay the BIG $$$ that Unix based
> software can charge.

There are two types of Linux user - those that use it at home (for
whom I think your opinion is correct), and those that use it for 
business. My company markets a $70k software package that runs under
Linux - it's nothing to do with FPGA's, but I don't see why if people
will pay in one business area, they won't pay in another ...

ATB,
	Simon.

Article: 34656
Subject: Problems with Synthesis and Implementation in Xilinx Foundation 3.3i
From: Kris Nichols <knichols@uoguelph.ca>
Date: Sun, 02 Sep 2001 00:18:16 GMT
Links: << >>  << T >>  << A >>
Hey everybody,
             I'm currently using Xilinx Foundation 3.3i (ELITE) with
service pack 8, and am attempting to synthesize and implement (i.e. map
and route) a VHDL design down onto a Xilinx Virtex-E (XCV100E-6PQ240Q)
FPGA.  When I use the Xilinx XST Synthesis tool to synthesize my design,
it uses up 3GB of memory (1GB physical memory + 2GB virtual memory) and
then produces the following error:

Memory Full --> Done: failed with exit code 0003.

I then try to synthesize my design using the Synopsys 'FPGA Express'
(version 3.5) and synthesis is successful.  However, when I try to then
implement (i.e. map and route) my design for the Virtex-E FPGA, I get
the following error while the design is being mapped:

:
Running unrelated pack...
EXEWRAP detected a return code of '-1073741819' from program 'map'
Done: failed with exit code: 0005

Has anyone ever come across these kinds of problems??  Anybody know of
any 'workarounds' for these kinds of problems??  Other than Xilinx
Answer's database, I'm unable to get any kind of support from Xilinx,
since I'm using their product under an 'academic' license. Thanks in
advance.

Kris Nichols
M.Sc. Candidate
School of Engineering
University of Guelph
Guelph, Ontario
Canada


Article: 34657
Subject: [testbench] testbench porting from Cadence to Altera
From: "tasi@emc" <tasi@emc.com.tw>
Date: Sun, 2 Sep 2001 09:50:26 +0800
Links: << >>  << T >>  << A >>
hi all

I have a testbench and test ok under Cadence. Now I want to do verification
under Altera's FPGA.
May I use original testbench to FPGA verification? and how to por it into
Altera's simulation tool?
Thanks!!





Article: 34658
Subject: Clock Multiplication
From: aadityas@hotpop.com (Sriram S)
Date: 2 Sep 2001 00:28:40 -0700
Links: << >>  << T >>  << A >>
Hi friends,

Without using a DLL/PLL how can i multiply a clock by 1.5.

I belive a Lookup Table method can be used. But this is not an optimal method. 
Please give more ideas on this.......


Kind regards
sriram

Article: 34659
Subject: Re: Problems with Synthesis and Implementation in Xilinx Foundation 3.3i SP8(ELITE)
From: "Tim" <tim@rockylogic.com.nospam.com>
Date: Sun, 2 Sep 2001 12:05:42 +0100
Links: << >>  << T >>  << A >>
Could be something like a combinatorial explosion when synthesising
a wide XOR, or synthesising a memory block as a bunch of FFs.  Does
the synth report file give any clues?

Try synthesising subdesigns in a 'bottom-up' manner to try and
isolate the problem module.

"Kris Nichols" <knichols@uoguelph.ca> wrote in message
news:3B91A350.625765CE@uoguelph.ca...
> Hey everybody,
>              I'm currently using Xilinx Foundation 3.3i (ELITE) with
> service pack 8, and am attempting to synthesize and implement (i.e. map
> and route) a VHDL design down onto a Xilinx Virtex-E (XCV100E-6PQ240Q)
> FPGA.  When I use the Xilinx XST Synthesis tool to synthesize my design,
> it uses up 3GB of memory (1GB physical memory + 2GB virtual memory) and
> then produces the following error:
>
> Memory Full --> Done: failed with exit code 0003.
>
> I then try to synthesize my design using the Synopsys 'FPGA Express'
> (version 3.5) and synthesis is successful.  However, when I try to then
> implement (i.e. map and route) my design for the Virtex-E FPGA, I get
> the following error while the design is being mapped:
>
> :
> Running unrelated pack...
> EXEWRAP detected a return code of '-1073741819' from program 'map'
> Done: failed with exit code: 0005
>
> Has anyone ever come across these kinds of problems??  Anybody know of
> any 'workarounds' for these kinds of problems??  Other than Xilinx
> Answer's database, I'm unable to get any kind of support from Xilinx,
> since I'm using their product under an 'academic' license. Thanks in
> advance.
>
> Kris Nichols
> M.Sc. Candidate
> School of Engineering
> University of Guelph
> Guelph, Ontario
> Canada
>



Article: 34660
Subject: Re: Xilinx Device Update under Solaris
From: hamish@cloud.net.au
Date: Sun, 02 Sep 2001 13:38:51 GMT
Links: << >>  << T >>  << A >>
Petter Gustad <newsmailcomp1@gustad.com> wrote:
> Some  time ago I received the CD titled: Device Update Foundation
> Series 3.3i (Contains Virtex-II Device Libraries and Service Pack
> 6).
> 
> I can't figure out how to install it on my Solaris machine. There
> is nothing about Solaris in the Readme.txt file. There is only  a
> Setup.exe Windows executable.

I think you should have a second CD for UNIX installation..


Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 34661
Subject: Re: Xilinx Device Update under Solaris
From: Petter Gustad <newsmailcomp1@gustad.com>
Date: 02 Sep 2001 16:35:35 +0200
Links: << >>  << T >>  << A >>
hamish@cloud.net.au writes:

> Petter Gustad <newsmailcomp1@gustad.com> wrote:
> > Some  time ago I received the CD titled: Device Update Foundation
> > Series 3.3i (Contains Virtex-II Device Libraries and Service Pack
> > 6).
> > 
> > I can't figure out how to install it on my Solaris machine. There
> > is nothing about Solaris in the Readme.txt file. There is only  a
> > Setup.exe Windows executable.
> 
> I think you should have a second CD for UNIX installation..

Thats the response I got from Xilinx too. I'm awaiting the CD from my
local distributor...

BTW: Why don't they provide the device libraries on the web...

Petter
-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 34662
Subject: DSP in OTP
From: "pete dudley" <padudle@spinn.net>
Date: Sun, 2 Sep 2001 12:10:44 -0600
Links: << >>  << T >>  << A >>
Hello All,

I have a customer who wants to replace an analog signal processing ASIC with
a digital fpga for flexibility.

The analog ASIC contains some low pass filtering, i/q demodulation and
integration operations. The filtering requires something like a 6th order
IIR. Input data is 8 bits or less. Input sample rates are like 15Msps.

All of this would be cake in a ram based fpga but it will be necesary  to
use an OTP like Actel or Quicklogic for shelf life and instant-on reasons.
Also we would like to keep the cost of the fpga below $20 because volume is
significant (10K to 100K/yr).

Could anyone offer advice about doing digital filtering in Actel or
Quicklogic? Their web pages have only basic discussions of digital
filtering. For example the Actel page only shows direct form implementations
of FIR filters with no mention of transpose form filtering.

I haven't given many details of my application so I'm just looking for
general advice on feasibility and approach.

Thank you,

--
Pete Dudley

Arroyo Grande Systems




Article: 34663
Subject: Re: DSP in OTP
From: "Kevin Neilson" <kevin_neilson@removethis-yahoo.com>
Date: Sun, 02 Sep 2001 18:19:32 GMT
Links: << >>  << T >>  << A >>
Is ClearLogic still around?  Their gig was that they made Altera clones, and
you send them the bitfile and they had a configurable top layer that they
programmed with a laser or something, so you got a hardwired version of the
Altera.  There was an NRE, but it was supposedly pretty reasonable,
especially compared with an ASIC.

"pete dudley" <padudle@spinn.net> wrote in message
news:tp4tbm3ejm4q88@corp.supernews.com...
> Hello All,
>
> I have a customer who wants to replace an analog signal processing ASIC
with
> a digital fpga for flexibility.
>
> The analog ASIC contains some low pass filtering, i/q demodulation and
> integration operations. The filtering requires something like a 6th order
> IIR. Input data is 8 bits or less. Input sample rates are like 15Msps.
>
> All of this would be cake in a ram based fpga but it will be necesary  to
> use an OTP like Actel or Quicklogic for shelf life and instant-on reasons.
> Also we would like to keep the cost of the fpga below $20 because volume
is
> significant (10K to 100K/yr).
>
> Could anyone offer advice about doing digital filtering in Actel or
> Quicklogic? Their web pages have only basic discussions of digital
> filtering. For example the Actel page only shows direct form
implementations
> of FIR filters with no mention of transpose form filtering.
>
> I haven't given many details of my application so I'm just looking for
> general advice on feasibility and approach.
>
> Thank you,
>
> --
> Pete Dudley
>
> Arroyo Grande Systems
>
>
>



Article: 34664
Subject: Re: DSP in OTP
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: 2 Sep 2001 18:22:57 GMT
Links: << >>  << T >>  << A >>
pete dudley <padudle@spinn.net> wrote:
: Hello All,

: I have a customer who wants to replace an analog signal processing ASIC with
: a digital fpga for flexibility.

: The analog ASIC contains some low pass filtering, i/q demodulation and
: integration operations. The filtering requires something like a 6th order
: IIR. Input data is 8 bits or less. Input sample rates are like 15Msps.

: All of this would be cake in a ram based fpga but it will be necesary  to
: use an OTP like Actel or Quicklogic for shelf life and instant-on reasons.
: Also we would like to keep the cost of the fpga below $20 because volume is
: significant (10K to 100K/yr).

: Could anyone offer advice about doing digital filtering in Actel or
: Quicklogic? Their web pages have only basic discussions of digital
: filtering. For example the Actel page only shows direct form implementations
: of FIR filters with no mention of transpose form filtering.

: I haven't given many details of my application so I'm just looking for
: general advice on feasibility and approach.

Quicklogic has so called "ESP chips, with dedicated logic. The Quick DSP has
dedicated DSP units, which should easily fullfill your DSP requirements.

Bye

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 34665
Subject: Re: DSP in OTP
From: NotMe <not-given@invalid.com>
Date: Sun, 02 Sep 2001 19:58:31 GMT
Links: << >>  << T >>  << A >>
I looked long and hard at Quicklogic a couple of years ago.

We needed to emulate an 8051 at quite fast rates and they had a
pretty good story.  We decided to stay with Xilinx in the end
for a single reason: the cost of the prototypes we would burn thru
while we got the very complex logic around the CPU working.  At
the time we were looking at UKP300 a chip and I expected to have to go through dozens of them
before it was right.  And losing the ability to fix screwups once
the device was at the customer also weighed heavily on my mind.

From your description you have a relatively small, well-defined
block to design with it and maybe these considerations will
not feature heavily with you, in which case, best of luck with 'em!

--
Posted using Nographer - News in your Browser
http://www.nographer.com - free, open source, and smart


Article: 34666
Subject: Re: FPGA : USB in an FPGA, has anyone done it before?
From: <jum>
Date: Sun, 2 Sep 2001 22:35:01 +0200
Links: << >>  << T >>  << A >>
Hi,
seems I read nothing about the software piece of such USB solutions.
Do you all have the USB stack/class software for this purposes?
Isnt that the main hurdle?
I want two PCs with USB (host) ports get connected as I did with the good
old (slow) RS-232.
The only thing I want to do ist something like X/Y/ZModem over USB (as over
RS-232, but much faster).
Are there any solutions for the software. We use RTOS on both sides, so we
need source code to get the stacks real timed.
Regards
Juergen



Article: 34667
Subject: Re: WebPack Con-Game
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Sun, 02 Sep 2001 15:08:48 -0600
Links: << >>  << T >>  << A >>
Kevin Brace wrote:
>         I won't call it a deception.
> Neither will I call WebPack a demo software.
> Like someone else said in the thread, do you expect Model
> Technology/Xilinx to give out their simulator for free without any
> limitations?

YES! For the basic system.
Other people NO! FPGA companies Yes. They make their money
selling FPGA's not with software.
How would you like to buy a Car and it only runs on a TRIAL
road? A hammer that can only hit 50 times?
Ben.
-- 
Standard Disclaimer : 97% speculation 2% bad grammar 1% facts.
"Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
Now with schematics.

Article: 34668
Subject: Re: WebPack Con-Game
From: kevinbraceusenet@hotmail.com (Kevin Brace)
Date: 2 Sep 2001 15:29:57 -0700
Links: << >>  << T >>  << A >>
"David Wright" <dwright@srtorque.com> wrote in message news:<Ybqj7.31607$4b5.801781@news6.giganews.com>...
> The "free" Xilinix Webpack should be classified as a Demo and not a real
> system to do even realistic small designs.
> 
> By the time you install the design and even a small test vector, you easily
> exceed the 500-line ModelSim Starter Design Limit.  There are even
> limitations on Test Bench and probably other portions of the package.
> 
> Xilinx needs to stop misleading its customers and tell them what they really
> need to know:
> 
>   What package is adequate to the design and what does it cost and will
> actually work?  We also need something that is supported and does not
> time-out before we are done with the design.
> 
>  To justify any design, the Engineer needs to know how much the tool will
> cost beforehand and not in the "oh, by the way, if you need a real
> system..."
> 
> Stop the deception - Xilinix


        I won't call it a deception.
Neither will I call WebPack a demo software.
Like someone else said in the thread, do you expect Model
Technology/Xilinx to give out their simulator for free without any
limitations?
Besides, the 500 line limitation you are talking about is a limitation
in which the speed of simulation starts to slow down after 500 lines
of code.
When you compile your design, you will see a warning on the screen
that says, "# WARNING: Design size of xxxxx statements exceeds
ModelSim XE-Starter recommended capacity. # Expect performance to be
adversly effected.", but the nice (?) part is that it won't stop you
from doing the simulation.
I recently simulated a 8000 gate design running at 33MHz, and
functional simulation took about a minute (exceeded the limit by 1445
statements), and the post-route simulation (exceeded the limit by
22430 statements) took about 40 minutes.
The computer I used has AMD-K6-2 380MHz as the microprocessor with
256MB RAM.
I suppose that 40 minutes for post-route simulation is pretty slow (it
will be interesting to see how long it will take to simulate the
design without the slowdown), but because it is free, I won't complain
about it.
       The post-route simulation gave me valuable information of the
quality of the synthesized logic.
When I did functional simulation of my design, everything was working
fine.
So, I did P&R (Place & Route), and programmed the PROM, but the design
will crash when I fire it up in a real system.
I made small modification to the design, did P&R, and programmed the
PROM, and I repeated all of these stpes at least 20 times, but it
didn't help.
After reading Xilinx Application Note 338 and WebPack's Tutorial, I
decided to do post-route simulation, and the post-route simulation
showed that an important control signal was at undefined state (StX)
instead of being asserted (St0) at the end of a transaction.
After making several more modification to the design, which didn't
help during post-route simulation, I decided to disable all the
optimizing options of the synthesis tool.
I did post-route simulation again, and this time the design gave me
results virtually identical to the results I got during functional
simulation (not quite identical because post-route simulation has
delays).
I programmed the PROM, and this time the designed worked perfectly in
a real system.
I guess what I learned here is that WebPack's synthesis tool (XST
Verilog Ver. D.27 which came with WebPack Design Entry WP3.3 V8.0) is
still buggy, therefore post-route simulation is crucial before firing
up the design in a real system.
        The device I targeted was 150k system gate Spartan II part
(XC2S150PQ208-5).
I think this part I used should be more than enough to fit sometime
small.
Also, you have to realize that WebPack itself doesn't require a
license (you need a login ID to download the files), and even though
ModelSim XE-Starter requires a license, it is a perpetual license, so
you don't have to worry about time limit.
I don't use HDLBencher or StateCAD, so I don't care what kind of
limitations they impose.
I wrote my own testbench script, so I don't see a reason using
HDLBencher.
I converted state-machine diagram to Verilog RTL in my head, so I
didn't have to use StateCAD to do that.
Although, I suppose that there may be some cases where those tools are
useful, but right now I don't need or care about them.
Since I got my design to work in a real world system, I can say that
WebPack is a complete set of working tools with some limitations.




Regards,



Kevin Brace (don't respond to me directly, respond within the
newsgroup)

Article: 34669
Subject: using non-standard eeprom to program xilinx fpga
From: "Daniel Nilsson" <danielnilsson@REMOVE_THIShem3.passagen.se>
Date: Mon, 3 Sep 2001 00:53:38 +0200
Links: << >>  << T >>  << A >>
Hi.
I wonder how I do generate the bitstream using webpack, when I want to load
a custom memory with it (some sort of serial EEPROM), is there specified
anywhere what is what inside the bitstream, and how it shall be loaded into
the fpga (in this case a spartan device)

/ Daniel Nilsson, M.Sc.EE student



Article: 34670
Subject: Re: DSP in OTP
From: Ray Andraka <ray@andraka.com>
Date: Mon, 03 Sep 2001 00:49:04 GMT
Links: << >>  << T >>  << A >>
Both Quick and Actel have a cell that is a collection of gates rather than a
look-up table.  This makes it quite a bit harder (but not impossible) to use
distributed arithmetic in the filter.  Provided your coefficients are known and
constant, you could build logic equivalents of the LUTs used in a DA filter to
realize a fairly compact filter in either of these architectures.  You could
also use memory (if the particular chip  has it, or an external memory) to hold
a bigger DA table..for a small filter you'd probably get out with a modest sized
memory.

If the coefficients need to be programmable, then you'll probably be best off
putting a fast multiplier in the fabric and using RAM to hold the coefficients,
more like a traditional processor based approach.  Quick logic has a version of
it's chip with a dedicated arithmetic core inteneded for DSP applications.  The
multiplier is fast (IIRC, over 300 MHz), but you only get a couple of them in
the biggest chips.  That one also helps because it takes care of the arithmetic
for you too.  That aside, neither Actel nor Quicklogic have native arithmetic
support, so you wind up building your adders without the benefit of a fast carry
chain.  You'll end up burning alot of FPGA resources and intellectual capital
making the arithmetic fast in these parts (with the exception of the arithmetic
cores in Quicklogic's DSP chip).

So the bottom line here, is yes you can do the filtering in either of these
families, but it may not be painless.  Does the filter have to be instant on, or
just some of the support logic around it?  Perhaps a small SRAM FPGA plus a CPLD
might fill the bill better (could be that you want a single chip replacement
that a third party could add to a board, in which case the antifuse FPGA or ASIC
appears to be the only choices).  If that is the case, how about a xilinx 4K
hardwire (not sure they are still doing those though).

pete dudley wrote:

> Hello All,
>
> I have a customer who wants to replace an analog signal processing ASIC with
> a digital fpga for flexibility.
>
> The analog ASIC contains some low pass filtering, i/q demodulation and
> integration operations. The filtering requires something like a 6th order
> IIR. Input data is 8 bits or less. Input sample rates are like 15Msps.
>
> All of this would be cake in a ram based fpga but it will be necesary  to
> use an OTP like Actel or Quicklogic for shelf life and instant-on reasons.
> Also we would like to keep the cost of the fpga below $20 because volume is
> significant (10K to 100K/yr).
>
> Could anyone offer advice about doing digital filtering in Actel or
> Quicklogic? Their web pages have only basic discussions of digital
> filtering. For example the Actel page only shows direct form implementations
> of FIR filters with no mention of transpose form filtering.
>
> I haven't given many details of my application so I'm just looking for
> general advice on feasibility and approach.
>
> Thank you,
>
> --
> Pete Dudley
>
> Arroyo Grande Systems

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34671
Subject: Virtex Architecture: Interconnect
From: Dereck <dereckaf@yahoo.com>
Date: Sun, 2 Sep 2001 18:05:49 -0700
Links: << >>  << T >>  << A >>
Hi
Guys do you have information about The Interconnect Routing in The Virtex Parts.
I am interested in knowing how many,
Long, single , double etc lines are present in a single tile in a Virtex part like XCV800.

2. I have seen how the routing looks in XC4000 Programmable Interconnect (Figure 27 Page 6-30).XC 4000 datasheet.
Such a picture is not available for XCV 800.
If you guys can help, Please write to me I will explain in more details.

Dereck 
dereckaf@yahoo.com

Article: 34672
Subject: Re: Virtex Architecture: Interconnect
From: Ray Andraka <ray@andraka.com>
Date: Mon, 03 Sep 2001 01:53:11 GMT
Links: << >>  << T >>  << A >>
There isn't a nice picture like there is for the 4K, but you can still glean most of the info from the databooks.
The best place to go though, if you have the tools, is into the FPGA editor.  It was that that finally made the
interconnect all clear.  Here is a summary of the routing:

Local CLB routing
        intra-CLB routing (first level switchbox)
        2 direct paths to horizontally adjacent CLBs
General purpose routing:
 Each CLB is associated with General Routing Matrix (a switchbox) which connects to:
        24 single length wires to adjacent GRMs in each of 4 directions
        96 buffered hex wires to GRMs 6 blocks away in 4 directions
                staggered pattern
                driven only at end points
                accessible at endpoints and midpoint
                1/3 are bidirectional, 1/3 unidirectionalleft/up and 1/3 unidirectional right/down
                vertical bidirectional hexes can connect to CLK, CE, SR and the tristate enables at every CLB
        12 Long lines
                buffered bidirectional wires, 2 connected at each GRM
                connections to GRMs at multiples of 6 rows/columns, staggered.
                vertical and horizontal lines span device
 Global Routing
        4 dedicated primary global nets driven by dedicated global buffers
        24 Horizontal backbones with connections to vertical long lines
I/O routing
        ‘Versa-Ring’ routing around chip periphery
        Extra routing resource to make pin placement less critical
Dedicated Routing
        4 Horizontal pseudo tri-state busses per CLB row
                    Partitionable for multiple busses in a row
                    Mux architecture mimics tri-state
                    Buffered so it is faster than tri-state
        Dedicated vertical fast carry connections




Dereck wrote:

> Hi
> Guys do you have information about The Interconnect Routing in The Virtex Parts.
> I am interested in knowing how many,
> Long, single , double etc lines are present in a single tile in a Virtex part like XCV800.
>
> 2. I have seen how the routing looks in XC4000 Programmable Interconnect (Figure 27 Page 6-30).XC 4000 datasheet.
> Such a picture is not available for XCV 800.
> If you guys can help, Please write to me I will explain in more details.
>
> Dereck
> dereckaf@yahoo.com

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 34673
Subject: Linux download bitstream [w/ source]
From: <khtsoi@pc90026.cse.cuhk.edu.hk>
Date: 3 Sep 2001 03:54:49 GMT
Links: << >>  << T >>  << A >>
Hi,

Thanks to the good ppl. in this news group, I can finally download the
bit stream to FPGA under Linux. I am here to share the experience (maybe
somebody have done it before but I could not find).

Environment:
1. Software
	Linux with kernel 2.2.17 (others whould work also)
	GNU gcc-2.95.2
2. Hardware
	Xilinx FPGA (I tried XCV600HQ240 and V1000EHQ240)
	Xilinx Parallel Cable III (DB25M head)
	six flying lead

Procedure:
1. connect the flying lead to Parallel Cable
	only the FPGA side is connected (i.e. VCC, GND, D/P, DIN, CCLK, /PROG)
2. connect the cable to a Linux computer and connect the leads to FPGA pins
		VCC	<-->	VCC
		GND	<-->	GND
		D/P	<-->	DONE
		DIN	<-->	DIN
		CCLK	<-->	CCLK
		/PROG	<-->	/PROG
	note that the /INT pin in FPGA is not connected
3. download and compile the source file (at the end of the document)
	use the following command (-O2 is a must)
	gcc -Wall -O2 -o w w.c
4. get ready the bitstream (*.bit) in the same directory of the program
	here assume the file name is "design.bit"
5. just involve the program after power up the FPGA
	make sure you are root when runing the command
	if the "DONE!" is printed, your design is downloaded correctly

Important:
1. I have only test it on Vertix/VertixE FPGA chips. This should also work
	on VertixII. Other families may not work (should not work since the
	programming requirements are differents)
2. The Parallel Cable III is not a must. you can make you only cable, check
	it out in the reference
3. Since the lack of /INT input to Linux host, the download process will not
	be interrupted by error(s). The initial stage is also not safe. But
	if Xilinx makes the cable and thinks it will work, who others will
	care that?
4. The DONE signal will tell the condition of program at the end. Since it's
	release only when CRC checking is passed, it can be trusted.
5. The download speed is quite fast (4-5 sec for XCV600HQ240 design) on a
	PIII700 PC.
6. User must be root to download the bitstream since the program use inb() and
	outb() to access the port directly. But you still have the choice to
	setuid and avoid logging in as root every time.
7. EPP mode is selected for this program. But it really don't matter. You can
	still run it in other modes.
8. This porgam is for development use only. Use it on your own risk.

Reference:
1. http://www.xilinx.com/support/programr/files/0380507.pdf
2. XAP137, XAP138, XAP138, XAP501
3. news from Alan Nishioka<alann@accom.com>
<--begin-->
However,  the format is pretty simple.  It uses keys and lengths to
divide the file.

2 bytes     length 0x0009 (big endian)
9 bytes     some sort of header (the length given above)
2 bytes     length 0x0001

1 byte      key 0x61
2 bytes     length 0x000a
10 bytes   string giving design name

1 byte      key 0x62
2 bytes     length 0x000c
12 bytes   string giving part name

1 byte       key 0x63
2 bytes      length 0x000b
11 bytes    string giving date

1 byte        key 0x64
2 bytes      length 0x0009
9 bytes      string giving time

1 byte                  key 0x65
2 bytes                 length 0x000c9090
8233440 bytes     raw bit stream starting with 0xffffffff aa995566 sync
word documented below.
<--end-->
4. Linux Device Driver p236 Fig.8
			Reg bit #	Direction	DB25 pin #
	Data Reg	0 - 7		---->		2 - 9
	Status Reg	3		<----		15
	Status Reg	4		<----		13
5. http://www.beyondlogic.org/epp/epp.htm

Source Code:
<--begin-->
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h> /* needed for ioperm() */
#include <sys/io.h>
//#include <asm/io.h> /* for outb() and inb() */

#define DATA 0x378
#define STATUS DATA+1
#define CONTROL DATA+2

int main(void) {
	FILE *bitfile;
	union {
		unsigned int i;
		unsigned short s[2];
		char c[4];
	} head_len;
	unsigned char head_key;
	char buf[2035464];

	unsigned int i;
	int j;
	unsigned char tmp;


	bitfile = fopen("design.bit", "r");
	fread(&(head_len.c[1]), 1, 1, bitfile);
	fread(&(head_len.c[0]), 1, 1, bitfile);
	fread(buf, head_len.s[0], 1, bitfile);
	fread(&(head_len.c[1]), 1, 1, bitfile);
	fread(&(head_len.c[0]), 1, 1, bitfile);

	head_key = 0;
	while (head_key != 0x65) {
		fread(&head_key, 1, 1, bitfile);
		fread(&(head_len.c[3]), 1, 1, bitfile);
		fread(&(head_len.c[2]), 1, 1, bitfile);
		if (head_key == 0x65) {
			fread(&(head_len.c[1]), 1, 1, bitfile);
			fread(&(head_len.c[0]), 1, 1, bitfile);
			fread(buf, head_len.i, 1, bitfile);
		}
		else {
			fread(buf, head_len.s[1], 1, bitfile);
			printf("%s\n", buf);
		}
	}

	fclose(bitfile);
	
	if (iopl(3)) {
		printf("cannot access port!\n");
		exit(1);
	}

	outb(0x04, CONTROL);

	// sense VCC
	tmp = inb(STATUS);
	tmp = (tmp>>3) & 1;
	if (!tmp) {
		printf("cabel not found\n");
		exit(0);
	}
	else
		printf("cabel detected\n");

	// clear config
	outb(0x10, DATA);
	printf("configuration memory cleared\n");
	outb(0x14, DATA);

	printf("start loading %d bytes\n", head_len.i);
	for (i=0; i<head_len.i; i++) {
		for (j=7; j>=0; j--) {
			tmp = (buf[i]>>j) & 1;
			outb(tmp|0x14, DATA);
			outb(tmp|0x16, DATA);
		}
	}
	printf("finish loading\n");

	// Done
	tmp = inb(STATUS);
	tmp = (tmp>4)&1;
	if (tmp)
		printf("DONE!\n");
	else
		printf("FAILED!\n");


	return (0);
}
<--end-->

Good Luck!

---- Brittle

Article: 34674
Subject: Segmented interconnects
From: Russell Shaw <rjshaw@iprimus.com.au>
Date: Mon, 03 Sep 2001 14:07:35 +1000
Links: << >>  << T >>  << A >>
Hi all,

What advantages/disadvantages do segmented-interconnect fpgas have over
continuous interconnect cplds?

Is there more flexibility in placing pins with segmentation?

A vs X:

  http://www.altera.com/literature/pib/pib18_01.pdf

--
   ___                                           ___
  /  /\                                         /  /\
 /  /__\ Russell Shaw, B.Eng, M.Eng(Research)  /  /\/\
/__/   / Victoria, Australia, Down-Under      /__/\/\/
\  \  /  http://home.iprimus.com.au/rjshaw    \  \/\/
 \__\/                                         \__\/



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