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Messages from 28550

Article: 28550
Subject: Re: Synplicity newsgroup?
From: Muzaffer Kal <muzaffer@dspia.com>
Date: 17 Jan 2001 00:34:31 GMT
Links: << >>  << T >>  << A >>
Rick Filipkiewicz <rick@algor.co.uk> wrote:

>
>
>Utku Ozcan wrote:
>
>> What happened to Synplicity's newsgroup?
>> The newsgroup browser tells that the server is down...
>>
>> Utku
>
>I've never been able to get to it either - I contacted Synplicity about
>this a long time ago but never got any result.
>
It's gone down just two days ago. There wasn't much traffic on it but
I have been able to access to it till then. For a short while web site
was down too but it came up, news didn't.

Muzaffer

FPGA DSP Consulting
http://www.dspia.com

Article: 28551
Subject: Re: FPGA driving clock line
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Tue, 16 Jan 2001 17:34:24 -0800
Links: << >>  << T >>  << A >>

--------------68EC4BA62900476F802CF76A
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353"
Content-Transfer-Encoding: 7bit

There seem to be three issues here:
1
Does  Spartan have enough drive to supply clocks to several chips?
Answer: yes, no problem
2
What happens during configuration?
Answer: Outputs are 3-stated, and internal logic is being held reset. Output
will be glitch-free if the user keeps it 3-stated until the clock multiplexer
is running properly. May take another internal flip-flop. But they are cheap.
3
How can I mux asynchronous clocks reliably, without glitches and runt output
pulses?
Answer: click on
http://www.xilinx.com/xcell/xl24/xl24_20.pdf

Peter Alfke, Xilinx Applications
=======================
"S. Ramirez" wrote:

> "Dean,
> It' hard to determine exactly what you are talking about.  Let me see if I
> have this right.  You have two Spartan II devices and three CPLDs.  You call
> one Spartan II device the "main" device, and you want logic on this device
> to select from two different input clocks for itself as well as the other
> Spartan II device and three CPLDs.
>
> This means that the main Spartan II will have two or more input clocks, and
> it is going to select the clock and drive itself as well as the other
> Spartan II and the three CPLDs.  I thnk that the following are applicable:
>    1.  You won't have a clock out of main Spartain II
>          until after configuration.  It could glitch, too.
>          Can you handle this?
>    2.  The logic selecting the clock is totally combinatorial
>         and not dependent on any of the clocks.
>   3.  You drive the selected clock to a IO pad and distribute
>         the clock to both Spartan IIs and CPLDs.
>   4.  The IO pad will be tristated and weakly pulled high.
>        You might want to pull it high with an external pull up
>         resistor.
>   5.  The clock network will probably have no termination
>        or a mild termination (pullup resistor?) due to the
>        Spartan II 24ma limit.  The clock may be 2 MHz, max,
>        but you still have to contend with those edges.
>   6.  You're not too worried about duty cycle.  At 2 MHz,
>         I think this would be true.
>
> Without having more information to work with, this is what I came up with.
> It would be nice to know how you are originally generating the clock, as the
> clock selection can be made there, too.
>
> With what you have, though, I would be tempted to select the clocks in the
> CPLDs, though, because they come right up after power on.
> Simon Ramirez, Consultant
> Synchronous Design, Inc.
> Oviedo, FL  USA

--------------68EC4BA62900476F802CF76A
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
There seem to be three issues here:
<br>1
<br>Does&nbsp; Spartan have enough drive to supply clocks to several chips?
<br>Answer: yes, no problem
<br>2
<br>What happens during configuration?
<br>Answer: Outputs are 3-stated, and internal logic is being held reset.
Output will be glitch-free if the user keeps it 3-stated until the clock
multiplexer is running properly. May take another internal flip-flop. But
they are cheap.
<br>3
<br>How can I mux asynchronous clocks reliably, without glitches and runt
output pulses?
<br>Answer: click on
<br><u><A HREF="http://www.xilinx.com/xcell/xl24/xl24_20.pdf">http://www.xilinx.com/xcell/xl24/xl24_20.pdf</A></u>
<p>Peter Alfke, Xilinx Applications
<br>=======================
<br>"S. Ramirez" wrote:
<blockquote TYPE=CITE>"Dean,
<br>It' hard to determine exactly what you are talking about.&nbsp; Let
me see if I
<br>have this right.&nbsp; You have two Spartan II devices and three CPLDs.&nbsp;
You call
<br>one Spartan II device the "main" device, and you want logic on this
device
<br>to select from two different input clocks for itself as well as the
other
<br>Spartan II device and three CPLDs.
<p>This means that the main Spartan II will have two or more input clocks,
and
<br>it is going to select the clock and drive itself as well as the other
<br>Spartan II and the three CPLDs.&nbsp; I thnk that the following are
applicable:
<br>&nbsp;&nbsp; 1.&nbsp; You won't have a clock out of main Spartain II
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; until after configuration.&nbsp;
It could glitch, too.
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Can you handle this?
<br>&nbsp;&nbsp; 2.&nbsp; The logic selecting the clock is totally combinatorial
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; and not dependent on any
of the clocks.
<br>&nbsp; 3.&nbsp; You drive the selected clock to a IO pad and distribute
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; the clock to both Spartan
IIs and CPLDs.
<br>&nbsp; 4.&nbsp; The IO pad will be tristated and weakly pulled high.
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; You might want to pull it high
with an external pull up
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; resistor.
<br>&nbsp; 5.&nbsp; The clock network will probably have no termination
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; or a mild termination (pullup
resistor?) due to the
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Spartan II 24ma limit.&nbsp; The
clock may be 2 MHz, max,
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; but you still have to contend
with those edges.
<br>&nbsp; 6.&nbsp; You're not too worried about duty cycle.&nbsp; At 2
MHz,
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I think this would be true.
<p>Without having more information to work with, this is what I came up
with.
<br>It would be nice to know how you are originally generating the clock,
as the
<br>clock selection can be made there, too.
<p>With what you have, though, I would be tempted to select the clocks
in the
<br>CPLDs, though, because they come right up after power on.
<br>Simon Ramirez, Consultant
<br>Synchronous Design, Inc.
<br>Oviedo, FL&nbsp; USA</blockquote>
</html>

--------------68EC4BA62900476F802CF76A--


Article: 28552
Subject: Re: FPGA driving clock line
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Tue, 16 Jan 2001 17:48:22 -0800
Links: << >>  << T >>  << A >>
Dean, now that you let us in on your real plans, let me give some advice:
Do not source two different clocks, but rather build a simple internal switch
differentiator and gate the clock for one period.

Better yet, let the clock run freely, and use the FPGA to create a
one-clock-period Enable signal when you want to single step. Driven by a simple
state machine in less than one CLB, this is the solution that will give you the
least trouble ( none at all)

Peter Alfke
===========================
Dean Armstrong wrote:

> Hi Simon,
>
> Thanks for your reply.
>
> You understood me correctly.
>
> The intention is that one clock source be a crystal oscillator at about 2MHz,
> the other will be a push button (which will be debounced in programmable logic
> somewhere). A third input (an on/off switch) will select between the two. This
> will allow the devices to run on the clock or be switched into a single-step
> mode.
>
> Basically, what I am designing is a computer system that can free-run, or be
> switched into a mode where the CPU and bus operations are single stepping. Some
> of these devices (eg UART, programmable timer) will still need the high speed
> clock to perform their operations correctly, but all bus transactions with them
> will be single stepped.
>
> Thanks,
> Dean
>
> "S. Ramirez" wrote:
>
> > "Dean Armstrong" <daa1@cs.waikato.ac.nz> wrote in message
> > news:3A64DFBC.A895C809@cs.waikato.ac.nz...
> > > Sorry,  I also forgot to mention that this will only be operating at low
> > > frequencies (~2MHz).
> > >
> > > Dean Armstrong wrote:
> > >
> > > > Hi All,
> > > >
> > > > Is it possible to drive a clock line for a Spartan II device and three
> > > > Xilinx XC9500XL CPLD devices from a user IO pin on another Spartan II.
> > > > The application is one where I want logic within the main Spartan to
> > > > select between two different input clocks. To be used for itself and the
> > > > other devices.
> > > >
> > > > Thanks
> > > > Dean Armstrong
> >
> > Dean,
> > It' hard to determine exactly what you are talking about.  Let me see if I
> > have this right.  You have two Spartan II devices and three CPLDs.  You call
> > one Spartan II device the "main" device, and you want logic on this device
> > to select from two different input clocks for itself as well as the other
> > Spartan II device and three CPLDs.
> >
> > This means that the main Spartan II will have two or more input clocks, and
> > it is going to select the clock and drive itself as well as the other
> > Spartan II and the three CPLDs.  I thnk that the following are applicable:
> >    1.  You won't have a clock out of main Spartain II
> >          until after configuration.  It could glitch, too.
> >          Can you handle this?
> >    2.  The logic selecting the clock is totally combinatorial
> >         and not dependent on any of the clocks.
> >   3.  You drive the selected clock to a IO pad and distribute
> >         the clock to both Spartan IIs and CPLDs.
> >   4.  The IO pad will be tristated and weakly pulled high.
> >        You might want to pull it high with an external pull up
> >         resistor.
> >   5.  The clock network will probably have no termination
> >        or a mild termination (pullup resistor?) due to the
> >        Spartan II 24ma limit.  The clock may be 2 MHz, max,
> >        but you still have to contend with those edges.
> >   6.  You're not too worried about duty cycle.  At 2 MHz,
> >         I think this would be true.
> >
> > Without having more information to work with, this is what I came up with.
> > It would be nice to know how you are originally generating the clock, as the
> > clock selection can be made there, too.
> >
> > With what you have, though, I would be tempted to select the clocks in the
> > CPLDs, though, because they come right up after power on.
> > Simon Ramirez, Consultant
> > Synchronous Design, Inc.
> > Oviedo, FL  USA


Article: 28553
Subject: Re: FPGA driving clock line
From: "S. Ramirez" <sramirez@deletethis.cfl.rr.com>
Date: Wed, 17 Jan 2001 02:16:49 GMT
Links: << >>  << T >>  << A >>
"Dean Armstrong" <daa1@cs.waikato.ac.nz> wrote in message
news:3A64E669.5A49690A@cs.waikato.ac.nz...
> Hi Simon,
>
> Thanks for your reply.
>
> You understood me correctly.
>
> The intention is that one clock source be a crystal oscillator at about
2MHz,
> the other will be a push button (which will be debounced in programmable
logic
> somewhere). A third input (an on/off switch) will select between the two.
This
> will allow the devices to run on the clock or be switched into a
single-step
> mode.
>
> Basically, what I am designing is a computer system that can free-run, or
be
> switched into a mode where the CPU and bus operations are single stepping.
Some
> of these devices (eg UART, programmable timer) will still need the high
speed
> clock to perform their operations correctly, but all bus transactions with
them
> will be single stepped.
>
> Thanks,
> Dean

Good luck, Dean.  What you are doing sounds relatively simple, yet you can
be stepping on some mines here.  I would make sure to use an excellent
debounce circuit as well as verify that all components running on the slow
push button frequency can go to 0 Hz.
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL  USA



Article: 28554
Subject: Re: Virtex-II officially launched
From: Terry Hicks <hicksthe@egr.msu.edu>
Date: Tue, 16 Jan 2001 21:57:47 -0500
Links: << >>  << T >>  << A >>


Rick Filipkiewicz wrote:

> Peter Alfke wrote:Sorry for the blatant propaganda. Got carried away by
> my enthusiasm.
>
> >
> > I had been impatiently waiting for the Ides of January, for a long
> > time !
> >
> > Peter Alfke, Xilinx Applications
> > =====================================
>
> Peter,
>
> Sorry to sound a dampening note here among all the enthusiasm but a real
> world question occurs:
>
> Are Xilinx going to avoid the SpartanII mistake of letting a few major
> customers soak up all the Virtex-II production leaving those of us
> reliant on the disti's completely out of luck ? [lead time > 20 weeks =>
> no design in]
>
> [Anybody remember Ray's joke about the SpartanII T-shirt ?]

I have to second Rick's comment.  How about it?  No small quantities= no
design in.  I am currently designing a device which would benefit from a
small Virtex-E device due to the LVPECL i/o capability.  I don't think I
will use one, as I cannot trust the availability of the Virtex-E parts.  I
really like the Xilinx parts and the fact the real Xilinx people actually
read the news groups and reply.  Three cheers for Peter and Austin (and any
one else who I may have forgotten or missed.)  The available support is a
strong positive for Xilinx.  That and the fact that Xilinx has good
university support are the reason that I am using a SpartanXL in my current
design.  Currently I am working in a university setting and use small
quantities.  Someday I may be designing for systems with production runs of
100's of thousands instead of just 100's.  Needless to say I will remember
those who took the time to support the little guy.  I also will remember the
distributors and manufacturers who let the big guys take all the parts and
wouldn't support the little guys.  I hope Xilinx remains in the good camp.
Linear Tech and Analog Devices are in the use only if ABSOLUTELY necessary
group due to extremely long lead times.  In comparision, the 3 to 4 weeks
quoted for XCS05XL's is reasonably bearable.  (Stock would be even better.)

Thanks,
Theron Hicks


Article: 28555
Subject: Re: How to implement a 5-variable function in a CLB?
From: "Kwong Chan" <kwong_chan@hongkong.com>
Date: Wed, 17 Jan 2001 11:34:23 +0800
Links: << >>  << T >>  << A >>
> In the worst case, have you not used map with -k option?
>
> Utku
>

The -k option means for what?

You mean
    compile -k <design_name>  ??

kwong,



Article: 28556
Subject: Re: FPGA driving clock line
From: murray@pa.dec.com (Hal Murray)
Date: 17 Jan 2001 05:56:49 GMT
Links: << >>  << T >>  << A >>

> Is it possible to drive a clock line for a Spartan II device and three
> Xilinx XC9500XL CPLD devices from a user IO pin on another Spartan II.
> The application is one where I want logic within the main Spartan to
> select between two different input clocks. To be used for itself and the
> other devices.

I think there are two issues here.  The first is generating a clock
from a Spartan.  The second is making right logic inside a Spartan
to cleanly switch between clocks.

I don't know of any special problems with generating a clock on a
Spartan - just the standard problems of rise time, reflections,
and skew.  If you have enough pins, I'd suggest one pin per clock
and series terminate.

Cleanly switching clocks seems as though it should be a standard
problem.  But I don't remember seening an example.

  My straw man would be a small FSM with 3 states - clock1, clock2,
  idle.  When you want to switch, you go from clock1 to idle using
  logic clocked by clock1.  Then you run the idle signal through
  a synchronizer and go to the clock2 state ising logic clocked by
  clock2.

Another msg said the second clock was just to get single-stepping
on some logic.  In that case, you might leave the clock running all
the time and just use a clock-enable for the logic that needs it.
-- 
These are my opinions, not necessarily my employers.  I hate spam.

Article: 28557
Subject: Re: revision control tools ??
From: Steve O'Hara-Smith <steve@ams-gw.sohara.org>
Date: Wed, 17 Jan 2001 08:01:16 +0100
Links: << >>  << T >>  << A >>
In comp.arch.fpga Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote:

> hamish@cloud.net.au (Hamish Moffatt VK3SB) writes:
>> Sure, but ClearCase is much better. For one thing, because it
>> has a custom virtual file system on the client (MVFS -- multi version
>> file system) it can do a lot of things which CVS can't do.

	CVS is much better than Clearcase when you have many developers
geographically separated. Add cvsup to the kit and it is very hard
to beat for that case.

Article: 28558
Subject: FSM encoding
From: elmoties@hotmail.com
Date: Wed, 17 Jan 2001 07:11:11 GMT
Links: << >>  << T >>  << A >>
Hi,

I'm designing an arithmetic accelerator for the Xilinx Virtex 50K.

I'm having trouble synthsizing a design that I thought would fit with no
problems.  Xilinx's ISE 3.1i reports only using about 10500 gates but it
requires 99% of the slices on the FPGA.

The design is a large FSM that has about 30 states.  There is four
registers (idealing I want to have > 128 bit) that have operations
performed between them (xor, shifting with feedback) in several of the
states.  Most of the other states just before trivial signaling for
memory loading.

Several of the states have case statements contained with-in them to
determine when to peform specific operations.

My questions: (I'm more than willing to post more information if
somebody wants it)

Do FPGA's have an inherently hard time laying out large FSM's?
Is there a particular FSM encoding that is better than others for space
considerations?
Is having nested states (via cases statements inside a state) a bad
thing for compact sythesizing?
Is having nonstandard signal sizes that are quite large ( greater than
128 bit) really difficult to place and route on an FPGA

Thanks,

Jeff Elmot


Sent via Deja.com
http://www.deja.com/

Article: 28559
Subject: Re: How to implement a 5-variable function in a CLB?
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Wed, 17 Jan 2001 09:28:17 +0200
Links: << >>  << T >>  << A >>
Kwong Chan wrote:

> > In the worst case, have you not used map with -k option?
> >
> > Utku
> >
>
> The -k option means for what?
>
> You mean
>     compile -k <design_name>  ??
>
> kwong,

Xilinx has executable "map", used for technology
mapping phase for implementation. If you are
working on Sun Solaris, it is in

$XILINX/bin/sol/map

This executable has the -k option, which tells the
tool to map the functions with 4/5/6 inputs.

Utku



Article: 28560
Subject: Rconfiguration of FPSLIC
From: xgeorg@my-deja.com
Date: Wed, 17 Jan 2001 07:46:57 GMT
Links: << >>  << T >>  << A >>
Hi,
 I have some questions about the reconfiguration of the Atmel FPSLIC,
has anybody worked with that yet?
 How can I "trigger" the fpga  to reconfigure, especially how can I
come to mode 4 ??
 What about the 4 bit TAG and the other ???
 Are there any AVR routines for reconfiguration of fpga ?
 Any help appreciated
 Thanks a lot
 georg heinrich



Sent via Deja.com
http://www.deja.com/

Article: 28561
Subject: Re: Foundation P&R + location constraint
From: Michael Boehnel <boehnel@iti.tu-graz.ac.at>
Date: Wed, 17 Jan 2001 09:14:45 +0100
Links: << >>  << T >>  << A >>
Hi, Rick!

Rick Filipkiewicz wrote:

> Michael Boehnel wrote:
>
> > Hi!
> >
> > When I start a new design with partially coded (not yet fully
> > implemented) black boxes and location constraints for a fixed pin
> > assignment I often have the problem that the unused pins are optimized
> > away by the synthesis tool. This results in an error of the place&root
> > tools since the location constraint can't be met.
> >
> > Is it really necessary that the P&R tool results in an error if a pin in
> > the constraint file isn't existent? I think a warning would be enough so
> > that I don't have to set extra attributes in the VHDL/Verilog code!?
> >
> > Whats' the easiest way to prevent that (yet) unused pins are optimized
> > away?
> >
> > Thanks,
> >
> > Michael
>
> The easiest way is to temporarily change all the pins to outputs & drive
> them either to 0 or - better - to the value of one of the already defined
> inputs.

This will be a problem if you already have a signal of an external IC at this
input (short circuit). At the moment my "easiest" way is the following: I
reserve one ore more output pins and connect one ore more yet unused inputs
directly or via a logical operation (AND,..) to the output pin(s).

Michael


Article: 28562
Subject: Re: Oscillator for FPGA - low cost
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: 17 Jan 2001 08:30:41 GMT
Links: << >>  << T >>  << A >>
Mladen Veselic <veselic@eunet.yu> wrote:
: Hello,

: I know this is a little off topic ...

: FPGA that I'm using have CMOS threshold on CLK input. Vtrh=3.1v and
: Vtrl=1,3v ( 5V supply ).
: Standard Quartz oscillator build with TTL gates inside can reach these
: thresholds on lower frequencies <10MHz. On higher frequencies amplitude
: drops and threshold are not reached or, in some cases, FPGA is randomly
: triggered. Also CLK input have very low impendance.
: I have build my own quartz oscillator with BF246 transistor but it requires
: 30V to archive 3Vpp output when  loaded with FPGA.
: Can anybody give me an advice how to implement crystal oscillator with:
: - output amplitude >2.5 v
: - work with crystals from 1MHz  to  ~50 MHz ( fundamental frequency )
: - high fanout
: - without expensive special components.

Quicklogic has an application note to build an oscillator with their
technology 

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 28563
Subject: Re: Xilinx UCF/ngdbuild problem
From: Nicolas Matringe <nicolas.matringe@IPricot.com>
Date: Wed, 17 Jan 2001 10:04:43 +0100
Links: << >>  << T >>  << A >>
> Hi There Nicholas,

Hi Rick


> One possibility that has happened to me before is that the real
> error is in the line *before* the one that NGDBUILD complains
> about.

I don't think it's the problem here since the error disappears when I
comment the line out.
The solution Utku gave yesterday works fine.

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01      http://www.IPricot.com/

Article: 28564
Subject: Re: Rconfiguration of FPSLIC
From: "Ulf Samuelsson" <ulf@atmel.dot.com>
Date: Wed, 17 Jan 2001 10:24:00 +0100
Links: << >>  << T >>  << A >>
Send the question to fpslic@atmel.com

--=20
Best Regards
Ulf at atmel dot com
These comment are intended to be my own personal view
and may or may not be shared by my Employer Atmel Sweden.


<xgeorg@my-deja.com> skrev i meddelandet =
news:943ilh$anl$1@nnrp1.deja.com...
: Hi,
:  I have some questions about the reconfiguration of the Atmel FPSLIC,
: has anybody worked with that yet?
:  How can I "trigger" the fpga  to reconfigure, especially how can I
: come to mode 4 ??
:  What about the 4 bit TAG and the other ???
:  Are there any AVR routines for reconfiguration of fpga ?
:  Any help appreciated
:  Thanks a lot
:  georg heinrich
:=20
:=20
:=20
: Sent via Deja.com
: http://www.deja.com/


Article: 28565
Subject: Re: revision control tools ??
From: hamish@cloud.net.au (Hamish Moffatt VK3SB)
Date: Wed, 17 Jan 2001 10:00:55 GMT
Links: << >>  << T >>  << A >>
In comp.lang.vhdl Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote:
> hamish@cloud.net.au (Hamish Moffatt VK3SB) writes:
>> Sure, but ClearCase is much better. For one thing, because it
>> has a custom virtual file system on the client (MVFS -- multi version
>> file system) it can do a lot of things which CVS can't do.

> On the other hand, depending on a special file system is also a
> disadvantage.  It's not portable, and it prevents you from using
> some tools that are available for normal file systems.

Perhaps; I haven't seen an example of this yet. It's a virtual file
system; the actual files are stored on the normal NT file system,
either on the server (VOB storage) or in view storage.

> CVS has some deficiencies, but for most projects it works
> quite well.

Well, I like not having to have a complete copy of everything
in the repository, as in CVS (or a ClearCase snapshot view);
I don't need most of it, and the LAN is fast enough. It saves
me disk space, and means I don't have to remember to update it
regularly.


Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 28566
Subject: Re: Altera Jam player on SHARC
From: steve (Steve Rencontre)
Date: Wed, 17 Jan 2001 10:46 +0000 (GMT Standard Time)
Links: << >>  << T >>  << A >>
In article <Xns902A7C0CFshivawellcom@207.126.101.100>, shiva@well.com 
(Kenneth Porter) wrote:

> Yuri G Tregubov <ytregubov@my-deja.com> wrote in 
> <93uk2f$3ou$1@nnrp1.deja.com>:
> 
> >Has anybody ported Altera Jam player to the
> >SHARC platform ? What are the main pitfalls?
> 
> I haven't ported Jam (I do use it on a PC) but I have ported 80186 
> code. I can tell you that the main issue is the 8/32 bit difference in 
> chars and code that expects that chars are one byte wide. In 
> particular, look out for code that expects that casting to (char) will 
> reduce a 32 bit value to 8 bits. For this I've defined a macro 
> MASK_TO_8_BITS(v) which, for byte-like processors, just does a cast to 
> char and, for the SHARC (with 32-bit chars), performs a mask with 0xFF.

Also watch out for any code that assumes four chars and one long have the 
same memory footprint. In a similar vein, while the Sharc does not have 
any concept of endianness, peripherals connected to it may, and may not 
necessarily all be the same!

--
Steve Rencontre		http://www.rsn-tech.co.uk
//#include <disclaimer.h>


Article: 28567
Subject: Re: revision control tools ??
From: Petter Gustad <dev.null@dev.null.org>
Date: 17 Jan 2001 11:49:59 +0100
Links: << >>  << T >>  << A >>
hamish@cloud.net.au (Hamish Moffatt VK3SB) writes:

> In comp.lang.vhdl Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote:
> Well, I like not having to have a complete copy of everything
> in the repository, as in CVS (or a ClearCase snapshot view);

You don't need to check out everything from a CVS repository. You can
pick whatever you want. You can also include an alias in the modules
file to make an abbreviation for sets of modules you use frequently.

Petter
-- 
________________________________________________________________________
Petter Gustad       8'h2B | (~8'h2B) - Hamlet      http://www.gustad.com
#include <stdio.h>/* compile/run this program to get my email address */
int main(void) {printf ("petter\100gustad\056com\nmy opinions only\n");}

Article: 28568
Subject: Re: Stereo vision on Virtex
From: Steven Derrien <sderrien@irisa.fr>
Date: Wed, 17 Jan 2001 12:08:53 +0100
Links: << >>  << T >>  << A >>


Sven Fleck wrote:
> 
> > The thing is that there would be no reason (except power consumption) to
> > implement correlation based approach in an FGPA since you can already
> > get real-time in sowtware with recent CPUs or DSPs...

> This sounds not possible in my eyes for large resolutions

It's Ok for up to 640*480 (most hi-res CCd camera have this resolution)
on a recent MMx 

> complete-image-disparities 

What do you mean by complete image disparity ? Searching for corelation
along a full line ?

> with more sophisticated filters, 

> as in http://www.ai.sri.com/~konolige/papers/svm.pdf only relatively small images
> have been taken (320x240, 32 disparities). 

> I believe that this problem maps
> far better to an FPGA design than to a DSP.

Some step do map well on a FPGA some others are more difficult to handle 
(consider for example the camera calibration problem).

Besides since the problem is easy to partition for a multi DSP plaform
implementation (each DSP handle a part of the images), this makes
another point in favour of DSP.

To my mind, if you're considering to use a real-time stereo-vison kernel
on a mobile 
robot then the FPGA is a good bet because of power consumption issues. 
Otherwise, just because of design time, you'd better stick to DSPs.



Steven

Article: 28569
Subject: Re: Virtex-II officially launched
From: "Gary Watson" <gary2@nexsan.com>
Date: Wed, 17 Jan 2001 11:44:35 -0000
Links: << >>  << T >>  << A >>
In a volume production environment, is there any way to load a unique serial
number into a Virtex-II?  (Assuming that this is a SOC application where
there is no external microprocessor...)

--

Gary Watson
gary2@nexsan.com  (you should leave off the digit two for email)
Nexsan Technologies Ltd.
Derby DE21 7BF  ENGLAND
UK-based Engineers: See our job postings at
http://www.nexsan.com/pages/careers.htm

"Rune Baeverrud" <fpga@no.spam.iname.com> wrote in message
news:979567585.218715@news2.cybercity.dk...
> Hello,
>
> Xilinx Virtex-II has now been officially announced.
>
> Check out the press release:
> http://www.xilinx.com/prs_rls/vtx2ship.htm
>
> and the Virtex-II Handbook:
> http://www.xilinx.com/products/virtex/handbook/index.htm
>
> Some highlights are:
> - digitally controlled impedances for input and output pins
> - new resources for clock management and clock synthesis
> - digital spread spectrum clocking
> - encrypted bitstreams
> - dedicated multipliers
>
> Go and see for yourself!
>
> Regards,
> Rune Baeverrud
>
>
>



Article: 28570
Subject: Re: revision control tools ??
From: eml@riverside-machines.com.NOSPAM
Date: Wed, 17 Jan 2001 11:48:40 GMT
Links: << >>  << T >>  << A >>
On Sun, 14 Jan 2001 19:58:53 GMT, strshn99@my-deja.com wrote:

>Dear Gurus,
>
>I have a newbie question to ask you.  What kind of Revision control
>tools do you use when you are working on a design?  Any recommendation
>as to which is better?

I don't think anyone's mentioned MKS's SI, or Microsoft's Sourcesafe.
I've used MKS, RCS (with a CS-RCS frontend), and CVS (currently with a
WinCVS frontend, over ssh). Of these, MKS is much the best, but it's
the only one you have to pay for. I've also heard good things about
Clearcase. I'd say if you're doing real commercial work then a good
source control tool is pretty much top of the shopping list, and has
to be paid for.

CVS is pretty much the standard, but it's not for anyone who's got
better things to do than trawl through obscure documentation, and
control hundreds of files with an antiquated command line interface.
WinCVS does a good job of making CVS more usable, but it's not really
finished yet, and it's nowhere near as good as MKS. Security is also a
problem.

Evan

Article: 28571
Subject: Re: CRC - from long division to XOR, how?
From: eml@riverside-machines.com.NOSPAM
Date: Wed, 17 Jan 2001 11:50:12 GMT
Links: << >>  << T >>  << A >>
On Mon, 15 Jan 2001 15:31:29 -0500, "Jamie Sanderson"
<jamie@nortelnetworks.com> wrote:

>I will continue searching for the elusive app note... Sounds like just the
>thing I need.
>
>Regards,
>Jamie

Found it - 'Implementing parallel CRC for reliable high-speed
point-to-point communication using TAXI', AMD pub.#12572. There's not
much more than you already know. It doesn't seem to be on the website,
so I've scanned the relevant 3 pages to:

www.riverside-machines.com/pub/AMD_12572.zip

Have fun -

Evan

Article: 28572
Subject: CMOS or TTL
From: erika_uk@my-deja.com
Date: Wed, 17 Jan 2001 12:40:00 GMT
Links: << >>  << T >>  << A >>
hello,

which provides better performance CMOS or TTL based devices?
I believe that CMOS gives better performance, and it's the CMOS based
devices which are more expensive...but my friend told me the inverse ?

but what let the better to be better ?
are all fpga based CMOS devise ?

any input  ?

--Erika


Sent via Deja.com
http://www.deja.com/

Article: 28573
Subject: Re: revision control tools ??
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Wed, 17 Jan 2001 13:18:34 +0000
Links: << >>  << T >>  << A >>


eml@riverside-machines.com.NOSPAM wrote:

<snip>

> CVS is pretty much the standard, but it's not for anyone who's got
> better things to do than trawl through obscure documentation, and
> control hundreds of files with an antiquated command line interface.


^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

<pins>


Not if you use emacs + the p-cvs package.


Article: 28574
Subject: Re: revision control tools ??
From: Petter Gustad <dev.null@dev.null.org>
Date: 17 Jan 2001 15:35:10 +0100
Links: << >>  << T >>  << A >>
eml@riverside-machines.com.NOSPAM writes:

> On Sun, 14 Jan 2001 19:58:53 GMT, strshn99@my-deja.com wrote:
> 
> >Dear Gurus,
> >
> >I have a newbie question to ask you.  What kind of Revision control
> >tools do you use when you are working on a design?  Any recommendation
> >as to which is better?
> 
pushd> I don't think anyone's mentioned MKS's SI, or Microsoft's Sourcesafe.
> I've used MKS, RCS (with a CS-RCS frontend), and CVS (currently with a
> WinCVS frontend, over ssh). Of these, MKS is much the best, but it's

What kind of functionality does MKS provide that CVS do not?

> CVS is pretty much the standard, but it's not for anyone who's got
> better things to do than trawl through obscure documentation, and
> control hundreds of files with an antiquated command line interface.

Personally I don't like specilized GUIs to work against my revision
control system. Most of the time I use CVS from within emacs (the vc
interface) and the command line interface (from bash) when doing bulk
type work (e.g. tagging source trees) or from scripts.

> WinCVS does a good job of making CVS more usable, but it's not really

You mean it's more usable because it provides a GUI or does it add
functionality?

I work mainly in a Solaris/Linux environment and I'm very happy with
CVS. However, I had some problems with the Windows port of CVS. Today
I tried to check in a netlist and I got:

cvs server: Up-to-date check failed for `PSB63.edf'
cvs [server aborted]: correct above errors first!

I had to transfer the files over to Solaris and check them in from
there...

> finished yet, and it's nowhere near as good as MKS. Security is also a
> problem.

What's the problem with the CVS/ssh combo? 

Petter
-- 
________________________________________________________________________
Petter Gustad       8'h2B | (~8'h2B) - Hamlet      http://www.gustad.com
#include <stdio.h>/* compile/run this program to get my email address */
int main(void) {printf ("petter\100gustad\056com\nmy opinions only\n");}



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