Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 29875

Article: 29875
Subject: Re: Again Spartan II power
From: Magnus Homann <d0asta@licia.dtek.chalmers.se>
Date: 14 Mar 2001 23:41:03 +0100
Links: << >>  << T >>  << A >>
"R Sefton" <rsefton@home.com> writes:

> Austin -
> 
> A little more information if it helps. The 2.5V supply ramp-up was
> very fast (a few hundred microseconds. T

[...]

> I know the 2.5V rise was much faster than the 2ms min recommended in
> the datasheet, but my understanding was that the fast rise would
> increase current draw but cause no other problems. Is that true
> assuming the 2.5V regulator can handle it?


My understanding is that the minimum current requirment
might change. Maybe you would have to supply 2A instead. Can your power
supply do that?

Did you try slowing down the Vccint ramp, without changing the timing?

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se


Article: 29876
Subject: Re: Metastability
From: Magnus Homann <d0asta@licia.dtek.chalmers.se>
Date: 15 Mar 2001 00:08:01 +0100
Links: << >>  << T >>  << A >>
Ray Andraka <ray@andraka.com> writes:

> It does matter if you've used up most of your clock cycle in routing & logic
> delays.  I

That's the time between FF1 and FF2. It can be different for different designs.

> It all comes down to clock rate, or more specifically, the slack time before the
> data is clocked into the next flip-flop.  If you have plenty of slack, one
> flip-flop will usually do it.  If not, then be careful!

I think this was what I said?

Basically there are two issues:
1) Metastability
2) Two registers to a FSM depending on the same asynch. input, and thuis getting different values - depending on routing delay - without any metastability.

One FF wil solve the second problem for all cases.  No amount of FFs
will completely solve the first problem.  Depending on your design one
to ifinite amount of FFs wil solve both problems sufficiently.

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se

Article: 29877
Subject: Re: Metastability
From: Magnus Homann <d0asta@licia.dtek.chalmers.se>
Date: 15 Mar 2001 00:10:29 +0100
Links: << >>  << T >>  << A >>

I was unclear. I DID mean slack time between FFs. Honestly!

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se


Article: 29878
Subject: Re: Metastability
From: Magnus Homann <d0asta@licia.dtek.chalmers.se>
Date: 15 Mar 2001 00:21:49 +0100
Links: << >>  << T >>  << A >>

Just one more comment. Withouting setting timing constraints - and
checking them! - you cannot know if going to one or going to two FFs
will give you more or less slack. Depends on where the FFs are
located, routing resources used and the clock cycle.

If you are using a rule of thumb, you should really know why and when
it does and doesn't apply.

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se


Article: 29879
Subject: Re: Metastability
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Thu, 15 Mar 2001 00:51:02 +0000
Links: << >>  << T >>  << A >>


Magnus Homann wrote:

> Just one more comment. Withouting setting timing constraints - and
> checking them! - you cannot know if going to one or going to two FFs
> will give you more or less slack. Depends on where the FFs are
> located, routing resources used and the clock cycle.
>
> If you are using a rule of thumb, you should really know why and when
> it does and doesn't apply.
>
> Homann
> --
> Magnus Homann, M.Sc. CS & E
> d0asta@dtek.chalmers.se

When I was suggesting a rule of thumb I was thinking of one that can be
used automatically, via a perl script, to derate the synchroniser FF
constraints in a device/speed-grade/technology dependant way.


Article: 29880
Subject: Re: NIOS 16-Bit
From: "Vitaliy Tkachenko" <vit@telus.net>
Date: Thu, 15 Mar 2001 06:11:31 GMT
Links: << >>  << T >>  << A >>
Marco,
Today I've received a letter from Altera regarding Nios. They mentioned that
an upgrade is available on their Web site, and besides other things it
improves much the 16-bit Nios implementation.
Vitaliy.

"Marco Landert" <e-mail@landert.org> wrote in message
news:3AAF4EB3.12F3288B@landert.org...
> dear all,
>
> has anyone experience in writing c-code for a nios system from altera?
> i'm writing c-code for a 16-bit nios system and there are many
> problems...
> for example the interrupt-handling and of course the simulation of the
> source code. i'm also  searching a simulator for this system. at the
> moment, i'm using modelSim (for timing-diagram), but a gui-tool would be
> better and less time-intensive.
> has anyone example-programs for a 16-bit nios system? especially with a
> pio-interface and isr's.
>
> or general, has anyone experience in developing a 16-bit nios system?
>
> thank's for answers
>
> marco
>



Article: 29881
Subject: Re: NIOS 16-Bit
From: "Wolfgang Loewer" <wolfgang.loewer@elca.de>
Date: Thu, 15 Mar 2001 11:04:33 +0100
Links: << >>  << T >>  << A >>
Marco,

have you looked at the documents in
C:/cygwin/usr/altera/excalibur/nis-sdk/technotes/
They are a little hidden, but quite helpful, especially the document
"NiosProgramStructure.doc"

Regards
Wolfgang


Marco Landert <e-mail@landert.org> wrote in message
news:3AAF4EB3.12F3288B@landert.org...
> dear all,
>
> has anyone experience in writing c-code for a nios system from altera?
> i'm writing c-code for a 16-bit nios system and there are many
> problems...
> for example the interrupt-handling and of course the simulation of the
> source code. i'm also  searching a simulator for this system. at the
> moment, i'm using modelSim (for timing-diagram), but a gui-tool would be
> better and less time-intensive.
> has anyone example-programs for a 16-bit nios system? especially with a
> pio-interface and isr's.
>
> or general, has anyone experience in developing a 16-bit nios system?
>
> thank's for answers
>
> marco
>



Article: 29882
Subject: Re: NIOS 16-Bit
From: Nial Stewart <nials@sqf.hp.com>
Date: Thu, 15 Mar 2001 10:06:49 +0000
Links: << >>  << T >>  << A >>
Marco Landert wrote:
> 
> nial,
> 
> are there any documentations...? no, serious: the documentations (whitch you
> have to search) are not really detailed. the main problem is, that the
> 16-bit version includes bugs and (altera has became conscious of them) you
> don't know exactly what should works correct.
> 
> if you know an adress, where i could find more information/ documentation/
> example programs about nios, just tell me this.
> 
> marco


Marco, I haven't any more info than's available on the 
Altera web site.

Nial.

Article: 29883
Subject: Re: NIOS 16-Bit
From: Marco Landert <leica-geosystems@landert.org>
Date: Thu, 15 Mar 2001 13:34:14 +0100
Links: << >>  << T >>  << A >>
i'm using the bash shell to compile, link etc. and i use the nios-build
instruction. but afterwards, i simulate the function with ModelSim (Mentor
Graphics) because i have to control the interface-access.
well, i'm not really experienced in developing such systems and if you have
other ideas to test the software, just tell me more.
marco

"Frank Ch. Eigler" schrieb:

> Marco Landert <e-mail@landert.org> writes:
>
> : [...]
> : has anyone experience in writing c-code for a nios system from altera?
> : i'm writing c-code for a 16-bit nios system and there are many problems...
> : for example the interrupt-handling and of course the simulation of the
> : source code. i'm also  searching a simulator for this system. [...]
>
> Are you aware of the NIOS 16/32-bit instruction-set simulators that
> are part of the GNUPro toolchain that comes with the Excalibur kit?
>
> - FChE


Article: 29884
Subject: Re: NIOS 16-Bit
From: "Rune Baeverrud" <fpga@no.spam.iname.com>
Date: Thu, 15 Mar 2001 13:38:59 +0100
Links: << >>  << T >>  << A >>
> have you looked at the documents in
> C:/cygwin/usr/altera/excalibur/nis-sdk/technotes/

Could you tell us the IP address of your c-drive, please?

Rune :)




Article: 29885
Subject: Using Virtex DLLs in Leonardo
From: Tom Van Uffelen <vuffelen@imec.be>
Date: Thu, 15 Mar 2001 14:02:07 +0100
Links: << >>  << T >>  << A >>
Hello,

I'm working at IMEC in Belgium and I'm using Leonardo Spectrum 2001.1a
to synthesize an FPGA design for a VIRTEX 800.

When Leonardo reads the design, it does not recognize the signals coming

out of the DLL as being a clock. So I'm not able to specify the
frequency of
that clock. I can't use the global clock constraint because the
frequency of that clock is typically 4 times smaller then the highest
frequency in the design. If I would do that, then there is a lot of
negative slack on the logic that is using this slower clock.

How do I tell Leonardo that the output of a DLL is a clock?

Thanks in advance,

Tom Van Uffelen

Article: 29886
Subject: Re: IP Cores, Megacores
From: "Compilit" <compilehr@hotmail.com>
Date: Thu, 15 Mar 2001 05:05:38 -0800
Links: << >>  << T >>  << A >>
Not sure about Xilinx, but I believe Altera will let you try these cores out
for free.

What would prevent you from not paying while actually using them ? Just
curious


"Zimba" <zimba@zamba.com> wrote in message
news:98is1o$fik$1@s1.read.news.oleane.net...
> We bought a PCI core and it seems that we have full source code in both
VHDL
> and Verilog. I think the protection is more like "Why would I give away
> something that I paid $5000,- for?". Furthermore, buying a core (Xilinx,
> that is, I don't know about others) gets you a password that gives access
to
> support that you need. (Of course you can also give the password away, if
> you like.)
>
> It is the same as with other software that you buy with sources. You can
> give it away if you like and this is why software with sources is usually
> way more expensive than without.
>
> For Xilinx and other component manufacturers, I think that they get their
> IP-core development costs from IP-core sales and the real profit from
> selling devices.
>
> Clemens
>
>



Article: 29887
Subject: Re: Using Virtex DLLs in Leonardo
From: "Håkan Pettersson" <chakanp@hem1.passagen.se>
Date: Thu, 15 Mar 2001 14:57:55 +0100
Links: << >>  << T >>  << A >>
set_clock -net -name <output_from_dll> -clock_cycle <string> -clock_offset
<string> -pulse_width <string>

/Håkan


"Tom Van Uffelen" <vuffelen@imec.be> wrote in message
news:3AB0BD4F.65DA9250@imec.be...
> Hello,
>
> I'm working at IMEC in Belgium and I'm using Leonardo Spectrum 2001.1a
> to synthesize an FPGA design for a VIRTEX 800.
>
> When Leonardo reads the design, it does not recognize the signals coming
>
> out of the DLL as being a clock. So I'm not able to specify the
> frequency of
> that clock. I can't use the global clock constraint because the
> frequency of that clock is typically 4 times smaller then the highest
> frequency in the design. If I would do that, then there is a lot of
> negative slack on the logic that is using this slower clock.
>
> How do I tell Leonardo that the output of a DLL is a clock?
>
> Thanks in advance,
>
> Tom Van Uffelen



Article: 29888
Subject: Re: IP Cores, Megacores
From: "Zimba" <zimba@zamba.com>
Date: Thu, 15 Mar 2001 17:43:56 +0100
Links: << >>  << T >>  << A >>
Well, probably in this case they don't give the sources but just a generic
binary to show off some functionality. I guess.

Clemens




Article: 29889
Subject: Re: Low volume users (was: Re: VirtexE LVPECL I/O Ports? experience?)
From: "Jaan Sirp" <jaan.sirp@mail.ee>
Date: Thu, 15 Mar 2001 08:57:38 -0800
Links: << >>  << T >>  << A >>
Hi,

I have found several messages from this group, that BGAs are not for low volume production. The guy, who has soldered my proto boards says, that soldering BGAs isn't more difficult, than soldering QFPs. He has made a thermal-isolated box and uses hot-air gun and thermal sensor to keep track of characteristics. He uses no paste, just flux for BGAs. The soldering to gilded pads is very successful, if PCB has tin/lead pads, sometimes second round with little weight on BGA is needed (he think, his flux isn't the best).

Jaan

Article: 29890
Subject: Re: Programming CPLD and FPGA on XESS board for Ethernet.
From: "Jaan Sirp" <jaan.sirp@mail.ee>
Date: Thu, 15 Mar 2001 09:26:17 -0800
Links: << >>  << T >>  << A >>
Hi,

Join the CPLD and FPGA to JTAG chain, use .mcs files for configuration.

I have currently the similar FPGA project, Ethernet connection is needed among other things. The price difference between PHY chips and PHY/MAC chips is much smaller, than price of FPGA area, needed for implementing MAC (not speaking about time, needed for MAC implementing), so I decided using PHY/MAC chip (DP83815).
My problem: I haven't found from marked TCP/IP core, suitable for FPGA. I know, some people have begun designing TCP/IP core, but without successful completing. Probably I have to use processor for TCP/IP stack (I have C source for it).

Jaan

>I'm trying to setup an ethernet controller on a Xilinx Virtex chip and
need to control the level1 PHY chip with information that is both on the
CPLD and the Virtex FPGA. Does anyone know how to program both at the same
time? I'm able to program one but in loading the other .svf or .bit the
originally programmed chip looses its functionality.

Article: 29891
Subject: Re: Parallel Port EPP (again)
From: hphan@dacafe.com (Hoa Phan)
Date: Thu, 15 Mar 2001 17:59:42 GMT
Links: << >>  << T >>  << A >>
Please, send me this in ABEL and schematic for EPP mode, if you don't
mind, and I appreciated this. I also use this stuff. Thank you
Hoa Phan
hphan@dacafe.com

On Wed, 14 Mar 2001 15:29:39 +0000, John Chambers
<JohnC@ihr.mrc.ac.uk> wrote:

>The EPP port has some extra registers
>
> BASEADDR 0x378		Not used in EPP mode
> STATUS 0x379		Not used in EPP mode
> CONTROL 0x37A		Need to set bit 5 to enter EPP mode
> LOADDR 0x37B		Reading and writing to this will cause an EPP address
>read or write
> DATAPORT 0x37C		EPP data port
>			This is at least one one byte wide and every one I've seen is two
>bytes
>			So you can outpw to DATAPORT which will write two data bytes to the
>EPP
>			Similarly inpw will read 2 data byte from the EPP port
>
>You can use something like WIN95IO.DLL to talk to IO ports in
>windows95/98/mil from C or VB.  If you want to do it properly or you are
>using NT (No Tinkering) then you'll have to buy some software to access
>the IO the "Microsoft way".  TVICHW32 is good and cheap and has an
>evaluation version but is terribly slow.  Have a look an
>http://www.lvr.com for all the different ways of skinning this
>particular cat.
>For example this send an 8 bit address (0x54) and a 32 bit data value
>(0x12345678) to the EPP port 
>
>union {
>	short int lsw[2];
>	long memval;
>} conv;
>
>	conv.memval=0x12345678
>	vbOut (LOADDR,0x54);
>	vbOutw(DATAPORT,conv.lsw[0]);
>	vbOutw(DATAPORT,conv.lsw[1]);
>
>I also spent a lot of time getting the latching of the strobe signal
>sorted in my CPLD design (Lattice 1032 using ABEL and schmatic
>capture).  I'll send you my state machine if you want but it is designed
>to interface with a DSP (SHARC 21061) and so is rather more complicated
>than you would want.
>
>John
>
>"F.M. Fontaine" wrote:
>> 
>> A few days ago there was a thread in this newsgroup regarding the
>> implementation of a parallel port interface EPP in a FPGA. Having read the
>> suggestions in this newsgroup this doesn't seem to be very complicated.
>> 
>> However one thing that worries me a little is the driver software (for
>> Win95). How can the EPP port be addressed? Is there a standard driver
>> available to address the I/O registers? Should I adjust my BIOS setings to
>> have a true EPP port on the LPT, or should it also work in the standard
>> ECP-mode?
>> 
>> Any suggestions regarding the driver issue are highly appreciated. Thanks.
>> 
>> Filip Fontaine


Article: 29892
Subject: Archive of Electronic Engineering jobs incl: ASIC,DSP,VHDL,FPGA,RF etc..
From: tekjobs@a1acomputerpros.net (A1A Computer Professionals)
Date: Thu, 15 Mar 2001 18:00:08 GMT
Links: << >>  << T >>  << A >>
Find the latest electrical/electronic engineering jobs

http://groups.yahoo.com/group/a1a-EEjobs


Use our archives to find your next job.. Easy keyword search engine.

ASIC,RF,DSP,FPGA VHDL etc..

thanks for letting us post here..


Article: 29893
Subject: International VHDL cooperation wanted
From: "Danny Niewzwaag" <d.niewzwaag@freeler.nl>
Date: Thu, 15 Mar 2001 19:30:20 GMT
Links: << >>  << T >>  << A >>
Dear all,

Currently I am employed with a leading VHDL /design house in the Netherlands
called Lumino. In order to keep our leading position we would like to get in
touch with international company's and VHDL specialists to share knowledge,
capacity and projects.
Also we would like to get informed about any previous experiences with
outsourcing or subcontracting via the internet.

Any information will be helpfull,

Thanks in advance,

Danny Niewzwaag

danny@niewzwaag.com




Article: 29894
Subject: Looking for VHDL code or ABEL+schematic capture for interfacing parallel port in mode EPP
From: hphan@dacafe.com (Hoa Phan)
Date: Fri, 16 Mar 2001 02:10:33 GMT
Links: << >>  << T >>  << A >>
Hi,
I am looking for VHDL code or ABEL code or veriliog code for parallel
port interface in mode EPP. Any pointers would be appreciated. Thank
you in advance

Article: 29895
Subject: Re: IP Cores, Megacores
From: "Compilit" <compilehr@hotmail.com>
Date: Thu, 15 Mar 2001 20:02:28 -0800
Links: << >>  << T >>  << A >>
Zimba and Denis,

The reasons I am asking all this is that I wonder if it's feasible to form a
company coding and selling IP cores. Is there a way to protect them when you
sell them to your customer.


"Zimba" <zimba@zamba.com> wrote in message
news:98qrh1$ega$1@s1.read.news.oleane.net...
> Well, probably in this case they don't give the sources but just a generic
> binary to show off some functionality. I guess.
>
> Clemens
>
>
>



Article: 29896
Subject: Re: IP Cores, Megacores
From: "Dennis Scott" <themenace@nospam.mindless.com>
Date: Fri, 16 Mar 2001 04:19:40 GMT
Links: << >>  << T >>  << A >>
I know that there are many companies doing this in partnersip with Altera
and probably Xilinx and others.  I am certain there is some kind of
protection but I think there has to be support from the tools.  I remember
in an Altera seminar someone speaking of an "encrypted netlist" and some
newer type of protected IP that is in a higher level form than a netlist,
allowing the tools to optimize and route while at the same time protecting
the vendor's IP.

Dennis

"Compilit" <compilehr@hotmail.com> wrote in message
news:98s3l4$dt5$1@taliesin.netcom.net.uk...
> Zimba and Denis,
>
> The reasons I am asking all this is that I wonder if it's feasible to form
a
> company coding and selling IP cores. Is there a way to protect them when
you
> sell them to your customer.
>
>
> "Zimba" <zimba@zamba.com> wrote in message
> news:98qrh1$ega$1@s1.read.news.oleane.net...
> > Well, probably in this case they don't give the sources but just a
generic
> > binary to show off some functionality. I guess.
> >
> > Clemens
> >
> >
> >
>
>



Article: 29897
Subject: Re: IP Cores, Megacores
From: "Zimba" <zimba@zamba.com>
Date: Fri, 16 Mar 2001 09:05:46 +0100
Links: << >>  << T >>  << A >>
As I said before, the protection is as with other software since a core is
just software. You can't say Microsoft isn't making money selling software
even while it is obvious that everybody is giving it away to all of there
friends (without sources).

If you sell a core to a company then there is no reason that the company
will give it away. Why would they give it away? And to who? A competitor?
Or, take me for instance, I don't even know somebody who might be interested
in a core I bought. Even if I would, I couldn't give it away.

And even if people would give it away, as long as your market is large
enough and your product good enough you will still find customers and make
money. People that give your core away are like competitors. You just cannot
hope for selling your core to everybody that needs it. But then again, you
don't need everybody, a (small) percentage is enough. If your product is
good and your price is right, the customer will buy and you will make money.

Did you ever try to use/modify somebody else's code? And without
documentation? This is one of the reasons why people pay for software: it
makes them save (a lot of) time. We paid happily $5000 for a core instead of
trying to develop it ourselves or looking for a free one. The core we got
was tested and working, with specialist support and we had it in just one
day! Now how can you beat that?

Your biggest problem is probably finding the customers for your product and
not how to protect it. So stop worrying about it.

Clemens



Article: 29898
Subject: RAM-based Shift Register
From: Heinrich Fonfara <heinrich.fonfara@ibmt.fhg.de>
Date: Fri, 16 Mar 2001 09:58:32 +0100
Links: << >>  << T >>  << A >>
Hello,

the RAM-based shift register created by the CoreGen for Virtex or
SpartanII can be configured as variable length SR. This is a very
usefull feature for my application, but in the product specification
this module is referred to a "lossy" ("because when the Address is
changed the output cannot be quaranteed to be correct for C clock cycles
where C is the new value for the address").
How to use the variable length feature of this module?  Can someone tell
me where
can I get some more information about the operation in the variable
length mode, perhaps some timing diagrams?

Thanks in advance

Heinrich Fonfara



Article: 29899
Subject: Passing text strings to procedures in VHDL
From: "Dave Glenton" <dave.glenton@pace.co.uk>
Date: Fri, 16 Mar 2001 10:27:00 -0000
Links: << >>  << T >>  << A >>
Anybody know how you can pass a text string to a VHDL procedure ?
Idealy of variable length ?

Cheers

Dave Glenton





Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search