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Messages from 29800

Article: 29800
Subject: Re: Questions about Xilinx Web Pack ISE
From: "Simon Bacon" <simonb@tile.demon.co.cut_this.uk.>
Date: Sun, 11 Mar 2001 00:25:04 -0000
Links: << >>  << T >>  << A >>

"llandre" <andmars@tin.it> wrote in message
news:vzpq6.24215$yl2.572464@news1.tin.it...
> I have just received the Xilinx Web Pack ISE v. 3.2.
> I tried to synthesize the code released by Xilinx itself
> associated with an Application Note describing how to
> implement an asynchronous FIFO using Spartan II devices.
> I have some questions:
> 1) how to locate the pins? I think I have to use the "attribute"
> reserved word, but which is the precise syntax?

Several solutions, but via a UCF file is the general approach.
I don't have the Web Pack, but look for a .ucf file in the
examples.

Using an attribute is another approach.  The syntax depends on
the design entry method - schematic/Verilog/VHDL/...

> 2) The code uses some device-dependent components (i.e. BUFGB).
> The synthesizer messages say that it generates black-box for these
> components. In other words, it seems it can not understant what component
> to instantiate. How to solve it (missing libraries???)?

The synthesiser references a library which defines all these as
black boxes.  Again, does the Web Pack come with some examples?






Article: 29801
Subject: Re: Metastability
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Sun, 11 Mar 2001 01:20:14 +0000
Links: << >>  << T >>  << A >>


Rick Collins wrote:

> As Ray pointed out, metastability is resolved not in the cycle time, but
> in the slack time. So the more places you have to route to, the less
> slack time you are left with. So what you say is basicially true, you do
> have to watch your cycle time vs the routing time. If the routing eats
> up too much of the cycle time you will degrade your metastability
> resolution.
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX

... and the only way it seems that you can control this is to derate the timing
constraints that apply to the fanout(s) from the async FF. The $2**64 question is by
how much ? Without the manufacturers publishing basic metastab parameters this just
has to be guesswork.

Question for Peter A.: Is it possible, for a known FF silicon structure, to compute
these values from basic physics [or maybe not so basic quantum mechanics] ? If not
then are the difficulties theoretical or practical/computational ?



Article: 29802
Subject: Re: Using LVDS I/O buffers on Virtex-II
From: Catalin Baetoniu <a@z.com>
Date: Sun, 11 Mar 2001 03:26:07 GMT
Links: << >>  << T >>  << A >>
Aldo,

Try to turn off buffer insertion in Synplicity and instantiate all IO 
buffers (both normal and LVDS) manually. I am using this approach in my 
current design and it works with VirtexE.

Catalin Baetoniu
Starnet Engineering Inc.

Aldo Mastrosimone wrote:

> Anyone using LVDS I/O on Virtex-II ? We're having trouble getting Edif2NGD
> to correctly expand the lower level primitives (IOBUF_LVDS). We're using
> Synplicity V6.13, Alliance 3.3i (w/ Service Pack 7). Not sure if we have all
> the files we're supposed to. When Edif2NGD fails, we get an error 432. It
> appears that it's looking for a .NGO file for the IOBUF_LVDS primitive. Any
> ideas ??


Article: 29803
Subject: sample code for JTAG configuration of Virtex, Spartan II?
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 11 Mar 2001 01:41:34 -0800
Links: << >>  << T >>  << A >>
Does anyone have any sample code (perhaps in C?) for JTAG configuration
of Virtex or Spartan II parts?

Thanks!
Eric

Article: 29804
Subject: Configuration devices
From: jschneider@cix.CEEOWE.EWEKAY
Date: 11 Mar 2001 11:47:10 +0000
Links: << >>  << T >>  << A >>
I was a little bit staggered on getting a price for Altera EPC2
configuration devices (25 in one off).

If they can't make/sell flash at a reasonable price why don't their
devices configure from normal serial flash ? It would be cheaper to
put a small microcontroller down and use that to do the
configuration. Is this just a clever way for them to get more money ?

There are obviously various application notes from the various vendors
describing ways to configure devices. If I genuinely want to replace
an ASIC with a low cost FPGA (low end Spartan II perhaps) but that
might be reprogrammed at little or no hardware cost and in the absense
of a micro on board, what methods are best ?

I know I can work it out in theory but getting quotes out of
distributors is a long painful process over here - believe me.

	Jon

Article: 29805
Subject: Re: Configuration devices
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Sun, 11 Mar 2001 21:25:21 +0100
Links: << >>  << T >>  << A >>
jschneider@cix.CEEOWE.EWEKAY schrieb:
> 
> describing ways to configure devices. If I genuinely want to replace
> an ASIC with a low cost FPGA (low end Spartan II perhaps) but that
> might be reprogrammed at little or no hardware cost and in the absense
> of a micro on board, what methods are best ?

Hmm, some (all?) of the Xilinx serial EEPROMS are programmable via JTAG.
Or use a small CPLD to implement a simple state machine to configure a
FPGA via a standard EEPROM/FLASH.

-- 
MFG
Falk

Article: 29806
Subject: Re: More detailed Spartan II CLB drawings?
From: Neil Franklin <neil@franklin.ch.remove>
Date: 11 Mar 2001 23:09:55 +0100
Links: << >>  << T >>  << A >>
Kent Orthner <korthner@hotmail.nospam.com> writes:

> Part of the JBits package includes an explanation of th Virtex/
> Spartan-II architacture.

No need of getting JBits just for the "Slice" graphic in the Virtex
Architecture Guide. It is nearly[1] identical to the graphic[2] in
the Virtex data sheet, available to anyone direct from the Xilinx
web site.

[1] apart from the JBits specific "numbering" of the features for
introducing the JBits constants used to configure the features.

[2] http://www.xilinx.com/partinfo/ds003.pdf, Page 7, Figure 5


>  but  it's much better than the databook.

Next to identical to the Virtex data sheet / databook. Most likely
copied from there and then annotated.


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/FH/BSc, Sysadmin, Roleplayer, LARPer, Mystic

Article: 29807
Subject: Re: Configuration devices
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 12 Mar 2001 02:18:52 +0000
Links: << >>  << T >>  << A >>


Falk Brunner wrote:

> jschneider@cix.CEEOWE.EWEKAY schrieb:
> >
> > describing ways to configure devices. If I genuinely want to replace
> > an ASIC with a low cost FPGA (low end Spartan II perhaps) but that
> > might be reprogrammed at little or no hardware cost and in the absense
> > of a micro on board, what methods are best ?
>
> Hmm, some (all?) of the Xilinx serial EEPROMS are programmable via JTAG.
> Or use a small CPLD to implement a simple state machine to configure a
> FPGA via a standard EEPROM/FLASH.
>
> --

The CPLD/Flash idea works very well except that the only socketable Flash
parts are 4MBit. Probably o.k. for Spartans but not big Virtex's. Also if
you use the PLCC32 for the flash package beware that PLCC sockets are
notoriously fragile.

The ideal would be to find some way of programming an SMT flash via a
Centronics cable. I've been told that the awkwardness of this is due to
having to be able to read the flash as well as write it in order to get the
manufacturer ID etc.
Therefore you need to implement ECP/EPP in a small - but getting bigger -
CPLD.

Still I expect Centronics conn + Flash + CPLD would be cheaper and much more
flexible than the serial EEPROMs supplied by Xilinx/Altera. Takes more board
area though.



Article: 29808
Subject: Re: Configuration devices
From: Ray Andraka <ray@andraka.com>
Date: Mon, 12 Mar 2001 03:21:46 GMT
Links: << >>  << T >>  << A >>
No need, you can use the standard Parallel port (can't remember the name at the
moment), returning a nibble at a time over the status lines.  The driver is a
little more work, but it is compatible with all PCs, even if EPP and ECP are not
supported.  The logic on the device end will fit in a Lattice 1032E.

Rick Filipkiewicz wrote:
> The ideal would be to find some way of programming an SMT flash via a
> Centronics cable. I've been told that the awkwardness of this is due to
> having to be able to read the flash as well as write it in order to get the
> manufacturer ID etc.
> Therefore you need to implement ECP/EPP in a small - but getting bigger -
> CPLD.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 29809
Subject: Re: Configuration devices
From: msimon@xta.com (M. Simon)
Date: Mon, 12 Mar 2001 04:17:57 GMT
Links: << >>  << T >>  << A >>

>The ideal would be to find some way of programming an SMT flash via a
>Centronics cable. 

I have done this recently.

I have boards to simulate 8255s (using HCT) driven by a parallel port.

I use these simulated 8255s to control the reading and writing of the
FLASH. (with buffers and level translators where appropriate.

The software I did for this is proprietary and in any case is tailored
to a specific chip so it will need to be rewritten.

The board designs I own so replication of the hardware would be
relatively simple.

Let me know if you are interested.





M. Simon  Space-Time Productions http://www.spacetimepro.com
              Free CNC Machine Control Software
              Free Source Code
              Control the World From a Parallel Port

Article: 29810
Subject: Re: SRAM fpga cell
From: Peter Alfke <palfke@earthlink.net>
Date: Mon, 12 Mar 2001 05:37:23 GMT
Links: << >>  << T >>  << A >>


Utku Ozcan wrote:

> <snip> will it be technologically possible to have
> reconfigurable FPGA-like control system in DRAMs, so that
> we can get rid of RDRAM, SDRAM, EDO, ZBT etc.? :)
>

Very unlikely. Cut-throat competition.
DRAMs are extremely price-sensitive commodity parts.
No room for luxuries like programmable interfaces.
You just buy the features and the speed you need, or can afford...

Peter Alfke



Article: 29811
Subject: Re: Again Spartan II power
From: "R Sefton" <rsefton@home.com>
Date: Mon, 12 Mar 2001 06:03:23 GMT
Links: << >>  << T >>  << A >>
We had intermittent power-related start-up problems with a Spartan
II device and it took us a couple of weeks to fix it. We abided by
all of the data sheet power requirements, but eventually delaying
2.5V startup in relation to the 3.3V supply eliminated the problem
(i.e., Vccint/Vcco sequencing DID matter). We had an XC2S150 and
XC2S200 on the same board (and same power supplies). The XC2S200 was
not affected, but the XC2S150 failed to configure 5-10% of the time.
The device would not respond to PROG/ (INIT/ would stay high).

Bob S.


"Austin Lesea" <austin.lesea@xilinx.com> wrote in message
news:3AA5AAD6.55B0F0A9@xilinx.com...
> Falk,
>
> We do not test every single part for any power on ramp exceeding
50 ms.
>
> We have done characterization which shows you may have problems
with ramps
> longer than 100 ms because you can not keep the voltage generally
increasing
> through the critical power on trip point (POR).
>
> Spartan II has no Vccint vs. Vcco sequence issues (either can be
before the
> other, and outputs remain tristate, and no current results on the
Vcco).
>
> Virtex E MUST have Vccint before Vcco to operate properly.  This
is not true
> of Virtex, or Spartan II.
>
> I would work closely with your Xilinx FAE to characterize your
application
> to be sure you will have a reliable design across all corners.
>
> We are in the midst of a respecification of Spartan II right now.
>
> I have heard: longer ramps, current vs ramp rate, sequence issues,
> non-linear ramps, and current vs device size all requested.
>
> Have I missed anything?????
>
> Thank you,
>
> Austin
>
> Falk Brunner wrote:
>
> > Please dont cry folks ;-)
> >
> > I ran through the preveous thread and have still some questions.
> > We have a hot-swapable card and to prevent big surge currents we
have to
> > use a very slow powerup ramp (250ms are planned).
> > Is this a problem for the Spartan II?? The powersupply can
delviver far
> > more than 500mA but not that fast as required in the datasheet
(50ms).
> > Another question is about the Vcoo and Vcint timing relation.
> > How critical is it (Vcoo must be above 1V when Vcint crosses
1.6V (POR)
> > ).
> >
> > --
> > MFG
> > Falk
>


Article: 29812
Subject: __Cut and Paste C codes, you can have your hardware!
From: kctang <kctang@ie.cuhk.edu.hk>
Date: Mon, 12 Mar 2001 15:11:54 +0800
Links: << >>  << T >>  << A >>
Dear all,

Cut and Paste C codes, you can have your hardware!
--------------------------------------------------


  http://www.jrs.com/legac.htm

  http://www.frontierd.com/art.htm

  http://www.cleveldesign.com/products/index.html



Thanks a LOT,   kctang



Article: 29813
Subject: Parallel Port EPP (again)
From: "F.M. Fontaine" <fontain@nlr.nl>
Date: Mon, 12 Mar 2001 10:04:57 +0100
Links: << >>  << T >>  << A >>
A few days ago there was a thread in this newsgroup regarding the
implementation of a parallel port interface EPP in a FPGA. Having read the
suggestions in this newsgroup this doesn't seem to be very complicated.

However one thing that worries me a little is the driver software (for
Win95). How can the EPP port be addressed? Is there a standard driver
available to address the I/O registers? Should I adjust my BIOS setings to
have a true EPP port on the LPT, or should it also work in the standard
ECP-mode?

Any suggestions regarding the driver issue are highly appreciated. Thanks.


Filip Fontaine





Article: 29814
Subject: IP Cores, Megacores
From: "Compilit" <compilehr@hotmail.com>
Date: Mon, 12 Mar 2001 01:31:58 -0800
Links: << >>  << T >>  << A >>
Hello everyone,

Please explain this about IP cores and Megacores sold by Altera and Xilinx.

How would they go about preventing people from stealing the code and giving
to someone else ?

Let's say if I want to buy a core for $15K, I want it in Verilog, will they
deliver in Verilog, and the test vectors, and that's it ? You own the core ?
I don't understand how one can protect these IP's .



Article: 29815
Subject: Re: cpul vs vhdl
From: "Compilit" <compilehr@hotmail.com>
Date: Mon, 12 Mar 2001 01:34:28 -0800
Links: << >>  << T >>  << A >>
Hey, what about Verilog ?

"Andy Peters noao [.] edu>" <"apeters <"@> wrote in message
news:97jga2$1j3p$1@noao.edu...
> Will wrote:
> >
> > > You can download free software from both Xilinx and Altera to design
> > > FPGAs in VHDL or Verilog. So why both learning CUPL? You don't need to
> > > be limimted by your software.
> >
> > CUPL is bad comparad to vhdl?
>
> CUPL was a buggy piece of crap last time I looked at it.
>
> --ap



Article: 29816
Subject: Re: clock divider by 1.5
From: goran <goran_metlic@yahoo.com>
Date: Mon, 12 Mar 2001 05:31:59 -0800
Links: << >>  << T >>  << A >>
first thank you all for taking time to help me and second :clock divider i found in the article didnt wok so good maybe it is becouse im using a xc4k device.i thought to make a clock multiplier (all multipliers use some sort of delay) but i dont have a dll in my libraries (im using xilinx foundation to make designs).if someone has some other idea or can help me with this please do so .(i need to extract 1.08mhz clock from 12.15mhz one)

Article: 29817
Subject: Leonardo 'renames' in- and outputs.
From: "Harjo Otten" <h.otten@rohill.geen.spam.nl>
Date: Mon, 12 Mar 2001 14:57:11 +0100
Links: << >>  << T >>  << A >>
Hi,

I'm having a little problem with my CPLD design in Leonardo Spectrum.
When I use FPGA express for the synthesis, everything is OK, but when I try
to use Leonardo, It seems as if Leonardo is renaming my adres-bus. This
means I cannot use my 'old' UCF anymore. Has anybody got an idea on how to
tell Leonardo not to rename my ports ?

Thanx,

H.



Article: 29818
Subject: Re: IP Cores, Megacores
From: "Dennis Scott" <themenace@nospam.mindless.com>
Date: Mon, 12 Mar 2001 14:49:41 GMT
Links: << >>  << T >>  << A >>
The way I understand it is that you don't get the code at all.  You get an
encrypted netlist that you use like a black box.

Dennis

"Compilit" <compilehr@hotmail.com> wrote in message
news:98i5ec$5ds$1@taliesin.netcom.net.uk...
> Hello everyone,
>
> Please explain this about IP cores and Megacores sold by Altera and
Xilinx.
>
> How would they go about preventing people from stealing the code and
giving
> to someone else ?
>
> Let's say if I want to buy a core for $15K, I want it in Verilog, will
they
> deliver in Verilog, and the test vectors, and that's it ? You own the core
?
> I don't understand how one can protect these IP's .
>
>



Article: 29819
Subject: Re: IP Cores, Megacores
From: "Zimba" <zimba@zamba.com>
Date: Mon, 12 Mar 2001 17:00:51 +0100
Links: << >>  << T >>  << A >>
We bought a PCI core and it seems that we have full source code in both VHDL
and Verilog. I think the protection is more like "Why would I give away
something that I paid $5000,- for?". Furthermore, buying a core (Xilinx,
that is, I don't know about others) gets you a password that gives access to
support that you need. (Of course you can also give the password away, if
you like.)

It is the same as with other software that you buy with sources. You can
give it away if you like and this is why software with sources is usually
way more expensive than without.

For Xilinx and other component manufacturers, I think that they get their
IP-core development costs from IP-core sales and the real profit from
selling devices.

Clemens



Article: 29820
Subject: Re: clock divider by 1.5
From: Ray Andraka <ray@andraka.com>
Date: Mon, 12 Mar 2001 16:49:36 GMT
Links: << >>  << T >>  << A >>
You can use direct digital synthesis to get a 1.08 MHz clock from an 12.15 MHz
one.  It will have jitter up to one cycle time of the 12.15 MHz clock on it.  T
oreduce the jitter use a faster master clock.  For details on the direct digital
synthesis, look back in this newsgroups archives in deja news for DDFS or direct
digital synthesis. It has been discussed here many times.

goran wrote:
> 
> first thank you all for taking time to help me and second :clock divider i found in the article didnt wok so good maybe it is becouse im using a xc4k device.i thought to make a clock multiplier (all multipliers use some sort of delay) but i dont have a dll in my libraries (im using xilinx foundation to make designs).if someone has some other idea or can help me with this please do so .(i need to extract 1.08mhz clock from 12.15mhz one)

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 29821
Subject: Re: Again Spartan II power
From: "Andrej Jancura" <andrej.jancura@e-technik.tu-ilmenau.de>
Date: Mon, 12 Mar 2001 18:30:35 +0100
Links: << >>  << T >>  << A >>
Hi,

I design now an board with XC2S150, and still have some unsureness about the
choice of this type.
Its my first design with FPGA and reading all topics about power-up trouble
makes some dark nights now...

I would like to know, how to design the power supply. I plane to use REG1117
on board.

Andrej


"R Sefton" <rsefton@home.com> schrieb im Newsbeitrag
news:LEZq6.24124$o7.803765@news1.rdc1.sdca.home.com...
> We had intermittent power-related start-up problems with a Spartan
> II device and it took us a couple of weeks to fix it. We abided by
> all of the data sheet power requirements, but eventually delaying
> 2.5V startup in relation to the 3.3V supply eliminated the problem
> (i.e., Vccint/Vcco sequencing DID matter). We had an XC2S150 and
> XC2S200 on the same board (and same power supplies). The XC2S200 was
> not affected, but the XC2S150 failed to configure 5-10% of the time.
> The device would not respond to PROG/ (INIT/ would stay high).
>
> Bob S.
>
>
> "Austin Lesea" <austin.lesea@xilinx.com> wrote in message
> news:3AA5AAD6.55B0F0A9@xilinx.com...
> > Falk,
> >
> > We do not test every single part for any power on ramp exceeding
> 50 ms.
> >
> > We have done characterization which shows you may have problems
> with ramps
> > longer than 100 ms because you can not keep the voltage generally
> increasing
> > through the critical power on trip point (POR).
> >
> > Spartan II has no Vccint vs. Vcco sequence issues (either can be
> before the
> > other, and outputs remain tristate, and no current results on the
> Vcco).
> >
> > Virtex E MUST have Vccint before Vcco to operate properly.  This
> is not true
> > of Virtex, or Spartan II.
> >
> > I would work closely with your Xilinx FAE to characterize your
> application
> > to be sure you will have a reliable design across all corners.
> >
> > We are in the midst of a respecification of Spartan II right now.
> >
> > I have heard: longer ramps, current vs ramp rate, sequence issues,
> > non-linear ramps, and current vs device size all requested.
> >
> > Have I missed anything?????
> >
> > Thank you,
> >
> > Austin
> >
> > Falk Brunner wrote:
> >
> > > Please dont cry folks ;-)
> > >
> > > I ran through the preveous thread and have still some questions.
> > > We have a hot-swapable card and to prevent big surge currents we
> have to
> > > use a very slow powerup ramp (250ms are planned).
> > > Is this a problem for the Spartan II?? The powersupply can
> delviver far
> > > more than 500mA but not that fast as required in the datasheet
> (50ms).
> > > Another question is about the Vcoo and Vcint timing relation.
> > > How critical is it (Vcoo must be above 1V when Vcint crosses
> 1.6V (POR)
> > > ).
> > >
> > > --
> > > MFG
> > > Falk
> >
>



Article: 29822
Subject: Re: clock divider by 1.5
From: Bertram Geiger <bgeiger@aon.at>
Date: Mon, 12 Mar 2001 19:40:40 +0100
Links: << >>  << T >>  << A >>
goran schrieb:
> 
> first thank you all for taking time to help me and second :clock divider i found in the article didnt wok so good maybe it is becouse im using a xc4k device.i thought to make a clock multiplier (all multipliers use some sort of delay) but i dont have a dll in my libraries (im using xilinx foundation to make designs).if someone has some other idea or can help me with this please do so .(i need to extract 1.08mhz clock from 12.15mhz one)

Did i miss something ? I understood that you first asked for a divider
by 1.5
The above is a divider by 11.25  or by 45/4 
That results in a modulo 45 counter, incremented by 4 with every cycle

Bertram


-- 
Bertram Geiger,  bgeiger@aon.at
HTL Bulme Graz-Goesting - AUSTRIA

Article: 29823
Subject: Re: SRAM fpga cell
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Mon, 12 Mar 2001 22:02:26 +0200
Links: << >>  << T >>  << A >>
Austin Lesea wrote:

> Utku,
>
> The DRAM process is different from the CMOS process, and making an IC with logic and
> DRAM is a significant challenge (foundries and companies have failed trying to do
> so).  One can not take advantage of the latest technology, and one finds oneself a few
> years behind (i.e. death of company to be late!!!)
>
> Moore's Law goes: 0.18 -> 0.15u -> 0.12u -> 0.10u -> 0.07u -> ???
>
> If you are not making silicon at the tiny end by now....it may be too late for you as
> a chip vendor.
>
> When it is a standard offered process (DRAM + logic), or even a prototype process that
> is available from a foundry in the world, we will be ready,
>
> Austin

But the thing is different for SRAM process + FPGA. Your technology is evidence of that.
(unless you use TFT or 2T with tera-ohm poly loads in SRAMs in Xilinx FPGAs?)
I mean, ZBT is a SRAM technology, when don't think about financial issues,
it must be technically possible the other way round. I agree:
No time for technically reasonable but financially non-sense solutions.

Utku



Article: 29824
Subject: Re: order Xilinx FPGA`s in Benelux
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Mon, 12 Mar 2001 12:10:16 -0800
Links: << >>  << T >>  << A >>
You can buy Xilinx devices in Belgium from:

Insight Memec P.O Box 167   9300  Aalst tel: 05-378-3521
or
IC-4S in Leuven, tel: 01-640-0025
or contact
SEI Rodelco in Wemmel, tel  02-456-0747

Peter Alfke ( back from giving seminars in Europe)
=====================
Steven Sanders wrote:

> Hello,
>
> Does anyone know where I can order small quantities (2-5) of Xilinx
> fpga`s in the Benelux?
>
> Thanx in advance!
>
> Steven




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