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Hi All:
I am trying to add my custmozied IP with DCM module in it using FSL
channel. I am facing problem adding DCM module generated from IP &
Architecture Wizard.
I tried this: I used the DCM vhd file created by IP & Arch wizard and
added the same in .pao file. It created timing constraint problem
particularly in DCM module. I face this problem because I used the
wizard created DCM vhd file? How can I overcome this problem? Is there
any other way that I can use DCM module in my customized IP?
Please help me out.
The DCM vhd file that I used and the timing constraint details given
below (Please note that I changed the component under the label
"CLKIN_BUFG_INST" to "BUFG". As per original vhd file, the component
instantiated was "IBUFG". But it gave me the error ERROr:NgdBuild: 445
logical net 'xxx' has multiple drivers'. When I changed it to BUFG, I
did not face the ngdbuild error: 455):
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity DCM_Module is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKDV_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end DCM_Module;
architecture BEHAVIORAL of DCM_Module is
signal CLKDV_BUF : std_logic;
signal CLKFB_IN : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND : std_logic;
component BUFG
port ( I : in std_logic;
O : out std_logic);
end component;
component DCM
generic( CLK_FEEDBACK : string := "1X";
CLKDV_DIVIDE : real := 2.000000;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := FALSE;
CLKIN_PERIOD : real := 0.000000;
CLKOUT_PHASE_SHIFT : string := "NONE";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DUTY_CYCLE_CORRECTION : boolean := TRUE;
FACTORY_JF : bit_vector := x"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := FALSE;
DSS_MODE : string := "NONE";
MAXPERCLKIN : time := 1000000 ps;
MAXPERPSCLK : time := 100000000 ps;
SIM_CLKIN_CYCLE_JITTER : time := 300 ps;
SIM_CLKIN_PERIOD_JITTER : time := 1000 ps);
port ( CLKIN : in std_logic;
CLKFB : in std_logic;
RST : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSCLK : in std_logic;
DSSEN : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLKDV : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
STATUS : out std_logic_vector (7 downto 0);
LOCKED : out std_logic;
PSDONE : out std_logic);
end component;
begin
GND <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKDV_BUFG_INST : BUFG
port map (I=>CLKDV_BUF,
O=>CLKDV_OUT);
CLKIN_BUFG_INST : BUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_INST : DCM
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.000000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.000000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => TRUE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND,
PSCLK=>GND,
PSEN=>GND,
PSINCDEC=>GND,
RST=>RST_IN,
CLKDV=>CLKDV_BUF,
CLKFX=>open,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
--------------------------------------------
Timing constraint not met problem:::
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
--------------------------------------------------------------------------------
Constraint | Requested | Actual |
Logic
| | |
Levels
--------------------------------------------------------------------------------
NET "bufgp_2/IBUFG" PERIOD = 10 nS HIG | 10.000ns | 9.883ns |
9
H 50.000000 % | | |
--------------------------------------------------------------------------------
PERIOD analysis for net "wpt_0/wpt_0/inst | 10.000ns | 8.254ns |
1
_WPT/Inst_DCM_Module/CLK0_BUF" derived fr | | |
om NET "bufgp_2/IBUFG" PERIOD = 10 nS | | |
HIGH 50.000000 % | | |
--------------------------------------------------------------------------------
* PERIOD analysis for net "wpt_0/wpt_0/inst | 20.000ns | 24.408ns |
8
_WPT/Inst_DCM_Module/CLKDV_BUF" derived f | | |
rom NET "bufgp_2/IBUFG" PERIOD = 10 nS | | |
HIGH 50.000000 % | | |
--------------------------------------------------------------------------------
1 constraint not met.
Generating Pad Report.
Thanks,
Aroul
Article: 83676<dave_baker_100@yahoo.co.uk> wrote in message news:1115239039.839241.303280@z14g2000cwz.googlegroups.com... > > Hi, > > I have a couple of questions regarding VHDL & synthesis for FPGA: > > 1) Are there any rule-of-thumb measurements for the max. no. of lines > of code in a clocked process statement (I assume each extra code > statement adds accumulated delays between successive clock edges) ? > > 2) Are there any good books that discuss issues relating to VHDL-FPGA > synthesis i.e. exactly what code translates to & the various > implications ? > > > Many thanks > Dave > 1) Others have addressed this. 2) This is target specific as VHDL can be used on many different devices by several vendors. However, the book HDL Chip Design by Steven Smith shows schematics for all VHDL and Verilog examples. This will help you understand some concepts such as when latches are inferred and how case statements are dealt with but it won't help you optimize your design for a specific chip.Article: 83677
williams wrote: > Hello, > I am using virtex 2 pro for a design of mine. When i am implementing > the synethesized edf using ISE it is giving hold time violation on > input clock for any frequency given during synthesis. I have given the > clock to usaual IBUFG followed by BUFG but its giving delay..i guess > so... How can i eleminate this problem? > > I have been integrating IP cores but the problem is some of the IP > core works fine but when i do minor change on some other module and > synthesize....the working IP stop working.... There is no resource > problem as i am using only 20% of it and also my clock speeed is 20 > MHZ. Can some one point where may be the problem ? Hold time violations that I've seen have generally been due to non-global clock routing resources being used - perhaps it would be worth looking at the design in fpga_editor and checking that the design has been implemented as you expect? Otherwise, static timing analysis might tell you something about the path - could you post a small section of a signal for which it's failing? The other indication that something's not quite right is the minor changes causing problems - again, I've seen this in designs that aren't purely synchronous, or in the case where local routing has been used. It indicates that when you resynthesise/map/par, the placement of the logic changes, and that the resulting placement is breaking the design. This would indicate insufficient constraints, constraint violations, or asynch. logic. JeremyArticle: 83678
On Wed, 04 May 2005 14:32:26 -0700, EveEllsworth wrote: > I am a senior technical recruiter with a very reputable firm, Common > Agenda. I have postitions to post in the SF Bay Area and very real. > My client company is actively interviewing. > > Please advise if it is acceptable to post here. > > Eve Ellsworth > > Senior Recruiter > Common Agenda, LLP > Tel: (732) 223-7114 Ext. 108 > > Fax: (732) 223-7116 > Email: eve@commonagenda.com > > Web: www.commonagenda.com > ...Partnering with progressive companies in the quest for exceptional > talent... I have only been reading this group for a very short time, so I can't speak for the group. But it doesn't seem very cohesive, so I doubt you will encounter organized resistance. Still, AFAIK, job postings are off-topic in technical groups, and generally frowned upon. If the job is not clearly FPGA related, you DEFINITELY should not post it here. If you want to play it safe, post the add somewhere else, e.g., craigslist (which you should use for sure, since it is free), and just put a very brief link here in the newsgroup to the craigslist ad. If you are going to take out a paid ad, I recommend the San Jose Mercury News Sunday classifieds. You can also use the SF Chronicle Sunday classifieds, if the job is actually in San Francisco or one of the immediately adjacent cities such as South San Francisco, Brisbane, Daly City, or Colma. Otherwise just use the Mercury News. I'm sure you'll get lots of responses. ;-) --MacArticle: 83679
Thank you for your reply. More details list here: ADI chip work at a clock of 200MHz, FPGA work from 40MHz up to 65MHz. FPGA write and read inner registers of ADI chip through parallel ports, which is the main job of the interface. ADI chip use WR# signal as the write data latch, and RD# signal as read latch. Write timing graph: __________________ | Address | |_________________| | | |---8ns---| ______________ | | | Data | | | |____________| | | | | |3ns | | | | Write __________ _________ __| |________| |__ |--7ns---| I hope write maximum frequnecy is the same as FPGA clock. So, if the FPGA works at 65MHz, I must drive Write signal by a combinatorial logic of a synchronized enable signal and the FPGA main clock. so, Write and Read is the Gated Clock. The timing of Address and data, whcih are synchronized with FPGA clock, responds to Write signal is troublesome. It is varies by physical design. And sometimes there are addition pulse on write signal, which come from time delay difference of 2 inputs(one is clock, one is control signal) of the LUT4 vary greatly. Could I use any timing constrains limits the delay difference to an accepted level? Thanks for your advice.Article: 83680
Thank you for your reply. More details list here: ADI chip work at a clock of 200MHz, FPGA work from 40MHz up to 65MHz. FPGA write and read inner registers of ADI chip through parallel ports, which is the main job of the interface. ADI chip use WR# signal as the write data latch, and RD# signal as read latch. Write timing graph: ----------------- | Address | |----------------| | | |---8ns---| -------------- | | | Data | | | |------------| | | | | |3ns | | | | Write ---------- --------- __| |________| |__ |--7ns---| I hope write maximum frequnecy is the same as FPGA clock. So, if the FPGA works at 65MHz, I must drive Write signal by a combinatorial logic of a synchronized enable signal and the FPGA main clock. so, Write and Read is the Gated Clock. The timing of Address and data, whcih are synchronized with FPGA clock, responds to Write signal is troublesome. It is varies by physical design. And sometimes there are addition pulse on write signal, which come from time delay difference of 2 inputs(one is clock, one is control signal) of the LUT4 vary greatly. Could I use any timing constrains limits the delay difference to an accepted level? Thanks for your advice.Article: 83681
Thank you for your advice. I'll try to use DLL to double the FPGA Clock. But another question, can I use any timing constrains limits the delay difference of 2 inputs of a LUT to an accepted level? How?Article: 83682
Hi Laguna_b1, > I understand that Xilinx will be doing a Floating Point Unit that uses > the APU interface. I haven't been able to find out how big a foot > print it will have within a given FPGA. I also don't know what the > cost will be. You are correct - Xilinx will indeed be releasing a Floating-Point Unit for the PowerPC 405 cores in the Virtex4 FX family, using the pipeline-coupled APU bus interface. This was demonstrated at the Embedded Systems Conference in San Francisco in March: http://www.xilinx.com/events/tradeshows/esc_sf05/workshop.htm As for price, footprint, availability... you have all the information that's currently available, I'm afraid! I can't offer any further details at this time. If you're interested, drop me a line with details of your application. Cheers, -Ben-Article: 83683
In my application, the designed interface is some alike the RAM interface. FPGA generate the write signal, read signal, address signal, and data signal (when writing), and ADI chip only drive the data signal (when reading). Data Reading not as fast as writing, up to 30 MHz. For I couldn't draw a timing graph correctly. The timing requusts is : when writing: Write is low active. The minimum low time of write signal is 2.5ns; the min high time of write signal is 7ns. Address signal setup time refer to write active(falling edge) is ns. Data setup time refer to write inactive(rising edge) is 3 ns. when reading: Read is low active. Maximum Data delay after address is 15ns; Maximum Data delay after read active (falling edge ) is 15ns; Minimum Address hold time after read inactive(rising edge) is 5 ns. Maximum Data hold time after read inactive(rising edge) is 10 ns. If still not clear, pls refer to AD9854 data sheet. Thansk all!Article: 83684
Thanks for the replies - you've set me straight on how to view processes. I'm new to VHDL/FPGAs but its starting to sink in.... Cheers DaveArticle: 83685
Markus Meng schrieb: > Markus Meng schrieb: > >> Hi all, >> >> we face a strange problem with our synchronized reset signal coming >> from the ISA-Bus. It seems that some part of the logic is not >> functioning correctly after reset-release. However I'am not shure. >> >> I would like to implement a digital debounce logic for this reset >> signal, and for this reason I would like to have part of the >> logic on reset-ed ONCE after power-up and configuration. Is there >> a way to connect to this internal power-up reset signal, or shall I >> leave the reset connection of such a debounce block always negated >> by connecting it to permanent '0', for a active '1' reset? >> >> Best Regards >> Markus >> >> ----== Posted via Newsfeeds.Com - Unlimited-Uncensored-Secure Usenet >> News==---- >> http://www.newsfeeds.com The #1 Newsgroup Service in the World! >> 120,000+ Newsgroups >> ----= East and West-Coast Server Farms - Total Privacy via Encryption >> =---- > > > Coming One Step further, we now have the following situation. The very > similar Spartan-II design is working perfectly in a clean 3.3Volt ISA > bus environment. Several thousand test runs using the the synchronized > Reset logic never produces an error. The card is working as expected. > > The very same card in a 'old' fashioned 5V ISA-Bus System with some > overshoot on the signals crashes from time to time after RESET. Once > this crash occurs, there is NO-WAY to reset the FPGA again. It remains > "kind-of-dead". Only Power-Off and Power-On again can 'solve' this > deadlock situation... > > The configuration is loaded from an external prom only once after > power-up. The ISA-Bus reset does not reload the bitstream but resets > the internal FF to their initial state ... > > Has somebody also seen this kind of strange behavior, where the FPGA > can not be reseted anymore by subsequent resets. It remains in this > state until power-off. > > Is this a 5Volt compatibility issue of Spartan-II? > > Best Regards > Markus > > ----== Posted via Newsfeeds.Com - Unlimited-Uncensored-Secure Usenet > News==---- > http://www.newsfeeds.com The #1 Newsgroup Service in the World! 120,000+ > Newsgroups > ----= East and West-Coast Server Farms - Total Privacy via Encryption =---- Hi all, completing this what I started. It has NOT been a Spartan-II IO issue concerning the 5 Volt compatibility issue of Spartan-II. Spartan-II works perfect in our legacy ISA Bus environment. Just in case, this comes up at another place Have a nice Day MarkusArticle: 83686
Hello, I interface my Cyclone with a micron SDRam using the Altera SDR SDRAM Controller but it seems that there is something very wrong in what I do. When I send a write command to the controller, what I get on the output using SignalTap is the write command issued to the SDRAM, but only 2 clocks later come the data. So the first two word I read are wrong, and the last two I write are lost. I think the configuration of the controller and the sdram is right, it runs at 50 MHz with a CAS of 2 (since it seems from the doc that the controller cannot do 1) If you have any idea ... Thanks NickArticle: 83687
Hi, my pad input clock is 100 MHz (clk_ibufg). I have constrained this to period 10 ns. How should I constrain the lvds_tick, which runs at max. 360 MHz ? Is this done automatically when I constrain clk_ibufg? Should I constrain the 180 MHz clock too? regards, Benjamin dcm2_1 : dcm2 port map ( CLKIN_IN => clk_ibufg, RST_IN => RESET, CLKFX_OUT => clk_180m, CLKDV_OUT => pixel_clk, LOCKED_OUT => lvds_locked, CLK0_OUT => open); dcm3_1: dcm3 PORT MAP( CLKIN_IN => clk_180m , RST_IN => not lvds_locked, CLK0_OUT => open, CLK2X_OUT => lvds_tick, LOCKED_OUT => open );Article: 83688
In article <1115242339.015173.259360@z14g2000cwz.googlegroups.com >, EveEllsworth <eellsworth@commonagenda.com> writes >I am a senior technical recruiter with a very reputable firm, Common >Agenda. I have postitions to post in the SF Bay Area and very real. >My client company is actively interviewing. > >Please advise if it is acceptable to post here. Technical group, no ads please. If one is allowed, others will follow and the group will be flooded so please don't. -- fredArticle: 83689
I'm working with a Xilinx board (Spartan XC3S2000) and I can't program Flash Eprom. I'm using iMPACT software. I have generated a configuration file for Eprom and I load it on Eprom. But it doesn't work. When I disconnect my parallel cable IV and set jumpers, my board does not read eprom program. Can someone help me please? How have I to set jumpers?Article: 83690
Hi again,
when I add this constrain, my design doesn't work anymore.
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 10 ns HIGH 50 %;
very strange, I don't understand this.
I am a little bit worried about this:
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 14.088ns (frequency: 70.984MHz)
Total number of paths / destination ports: 3140 / 194
-------------------------------------------------------------------------
Delay: 4.696ns (Levels of Logic = 14)
Source: col_count_0 (FF)
Destination: col_count_10 (FF)
Source Clock: clk rising 3.0X
Destination Clock: clk rising 3.0X
Data Path: col_count_0 to col_count_10
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCPE:C->Q 5 0.419 0.738 col_count_0 (col_count_0)
LUT4:I0->O 5 0.351 0.738 Ker1511 (CHOICE236)
LUT3_D:I0->LO 1 0.351 0.000 Ker1541 (N737)
MUXCY:S->O 1 0.422 0.000 col_count_inst_cy_0
(col_count_inst_cy_0)
MUXCY:CI->O 1 0.044 0.000 col_count_inst_cy_1
(col_count_inst_cy_1)
MUXCY:CI->O 1 0.044 0.000 col_count_inst_cy_2
(col_count_inst_cy_2)
MUXCY:CI->O 1 0.044 0.000 col_count_inst_cy_3
(col_count_inst_cy_3)
MUXCY:CI->O 1 0.044 0.000 col_count_inst_cy_4
(col_count_inst_cy_4)
MUXCY:CI->O 1 0.044 0.000 col_count_inst_cy_5
(col_count_inst_cy_5)
MUXCY:CI->O 1 0.044 0.000 col_count_inst_cy_6
(col_count_inst_cy_6)
MUXCY:CI->O 1 0.044 0.000 col_count_inst_cy_7
(col_count_inst_cy_7)
MUXCY:CI->O 1 0.044 0.000 col_count_inst_cy_8
(col_count_inst_cy_8)
MUXCY:CI->O 1 0.044 0.000 col_count_inst_cy_9
(col_count_inst_cy_9)
MUXCY:CI->O 0 0.044 0.000 col_count_inst_cy_10
(col_count_inst_cy_10)
XORCY:CI->O 1 0.973 0.000 col_count_inst_sum_10
(col_count_inst_sum_10)
FDCPE:D 0.263 col_count_10
----------------------------------------
Total 4.696ns (3.219ns logic, 1.477ns route)
(68.5% logic, 31.5% route)
regards,
Benjamin
Article: 83691Hi Ben, thank you very much for your measurements. I would say that the TCK signals on my board look exactly identical. Although I think that these signals look a bit strange because of the drop from 3,3V to 2V. For me it seems that the level converter in the cable is poorly designed. I have send the waveforms I have measured to altera. As soon as I get an answer from them I will also post it here in the newsgroup. The solution for me at the moment ist using Byteblaster MV instead of USB Blaster :-( It can't check the cable with the Nios - Board because I have only got the schematics and not the board. Best regards Markus > > Does this look familiar or is it way off? > > Also, if you have an Altera NIOS board lying around, could you try to > compare the waveforms between your USB Blaster and the diagram attached? > > If they are way off, you may indeed have a problem with the USB Blaster. > > Best regards, > > > Ben > > > ------------------------------------------------------------------------ > > > ------------------------------------------------------------------------ >Article: 83692
Hi, I figured out, that I have to use Place & Route Timings, because the DCM constraints are not even included in the synthesize timings. How can I manipulate the automatic DCM constraints? (besides overwriting single nets or groups with FROM-TO) Or is there never a reason to manipulate them? regards, BenjaminArticle: 83693
Hi Group, I figured out, that the automatic DCM constraints are only generated, if I specify the clk input of the first DCM with a manual constraint. Still I am wondering a little bit, if I have any impact on the automatic DCM cosntraints? regards, BenjaminArticle: 83694
Austin, I am probably not planning on using any of the DSP48 blocks, but I noticed the same for them (no change over temperature). Apologies for the skepticism, but it seems strange to me that I could load up my device with DCMs, DSP48s, PPC405s and measure the power at room temp and at high temp and have the difference between those two values be the same difference I would get if I were using NONE of those resources in the first place. Anyway, is there a spreadsheet for power calculations that I can get that would allow me to both do this analysis offline? Thanks, JD JDDCArticle: 83695
I am designing a board with 9 Xilinx V4FX60 FPGA's configured via System Ace CF controller. Does anyone have any experience regarding the max number of FPGA's in a JTAG chain that can be succesfully configured? Was any signal buffering required to acieve this? Thanks JasonArticle: 83696
In "Embedded System Tools Guide" on EDK6.2 say: ".... MicroBlaze requires 2 clock cycles to access on-chip Block RAM connected to the LMB for write and 2 clock cycles for read. On chip memory connected to the OPB bus requires 3 cycles for write and 4 cycles for read...." I don't understand, request latecies to BRAM = 1 tick. Request latecies to OPB (from timing waveforms) = 1 tick, if "Ack" signal generate with read strobe. PS sorry for bad englishArticle: 83697
Hi, I know a little bit of the answer already by now. It is because, the DCM auto constraints were not there, before I added the clk constraint. Is it possible to get the DCM auto constraints into the synthesize constraints? At the moment they are only in the Post and Place constraints, so synthesize doesn't optimize according to the DCM constraints. Next question: My lvds clock runs at 360 MHz now. However the Hsync and Vsync logic only needs to be updated every 7 cycles. At the beginning (see upper post) I had errors, complaining that the logic wasn't fast enough. I knew that, therefore I start the hsync and vsync calculations in cycle 3, but I need them only in cycle 1 (it goes 0-1-2-3-4-5-6-0, the signal is called lvds_div). I have attached the process. My solution is this: I have put all the col and row lines into a group, and set the from-to constraint to 5ns (equals about 2 lvds cycles). INST "row_count_0" TNM = "sync_logic_grp"; ... INST "col_count_0" TNM = "sync_logic_grp"; ... TIMESPEC "TS_sync_logic_grp" = FROM "sync_logic_grp" TO "sync_logic_grp" 5 ns; It would be nice to know, how a fpga veteran would do this, my methodology is probably not the best yet. Can I do something with a period constraint on the row and col signals? My route process has become very slow after these constraints, it goes now up to phase 25. Is there a way to get it faster again? Thanks for Your help! regards, Benjamin process (lvds_tick,screen_reset) begin if screen_reset='1' then col_count <= 0; row_count<= 0; DTMG <= '0'; -- pixel data enable VSYNC <= '0'; HSYNC <= '0'; elsif rising_edge(lvds_tick) then if lvds_div = 3 then case col_count is when num_col - 1 => DTMG <= '0'; if row_count = num_row -1 then VSYNC<='1'; elsif row_count = num_row+1 then VSYNC <='0'; end if; HSYNC <= '1'; when num_col + 28 => HSYNC <= '0'; when others => end case; if col_count = num_col + 68 then col_count <= 0; if row_count < num_row -1 then DTMG<='1'; end if; if row_count = num_row + 2 then row_count <= 0; DTMG<='1'; else row_count <= row_count +1; end if; else col_count <= col_count +1; end if; end if; end if; end process;Article: 83698
Hi Peter, Thanks for the info. I'm still a little confused though. Is this board expected to be purchased by customers? -KevinArticle: 83699
Hi John, the clock is actually 360 MHz divided by 7. It's an asyncronous clock like this "--___--". However the data goes at 360 MHz SDR. I have to use SDR, because the LCD doesn't support DDR. regards, Benjamin
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