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Messages from 120900

Article: 120900
Subject: Re: synthesis translate_off
From: "Tim (one of many)" <tim@nooospam.roockyloogic.com>
Date: Tue, 19 Jun 2007 22:56:34 +0100
Links: << >>  << T >>  << A >>
Kuo wrote:
> Does anyone if "//synthesis translate_off" in Xilinx is also honored by 
> ASIC synthesis tool (Design compiler) ?
> 
> Thanks

"synopsys translate_off" is, AFAIK, the original.

Article: 120901
Subject: Re: EDK - Microblaze question
From: "Vasanth Asokan" <vasanth@xilinx.com>
Date: Tue, 19 Jun 2007 14:59:32 -0700
Links: << >>  << T >>  << A >>
The warning comes about because you are trying to initialize this 
partitioned application into _BRAM_. When the bitstream is downloaded, your 
app won't work since only a part of it is present in the bitstream. But if 
you are downloading everything via XMD, then you are fine. So depending on 
what you are trying to do, the warning could be something real you have to 
watch out for.

You can use the linker script generator for partitioning ELf setions between 
different memories. It works and no, there is no confusion between the code 
segments as someone else pointed out.

Vasanths

"Fred" <fred@n0spam.com> wrote in message 
news:4673db4e$0$30318$fa0fcedb@news.zen.co.uk...
> Is there a method of using external RAM (Generic external Memory) where 
> the data, heap and stack can be located? Ideally the code would remain in 
> BRAM so not to require additional external non-volatile memory.
>
> I've tried altering the loader script to indicate a different address 
> range for the data side but I come up with:
> WARNING:MDT - Elf file TestApp_Memory/executable.elf does not reside 
> completely within BRAM memory of processor microblaze_0.
>
> Is there an example I can use as a starting point - if one exists!
> 



Article: 120902
Subject: [Announce] Linux 2.6.20 on MicroBlaze now available
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Wed, 20 Jun 2007 08:34:43 +1000
Links: << >>  << T >>  << A >>
Hi folks,

Just a quick announcement that PetaLogix has released version 0.20 of 
our PetaLinux environment, which includes Linux kernel 2.6.20 support 
for MicroBlaze (2.4.31 kernel is also available and supported).

It's a free download from

http://developer.petalogix.com

along with pages and pages of documentation, getting started and 
tutorial guides.

Both the kernel and u-boot bootloader are automatically configured by 
our autoconfig BSP generation tools (included for free), so board 
bringup is a snap.

PetaLinux contains kernel, library and application sources, GCC tools, 
hardware reference designs, and tools to tie it all together.  Basically 
everything you need to work with Linux on the MicroBlaze (except ISE and 
EDK of course!)

EDK 9.1 reference designs (both prebuilt and build yourself) are 
included for Xilinx ML401, and Spartan3E-500 and -1600 boards. 
PetaLinux comes with prebuilt binary demos for these boards in both 2.4 
and 2.6 kernels, so you can quickly try it out for yourself.

ISE and EDK versions 8.1 though 9.1 are supported.  You need a Linux 
workstation to work most effectively with PetaLinux, although mixed 
Windows/Linux setups are possible.

Please use the long-running microblaze-uclinux list for feedback and 
discussion, bug reports and so on.  See here for details:

http://developer.petalogix.com/wiki/UserGuide/GettingHelp

Have fun!

John

Article: 120903
Subject: Re: Graduate/Junior FPGA Designer concerns
From: Totally_Lost <air_bits@yahoo.com>
Date: Tue, 19 Jun 2007 20:11:24 -0700
Links: << >>  << T >>  << A >>
On Jun 17, 3:08 pm, freeplatypus <freeplaty...@gmail.com> wrote:
> Can anyone relate to this?
> Were this studies big mistake?

People looking for making a life long job decision based on a single
skill, are likely to be strongly disappointed at some point in their
ability to get and keep a job. Serous breadth not only allows for
greater choices in initial hiring out of school (because you are
useful to employers in many different product roles) but in your
ability to work in your field for the next 60 years. All forms of
engineering (not just narrow EE roles) including materials,
mechanical, industrial, software, computer, control systems, RF and
power give you the breadth to take small project from cradle to grave
(which would otherwise require a team of a dozen or more specialists
that might well cause the product to fail as a committee camel).

You gain those skill sets by actively choosing significant diversity
in your electives, your choices for internships, your choices for part
time work in school, and your choices for part and full time work
after graduation. Specifically choosing to go to work for small
companies, is often an important job choice in your lifetime, as
smaller companies doing product development frequently need
individuals capable of successfully wearing multiple hats in a
project ... or choosing a large company where mobility between many
different product areas.

The ability to grow into effective roles as a project lead, architect
or product manager require the abilities to visualize, and understand
a broad range of skills necessary to see the product from conception
to customer ship and beyond.

If at some point you choose to start your own business or branch out
into high value consulting, the ability to understand not only the
specific technology, but the application it's being applied will be
critical to your success.

Your years at school are just the foundation for a lifelong learning
quest ... you are almost certainly never going to make a successful
living on just what you were taught at school ... except the ability
to learn any task set before you.

Find mentors everywhere you go ... in school, in life, in your family,
in your job ... talk about life skills that enabled successes, and
choices that lead to failures, and reflect on those stories in ways
that affect your life ... learn from others mistakes and failures.

As an employer, project leader, small business owner, and mentor
working with students and young engineers I've seen a common tread ...
the toughest period for every grad is the first couple jobs where
project responsibility is passed to the newbie engineer, and they have
to face the initial struggle of "I wasn't taught that in school" and
are forced to understand they MUST learn the project, and become the
expert for that product. For some that growth happens in the first
several weeks of their first job, for others it might be 3-7 years
down the road while facing some very difficult project demands and
inner reflections about ones abilities. Poor managers might miss this
allowing you to fail, better managers will make sure the right
mentoring is in place to capitalize on your personal growth.

I generally suggest looking at working for smaller engineering
companies, both while in school, and after graduation, that allow you
to expand your skills, and grow professionally in ways that avoid a
narrow dead end specialized job will only set you up for failure later
in life when there are radical changes in technology that obsolete
your narrow skill set.


Article: 120904
Subject: Interesting problems about high performance computing
From: "hitsx@hit.edu.cn" <hitsx@hit.edu.cn>
Date: Tue, 19 Jun 2007 22:41:24 -0700
Links: << >>  << T >>  << A >>
There is a software application which demonds huge computation. My aim
is to port the software program into hardware. So first of all, I need
to evaluate the required volumn of computation.

The situation is that the software program will need up to 22 hours on
personal computer (P4 3.06G, 2GB RAM) to finish the computation, while
the operations mostly are float-point multiplications and additions. I
need to finish the computation by hardware in serveral minites. Is it
possible?

Another problem is that which kind of hardware platforms is
perferable. I have checked that the production provided by
Nallatech(www.nallatech.com) seems suitable for me. I am still
wondering whether I should choose some boards with multiple DSP
processors on it? I think DSP processors are better at floating point
operations.


Article: 120905
Subject: Re: Weird behavior in debuggin using XMD
From: Zara <me_zara@dea.spamcon.org>
Date: Wed, 20 Jun 2007 08:07:01 +0200
Links: << >>  << T >>  << A >>
On Tue, 19 Jun 2007 11:08:07 -0700, kislo <kislo02@student.sdu.dk>
wrote:

>I have implemented a base builder system for the Spartan3e starter kit
>where i have a TestApp_memory.c which is downloaded in blockram and
>works fine. Then i have another program also generated by the base
>system builder, TestAppPeripheral.c which i download to the extern
>memory with XMD which downloads fine and execute with con address. But
>when it tests interrupts in dosent catch any interrupts, so i wanted
>to debug the program to see if i could locate the problem (there is
>definitely some weird beheaviour since the interrupts sometimes
>work !!)
>But anyway, i wanted to debug the program using the debugger, i
>connected fine and started to debug, i placed a breakpoint at the
>start of the interrupt test, and i started debuggin. Now comes the
>weird beheaviour, the programtracer jumps back and forward and
>sometimes skips instructions. It evens jumps into a if statement which
>it cannot go into according to the data.
>So anyone have any ideer what is going on ?
>Maybe the base system builder code is rubish?
>Anyone have had trouble using interrupts and XMD together ?


To debug, it is always easier if you turn all optimising off. If you
take a llok at the asseembler code, you will see that, when
optimising, C instructions are translated into severla steps, and
steps from some intsructions may be interleaved. Thta geives a better
through put, but also lots of headaches to unaware programmers!

Best regrads, 

Zara

Article: 120906
Subject: Re: Interesting problems about high performance computing
From: Totally_Lost <air_bits@yahoo.com>
Date: Tue, 19 Jun 2007 23:30:57 -0700
Links: << >>  << T >>  << A >>
On Jun 19, 11:41 pm, "h...@hit.edu.cn" <h...@hit.edu.cn> wrote:
> There is a software application which demonds huge computation. My aim
> is to port the software program into hardware. So first of all, I need
> to evaluate the required volumn of computation.

put some counters in the software version to total the required number
of operations on each variable in the calculation, and you can get
that answer fairly accurately.

Next take a good look at the algorithm, for concurrency and necessary
serial operations.

Any place you have a different data value used in each iteration a
loop, you have the chance to do calculate two or more values per loop
iterations (unrolling the loop) to gain parallelism. If however, there
are serializations which offer no restructuring to parallelize, then
the application might well be done best with a fast cpu/cache rather
than a slower FGPA. Look at Amdahl's  law regarding possible speedup
between parallel and serial sections of a program.

In some cases, even a serial operation that is lengthy, may see some
gains by pipelining, as another form of parallelization. So be
constructive in looking for parallelism in the algorithm. In some
other cases, using a completely different algorithm which completes
the task equally, may be the only means for gaining the required
parallelism. This sometimes requires some thought, like replacing
recursion with linear code, to "unroll" the implied loops. or
reordering the sequence over operations ... such as loop combining
where one or more loops process the same data points.

> The situation is that the software program will need up to 22 hours on
> personal computer (P4 3.06G, 2GB RAM) to finish the computation, while
> the operations mostly are float-point multiplications and additions. I
> need to finish the computation by hardware in serveral minites. Is it
> possible?

In general, most FPGA implementations see speed improvements between
2X to 200X, sometimes worse, rarely much better, unless the main
software loop is very small, and the algorithm has exceptional
parallelism. The reason is that FPGA cycle times are relatively slow
compared to GHz multi-issue pipelined CPUs. It doesn't really mater
much if the data is fixed or floating point, what matters is the
degree of parallelism you can introduce and exploit in the FPGA. You
are looking for speed up's on the order of  22*60/3 = 440X which
rather implies the calculations of the algorithm must have a very
small kernel, and extremely easy to parallelize with little or no
serial component (such as memory accesses) to meet your goals in an
FPGA ... certainly possible with some careful work, but not
necessarily for all algorithms or problems.


> Another problem is that which kind of hardware platforms is
> perferable. I have checked that the production provided by
> Nallatech(www.nallatech.com) seems suitable for me. I am still
> wondering whether I should choose some boards with multiple DSP
> processors on it? I think DSP processors are better at floating point
> operations.

Beside looking at FPGAs, you might also consider GPUs, Cell
processors, and a different CPU architecture which has better multi-
issue floating point, cache, or memory performance ... including
tuning the application for exactly that CPU/Memory configuration.

Have fun!
John


Article: 120907
Subject: Re: Quartus Timing Analyzer question
From: Zorjak <Zorjak@gmail.com>
Date: Wed, 20 Jun 2007 07:58:52 -0000
Links: << >>  << T >>  << A >>
Thanks again, David. You realy helped.

I successed to get rid of this warning but I am still not shure
how:):):). For now its ok, but obviosly | have to learn much more.

Anywhay, this literature you recomended to me was realy helpfull.
Thanks again

dkarch...@gmail.com wrote:
> > When you said "define clock corectly", you meant define them in timing
> > analyzer. Am I right?
>
> Yes, all clocks need to be correctly defined in the Timing Analyzer
>
> > I did that and I found which paths have "Hold
> > Violation". But I don't know what to do now. What should I do to get
> > rid of this "Non operational path".
>
> In your case, I would continue focusing on why you have clock skew. A
> clean design should not have any clock skew to beging with, so changes
> in your HDL will likely be needed. As I said before, try doing a "List
> path" operation (use button-2 mouse on Hold Clock panel), and expand
> the clock skew message to get the detail path of both the source clock
> and the destination clock. You can locate to the chip planner and/or
> tech map viewer to visualize the path. Check specifically for
> combinational logic in your clock path, and if you find it, try to
> change your HDL to get rid of it (e.g. use the register's clock enable
> instead on an AND gate in your clock path).
>
> The other thing you want to check is your global clock utilization.
> Check the "Global Signals" under the "Resource Section" in the fitter
> report and confirm you are not running out of global signals, and that
> the clock in question has access to global resources.
>
> Also, take a look at the "Timing Optimization Advisor" and read
> http://www.altera.com/literature/hb/qts/qts_qii52005.pdf and
> http://www.altera.com/literature/hb/qts/qts_qii5v1_02.pdf for more
> ideas.
>
> Good luck.
>
> -David Karchmer
>  Altera


Article: 120908
Subject: How to use UART on Spartan 3E Starter Kit
From: Jay <jaycp.iitkgp@gmail.com>
Date: Wed, 20 Jun 2007 01:12:17 -0700
Links: << >>  << T >>  << A >>
Hello,

Can anybody help me with some reference designs, through which I can
get an insight to using UART on Spartan 3E Starter Kit ? I have
downloaded few reference designs which uses UART but I am not getting
exact hands on experience.

Thanks in advance.

Jayesh :-|


Article: 120909
Subject: Re: How to use UART on Spartan 3E Starter Kit
From: Antti <Antti.Lukats@googlemail.com>
Date: Wed, 20 Jun 2007 08:17:25 -0000
Links: << >>  << T >>  << A >>
On Jun 20, 10:12 am, Jay <jaycp.iit...@gmail.com> wrote:
> Hello,
>
> Can anybody help me with some reference designs, through which I can
> get an insight to using UART on Spartan 3E Starter Kit ? I have
> downloaded few reference designs which uses UART but I am not getting
> exact hands on experience.
>
> Thanks in advance.
>
> Jayesh :-|

the only way to gain experience is to use your hands and brain.

there are plenty of examples demonstration UART use for the starterkit

Antti



Article: 120910
Subject: Re: Spartan-3E DIG-3E1600 Development Board Kit
From: Sandro <sdroamt@netscape.net>
Date: Wed, 20 Jun 2007 01:47:51 -0700
Links: << >>  << T >>  << A >>
On 1 Giu, 06:45, John_H <newsgr...@johnhandwork.com> wrote:
>
> I got the board from them early on as well.  I figured the Xilinx
> exclusivity was the reason for "not currently for sale" but since XIlinx
> has the "buy from Digilent" link, if anyone wants this board...
>
> Call Digilent, please!

Hi all,
this is just to inform that I contacted by e-mail digilent about 3
weeks ago and
their answer was:
   "We don't have them for sale at this time but we will have them in
the near future..."

well... now is the "near future" ;-)  the board is available for sale
from digilent !

Sandro


Article: 120911
Subject: Re: How to use UART on Spartan 3E Starter Kit
From: Jay <jaycp.iitkgp@gmail.com>
Date: Wed, 20 Jun 2007 01:50:21 -0700
Links: << >>  << T >>  << A >>
You are right Antii,
Hands on experience can only get me exact details about spartan 3e kit
and related peripherals ... thanks for the prompt reply ...



Article: 120912
Subject: DFS to generate Frequencies slightly apart
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Wed, 20 Jun 2007 08:53:47 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hello,

for some legacy instrument, I need to replace AM796X Taxichips doing a
9B<->11B encoding/decoding. The Taxichip is long EOL, and replacement chips I
know only do 8B<->10B or 10B<-> 12B
Data encoding can easily be done with BRAMs as ROM, and also the aligned
receive data stream. For receiving, I plan to use the XAPP224
datarecovery. However having the data recovery run at the same nominal
frequency like the transmitter, two bits can be received in one receiver
clock cycle. This will make data alignment harder. Running the receiver
clock a little bit higher, say 125 vs 125.1 MHz, the two bit receive
situation can be avoided. The Xilinx DFS can "only" multiply by 2..32 and
divide by 1..32. With a clock frequency of 20 MHz, I could run at
transmitter at 125 MHZ and and the receiver at 130 MHz, imho too far apart.

Any idea how to generate frequencies slightly apart?

Thanks

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 120913
Subject: Re: Interesting problems about high performance computing
From: Christian Kirschenlohr <c.kirschenlohr@gmx.de>
Date: Wed, 20 Jun 2007 11:03:56 +0200
Links: << >>  << T >>  << A >>
Hello
> Another problem is that which kind of hardware platforms is
> perferable. I have checked that the production provided by
> Nallatech(www.nallatech.com) seems suitable for me. I am still
> wondering whether I should choose some boards with multiple DSP
> processors on it? I think DSP processors are better at floating point
> operations.
> 
perhaps, this one could suit your needs:
http://www.mathstar.com/products.html

Regards

Christian

Article: 120914
Subject: Suggestions for Xilinx based evaluation board for image processing
From: Marek Kraft <sepher_grupy@o2.pl>
Date: Wed, 20 Jun 2007 02:07:14 -0700
Links: << >>  << T >>  << A >>
Hello!

I have been playing with image processing on FPGA for some time now,
and the results seem interesting (I am working mainly on image
preprocessing and edge/corner detection algorithms). My main research
platform was the S3BOARD from Digilent/Xilinx, but I got to the point,
where RS232, or RS232 <-> USB converters do not offer sufficient speed
(imagine sending a 512x512 image to the board and then waiting for the
results, even in grayscale). Therefore, I'd like to invest some money
in a more advanced evaluation board. For now, the Virtex-4-based Video
Starter Kit seems to be the most reasonable choice for me. Is anyone
here using this kit? The opinions I have found while googling the net
(like the one here: http://www.embeddedrelated.com/usenet/embedded/show/54852-1.php)
are however somewhat disencouraging. I'd like to know if it's hard to
develop my own applications for the daughtercard without having to use
the Matlab/Simulink software (just plain HDL). I also tried to find
some other boards for this task (a solution that is functioning out-of-
the-box would be ideal). The price of boards by Vmetro and
Hitechglobal is an overkill for me. I considered also buying the
XUPV2P board from Digilent design a CameraLink compatible interface
for it, but I fear that V2Pro devices are a bit outdated and Xilinx
will stop supporting this product line. I'd also like to know if it is
better to use dedicated National Semiconductor chips to do the
deserialization, or try to use the IOB/multiple clocks based approach?
Thanks for any suggestions.


Article: 120915
Subject: Re: DFS to generate Frequencies slightly apart
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 20 Jun 2007 10:13:03 +0100
Links: << >>  << T >>  << A >>
Hi Uwe,

"Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> wrote in message 
news:f5apur$o4p$1@lnx107.hrz.tu-darmstadt.de...
> Hello,
>
> for some legacy instrument, I need to replace AM796X Taxichips doing a
> 9B<->11B encoding/decoding. The Taxichip is long EOL, and replacement 
> chips I
> know only do 8B<->10B or 10B<-> 12B
> Data encoding can easily be done with BRAMs as ROM, and also the aligned
> receive data stream. For receiving, I plan to use the XAPP224
> datarecovery. However having the data recovery run at the same nominal
> frequency like the transmitter, two bits can be received in one receiver
> clock cycle. This will make data alignment harder.
>
But not much, are you man or mouse! ;-)

> Running the receiver
> clock a little bit higher, say 125 vs 125.1 MHz, the two bit receive
> situation can be avoided. The Xilinx DFS can "only" multiply by 2..32 and
> divide by 1..32. With a clock frequency of 20 MHz, I could run at
> transmitter at 125 MHZ and and the receiver at 130 MHz, imho too far 
> apart.
>
> Any idea how to generate frequencies slightly apart?
>

20 * 19 / 3 = 126.67

Seriously, go with the exact 125MHz Rx clock thing. The additional 
complexity will be worth it as you design will be a _lot_ more jitter 
tolerant. Think what happens as the data edges and the clock edges start to 
align. If there's jitter, the thing can flip back and forth between states. 
E.g., if these numbers represent the number of bits received:-

1,1,1,1,0,2,0,1,1,1,1

even though you really wanted:-

1,1,1,1,0,1,1,1,1,1,1


Cheers, Syms. 



Article: 120916
Subject: Re: DFS to generate Frequencies slightly apart
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 20 Jun 2007 10:18:10 +0100
Links: << >>  << T >>  << A >>
"Symon" <symon_brewer@hotmail.com> wrote in message 
news:f5ar4d$2lo$1@aioe.org...
> Hi Uwe,
...and another thing. If you use the Tx clock as your Rx sampling clock, 
it's trivial to pass data between the Rx and Tx clock domains. Well worth 
the extra logic.
HTH, Syms. 



Article: 120917
Subject: Re: Linux 2.6.20 on MicroBlaze now available
From: Guru <ales.gorkic@email.si>
Date: Wed, 20 Jun 2007 02:41:23 -0700
Links: << >>  << T >>  << A >>
On Jun 20, 12:34 am, John Williams <jwilli...@itee.uq.edu.au> wrote:
> Hi folks,
>
> Just a quick announcement that PetaLogix has released version 0.20 of
> our PetaLinux environment, which includes Linux kernel 2.6.20 support
> for MicroBlaze (2.4.31 kernel is also available and supported).
>
> It's a free download from
>
> http://developer.petalogix.com
>
> along with pages and pages of documentation, getting started and
> tutorial guides.
>
> Both the kernel and u-boot bootloader are automatically configured by
> our autoconfig BSP generation tools (included for free), so board
> bringup is a snap.
>
> PetaLinux contains kernel, library and application sources, GCC tools,
> hardware reference designs, and tools to tie it all together.  Basically
> everything you need to work with Linux on the MicroBlaze (except ISE and
> EDK of course!)
>
> EDK 9.1 reference designs (both prebuilt and build yourself) are
> included for Xilinx ML401, and Spartan3E-500 and -1600 boards.
> PetaLinux comes with prebuilt binary demos for these boards in both 2.4
> and 2.6 kernels, so you can quickly try it out for yourself.
>
> ISE and EDK versions 8.1 though 9.1 are supported.  You need a Linux
> workstation to work most effectively with PetaLinux, although mixed
> Windows/Linux setups are possible.
>
> Please use the long-running microblaze-uclinux list for feedback and
> discussion, bug reports and so on.  See here for details:
>
> http://developer.petalogix.com/wiki/UserGuide/GettingHelp
>
> Have fun!
>
> John

Hi John,

That is a great news.
Is PPC supported in Xilinx ML401 reference design?

Cheers,

Guru


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From: Laurent Pinchart <laurent.pinchart@skynet.be>
Subject: Re: How to simulate testbenches using the ISE simulator in linux
Newsgroups: comp.arch.fpga
Date: Wed, 20 Jun 2007 12:04:52 +0200
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Hi Ankit,

> I think it would be really great if you could tell the exact bash script
> because i would not mind that too..My aim here is to run xilinx on linux
> it does not matter how it is done.. 

Ok. Here is a quick howto. I assume you have a basic knowledge of bash
scripting. If not, there are plenty of documentation available online.

0. Directories and file names

The examples below are based on the following project directory hierarchy.

/bench
        /vhdl                   VHDL test benches
        /verilog                Verilog test benches
/rtl
        /vhdl                   VHDL source files
        /verilog                Verilog source files
/sim
        /rtl_sim
                /bin            Simulation scripts
                /log            Simulation logs
                /out            Simulation results
                /run            Simulation resources
/syn
        /xst
                /bin            Synthesis scripts
                /log            Synthesis logs
                /out            Synthesis results
                /run            Synthesis resources

Only VHDL and Verilog sources can be simulated this. Coregen can generate
VHDL or Verilog simulation modules for (some) IP cores, and schematics can
be converted to VHDL or Verilog as well.

If you want to adapt the hierarchy to your needs (or even flatten everything
out), you will have to modify the simulation script.

1. Environment variables

First of all, make sure your environment variables are up-to-date. The
Xilinx binary and shared library directories should be accessible through
$PATH and $LD_LIBRARY_PATH. If you allowed the Xilinx ISE installer to
modify your system configuration (in /etc) this might be done already.

Check the $XILINX environment variable.

$ echo $XILINX
/opt/xilinx/ise9.1i/

If the variable is not set, you can just source the configuration script
(change the path to match your ISE installation directory).

$ source /opt/xilinx/ise9.1i/settings.sh

You will have to repeat this step for any shell instance you want to work
with. You can alternatively add the above line to your bash startup script
(.bashrc or .bash_profile).

2. Writing the test bench

The entity under test (EUT) must be instantiated in a portless top-level
entity that will drive the EUT inputs. I usually write tests in VHDL, but
you might be able to convert graphical waveforms into VHDL/Verilog code. I
haven't tested this myself.

The simulation script assumes that your top-level test bench entity is named
${module}_tb (for instance, if the EUT entity is named counter, the
top-level test bench entity should be named counter_tb). This can be
overridden when running the simulation script, but it's a good idea to
stick to a coherent naming if you have no reason to do otherwise.

3. Preparing the simulation resources

Now that your development environment is ready, you will have to prepare the
simulation resource files.

The simulation script goes in sim/rtl_sim/bin. As the news server doesn't
seem to like attachments, I included it inline. Let me know if it comes out
badly.

---------------- sim.sh --------------------
#!/bin/sh

set -e

if [ $# -lt 1 ]; then
        self=`basename "$0"`
        echo "Usage: ${self} [options] module"
        exit 1
fi

do_compile=true
do_wave=false
entity=

while [ $# -gt 0 ]; do
        case $1 in
        -no-compile)
                do_compile=false
                ;;
        -wave)
                do_wave=true
                ;;
        -entity)
                entity=$2
                shift
                ;;
        -*)
                echo Invalid argument $1
                exit 1
                ;;
        *)
                module=$1
                ;;
        esac

        shift
done

if [ x${entity} == x ]; then
        entity=${module}_tb
fi

if $do_compile; then
    vhpcomp -intstyle ise -work work=../out/work -prj ../run/${module}.prj
    fuse -work work=../out/work -top ${entity}
fi

../out/work/${entity}/lin/xsimbhv_${entity} -tclbatch ../run/${module}.tcl \
        -wavefile ../out/${module}.xwv

if $do_wave; then
    isimwave ../out/${module}.xwv &
fi
-----------------------------------------------

Command-line simulation requires a project file (.prj) listing the
VHDL/Verilog source files and a simulation script (.tcl) with the
simulation commands.

Here are a sample project file and simulation script that goes in
sim/rtl_sim/run.

---------------- sdclk.prj --------------------
vhdl work ../../../rtl/vhdl/sdclk.ent.vhd
vhdl work ../../../rtl/vhdl/sdclk.beh.vhd
vhdl work ../../../bench/vhdl/sdclk.test.vhd
-----------------------------------------------

---------------- sdclk.tcl --------------------
scope /sdclk_tb/

ntrace select -o on -n sd_frequency
ntrace select -o on -n sd_stop
ntrace select -o on -n sd_enable
ntrace select -o on -n sd_clk_in
ntrace select -o on -n sd_clk_out

ntrace start
run all
quit
-----------------------------------------------

The project file is pretty self-explanatory. Each line adds a source file to
the simulation. The first keyword is the source file language, the second
keyword the library which the source will be compiled into, and the third
keyword is the source file path and name.

The simulation script select signals that will be recorded in the output
waveform (ntrace directive) and start the simulation. The scope directive
can be used to navigate in the design hierarchy and select internal
signals.

More information on the ISE simulator and the simulation script commands can
be found at
http://
toolbox.xilinx.com/docsan/xilinx9/help/iseguide/mergedProjects/xsim/whnjs.htm

3. Running the simulation

The simulation script usage is as follows.

------------ Sample simulation session ----------
$ ./sim.sh

Usage: sim.sh [options] module

-entity         Top entity name. Defaults to module_tb.
-no-compile     Don't compile the sources. Useful if you modified the
                simulation script and want to rerun the simulation without
                recompiling the sources.
-wave           Automatically launch the waveforw viewer upon completion.

$ ./sim.sh -wave sdclk

Compiling vhdl file "rtl/vhdl/sdclk.ent.vhd" in Library work.
Entity <sdclk> compiled.
Compiling vhdl file "bench/vhdl/sdclk.test.vhd" in Library work.
Entity <sdclk_tb> compiled.
Entity <sdclk_tb> (Architecture <bhv_sdclk_tb>) compiled.
Compiling vhdl file "rtl/vhdl/sdclk.beh.vhd" in Library work.
Entity <sdclk> (Architecture <str_sdclk>) compiled.
Parsing "../run/sdclk.prj": 0.27
Codegen   work/sdclk: 0.00
Codegen   work/sdclk_tb: 0.00
Codegen   work/sdclk/str_sdclk: 0.00
Codegen   work/sdclk_tb/bhv_sdclk_tb: 0.00
Release 9.1.03i - ISE Simulator Fuse J.33
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
Building ../out/work/sdclk_tb/lin/xsimbhv_sdclk_tb
Release 9.1.03i - ISE Simulator Engine J.33
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
This is a Lite version of ISE Simulator.
Simulator is doing circuit initialization process.
Finished circuit initialization process.

** Failure:Simulation successful (not a failure).  No problems detected.
User(VHDL) Code Called Simulation Stop

 Simulation stopped when executing process: sdclk.test.vhd:stimuli
 on line 105 in file "bench/vhdl/sdclk.test.vhd"
-----------------------------------------------

The simulation script will use ${module}_tb as the top-level entity name. If
your top-level entity has a different name, use the -entity option.

I hope this helps. I've been using the ISE simulator with success for some
time now with command-line simulation. You should install ISE 9.1i (with
the latest service pack) or newer, as ISE 8.2i has lots of simulation bugs
that have been fixed in 9.1i (including crashes).

Best regards,

Laurent Pinchart


Article: 120918
Subject: Re: another Forth CPU design
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: 20 Jun 2007 12:07:14 +0200
Links: << >>  << T >>  << A >>
Frank Buss <fb@frank-buss.de> writes:

> When the design is finished, I want to implement an assembler for the
> system in Forth. How could the mnemonics look like and are there any good
> examples of assemblers in Forth, which could be used to implement my ISA?
> For testing, an emulator would be nice, too, but this should be easy to
> implement, because of the simple and orthogonal ISA.

I once implemented a microcode assembler generator in Common Lisp. The
specification for the mnemonics and arguments were written in Verilog
(as `define statements). The program would read this specification and
generate an assembler on the fly and then assemble the
microprogram. There were only two hard-coded instructions: ORG and
LABEL. The assembler source would be written using Common Lisp
syntax. The actual assembler generator was only a couple hundred lines
long.

The advantage was that the Verilog code was consistent with the
assembler and the designer did not have to fiddle with lex, yacc
etc. Only the Verilog source had to be updated to add new instructions
and/or parameters.


Petter

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 120919
Subject: Re: Graduate/Junior FPGA Designer concerns
From: freeplatypus <freeplatypus@gmail.com>
Date: Wed, 20 Jun 2007 03:40:40 -0700
Links: << >>  << T >>  << A >>
On Jun 20, 5:11 am, Totally_Lost <air_b...@yahoo.com> wrote:
> On Jun 17, 3:08 pm, freeplatypus <freeplaty...@gmail.com> wrote:
>
> > Can anyone relate to this?
> > Were this studies big mistake?
>
> People looking for making a life long job decision based on a single
> skill, are likely to be strongly disappointed at some point in their
> ability to get and keep a job. Serous breadth not only allows for
> greater choices in initial hiring out of school (because you are
> useful to employers in many different product roles) but in your
> ability to work in your field for the next 60 years. All forms of
> engineering (not just narrow EE roles) including materials,
> mechanical, industrial, software, computer, control systems, RF and
> power give you the breadth to take small project from cradle to grave
> (which would otherwise require a team of a dozen or more specialists
> that might well cause the product to fail as a committee camel).
>
> You gain those skill sets by actively choosing significant diversity
> in your electives, your choices for internships, your choices for part
> time work in school, and your choices for part and full time work
> after graduation. Specifically choosing to go to work for small
> companies, is often an important job choice in your lifetime, as
> smaller companies doing product development frequently need
> individuals capable of successfully wearing multiple hats in a
> project ... or choosing a large company where mobility between many
> different product areas.
>
> The ability to grow into effective roles as a project lead, architect
> or product manager require the abilities to visualize, and understand
> a broad range of skills necessary to see the product from conception
> to customer ship and beyond.
>
> If at some point you choose to start your own business or branch out
> into high value consulting, the ability to understand not only the
> specific technology, but the application it's being applied will be
> critical to your success.
>
> Your years at school are just the foundation for a lifelong learning
> quest ... you are almost certainly never going to make a successful
> living on just what you were taught at school ... except the ability
> to learn any task set before you.
>
> Find mentors everywhere you go ... in school, in life, in your family,
> in your job ... talk about life skills that enabled successes, and
> choices that lead to failures, and reflect on those stories in ways
> that affect your life ... learn from others mistakes and failures.
>
> As an employer, project leader, small business owner, and mentor
> working with students and young engineers I've seen a common tread ...
> the toughest period for every grad is the first couple jobs where
> project responsibility is passed to the newbie engineer, and they have
> to face the initial struggle of "I wasn't taught that in school" and
> are forced to understand they MUST learn the project, and become the
> expert for that product. For some that growth happens in the first
> several weeks of their first job, for others it might be 3-7 years
> down the road while facing some very difficult project demands and
> inner reflections about ones abilities. Poor managers might miss this
> allowing you to fail, better managers will make sure the right
> mentoring is in place to capitalize on your personal growth.
>
> I generally suggest looking at working for smaller engineering
> companies, both while in school, and after graduation, that allow you
> to expand your skills, and grow professionally in ways that avoid a
> narrow dead end specialized job will only set you up for failure later
> in life when there are radical changes in technology that obsolete
> your narrow skill set.

Well first of all:
1. I am engaged in (high level) software development since this is the
way I can make a living during studies. Sometimes this is the only
choice (better then weekend work at supermarket).
2. I enjoy programming logic, making tests for them and creating
firmware because I can see my result in physical implementation (at
the end, there is usually a device that does something)
3. I would love to broader my knowledge, but sometime lack ideas,
because I live and work in limited environment

Second of all:
How can one specialize for senior job (those which require many years
of experience) and keep developing skills in such a broad technology
range to find employment in case given technology goes out of use?

Third, last of all:
I never thought that 5 year study are going to provide knowledge for
life long job, but concerning current situation, it seems that there
was no point in spending these 5 years in EE as there are very few job
offers for starters (this included low paid internships).

That's why I am asking. How does it look in Europe? Maybe I am looking
at wrong message boards look for a job? Almost no internships offered.
Almost no entry level jobs ( or even better, job offer for entry
engineer but with multiple years of experience - I guess that salary
is for entry).

I must be missing a big picture? If not, it seems that EE is in very
poor condition.


Article: 120920
Subject: Re: MIG for Virtex-4 DDR dimm, only 165 Hz?
From: subint <subin.82@gmail.com>
Date: Wed, 20 Jun 2007 12:12:37 -0000
Links: << >>  << T >>  << A >>
On Jun 19, 11:59 pm, Patrick Dubois <prdub...@gmail.com> wrote:
> Hello,
>
> Why does Xilinx MIG controller support DDR dimm at only 165 MHz in
> Virtex-4 ? (175MHz in -12). I remember seeing a 200 MHz reference
> designs for DDR memory in a V2Pro!
>
> Quoting from the white paper "Memory Interfaces Made Easy with Xilinx
> FPGAs and the Memory Interface Generator":
> "For high-performance applications, pushing the limits of the memory
> interface bandwidth like 533 and 667 Mb/s per pin DDR2 SDRAMs, Xilinx
> offers the Virtex=E2=84=A2-4 and Virtex-5 FPGAs, which are capable of meeting
> the highest bandwidth requirements of most systems today."
>
> 533? That's like 266 MHz. 200 MHz should be easy for MIG then. 165 MHz
> is a far cry from the marketed 266 MHz.
>
> AR23862 answers part of this question (something about idelay jitter).
> Still, I feel that the MIG design should be able to extract more
> performance from the V4 fabric.
>
> Side question, why can MIG acheive 220 MHz with DDR2? That's like 33%
> faster.
>
> Thanks.
>
> Patrick

The controller generated by MIG tool is not efficient. There was lot
of bugs in the code i generated using 1.6 version. They are not sure
it's works in the higher frequency. That's why it's shown 165 as the
limit. But you can make changes in the code and can try to work for
higher frequency.
Regards
Subin


Article: 120921
Subject: Re: Linux 2.6.20 on MicroBlaze now available
From: "Ben Jones" <ben.jones@xilinx.com>
Date: Wed, 20 Jun 2007 13:23:26 +0100
Links: << >>  << T >>  << A >>

"Guru" <ales.gorkic@email.si> wrote in message 
news:1182332483.106686.23690@p77g2000hsh.googlegroups.com...
>
> That is a great news.
> Is PPC supported in Xilinx ML401 reference design?

Seems unlikely, as the ML401 has a Virtex-4 LX chip on it, which does not 
have an embedded PowerPC block. That would be the FX family, available on 
the ML403 board.

Cheers,

       -Ben- 



Article: 120922
Subject: Re: Graduate/Junior FPGA Designer concerns
From: Christian Kirschenlohr <c.kirschenlohr@gmx.de>
Date: Wed, 20 Jun 2007 15:05:58 +0200
Links: << >>  << T >>  << A >>
Hi freeplatypus,
actually, I change my employer in August. So I want to tell you some 
things about my jobsearch. The best thing is presenting your CV on 
websites like monster or networking platforms like XING. I got a lot of 
good and interesting job offers, which were never mentioned on the 
classic platforms or search engines for jobs. So try this.
Just one thing: In germany a lot of companies have problems to get good 
and enough engineers.


Regards Christian

Article: 120923
Subject: Re: Linux 2.6.20 on MicroBlaze now available
From: "stephen.craven@gmail.com" <stephen.craven@gmail.com>
Date: Wed, 20 Jun 2007 13:42:48 -0000
Links: << >>  << T >>  << A >>
I believe that Dr. Williams' work targets only the MicroBlaze.  In
which case the ML401 could be supported.

Stephen

On Jun 20, 8:23 am, "Ben Jones" <ben.jo...@xilinx.com> wrote:
> "Guru" <ales.gor...@email.si> wrote in message
>
> news:1182332483.106686.23690@p77g2000hsh.googlegroups.com...
>
>
>
> > That is a great news.
> > Is PPC supported in Xilinx ML401 reference design?
>
> Seems unlikely, as the ML401 has a Virtex-4 LX chip on it, which does not
> have an embedded PowerPC block. That would be the FX family, available on
> the ML403 board.
>
> Cheers,
>
>        -Ben-



Article: 120924
Subject: Re: Interesting problems about high performance computing
From: evansamuel@charter.net
Date: Wed, 20 Jun 2007 13:45:14 GMT
Links: << >>  << T >>  << A >>
Most engineers still don't realize the processing power of the FPGA. True,
today's processors operate at high clock frequencies.  People don't truly
understand how much of that raw speed is lost to processor overhead.
 I created a FPGA process for processing real time 1280pixel
32bit camera scans to identifiy the leading edge of incoming documents,
determine
the skew angle and rotate the image in realtime while the image was still
being scanned.  This process originally required 8 High speed DSP's with
significant
propagation delay and large amounts of memory.
I have also converted many software processes to the FPGA enviroment.
Each have had dramatic improvements in speed that no processor could
ever come close to matching.

Here is a short list of problems your software program may be
experiencing.

  1. Almost 25% to 50% your speed is lost to opcode and memory access.
This number varies depending on CPU cache efficiency.
  2. Depending on the software program size and memory access.  You
could be forcing excessive cache dumps and reload which can reduce
speed another 10 to 50%.
  3. You must then content with program efficiency.  Is the program
  optimized
for speed.
  4. Last, the efficiency of your software compiler.  Is it using extensive
use of libraries or inline code.

When a program is converted to hardware you eliminate items 1, 2, and 4. 
You
are left with program efficiency, how well it is translated to hardware.

The first thing to do is reorder the statements in the program.  Section the
program
into stages and identify the loop/repitition structure.  Each stage has a
dependency on the previous computation.  This
will usually lead to each stage having multiple computations.  These can be
executed in parallel in the FPGA and many equations can be executed in just
one
FPGA clock cycle.  After reordering the statements in the
proper order for hardware conversion, recompile the program and run to
insure in still functions correctly.  This is now your basic template for
conversion.

If you use large amounts of data in the program beyond the capacity of the
FPGA,
you will need to create a multi channel DMA controller w/cache.
This controller will provide access to each stage needing external memory.

Second, when using decimal calculation, determine the maximum decimal error.
Floating point offers many advantages but slows down computation, consume
large number of resources and add to the overall complexity of the hardware.
 You
should use fix point computation if possible.

Fix point decimal accuracy (decimal portion not including integer size)

 1 byte = 2 decimal places
 2 byte = 4 decimal places
 3 byte = 7 decimal places
 4 byte = 9 decimal places
 5 byte = 12 decimal places
 6 byte = 14 decimal places

Xilinx devices have built in multipliers (18x18) which are fast and save
hardware.
Division is possible but uses more resources.

A spartan3 can do the work.  The Virtex 2, and 4 are faster and offer more
memory and multipliers with the addition of CPU's to help with other tasks.
A DSP does provide avantages over a standard processor
but does not compare to the raw power of the FPGA.

evansamuel@charter.net



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