Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Sun, 24 Jun 2007 05:36:50 -0000, ghelbig@lycos.com wrote: >testbuilder.net appears to be dead. Would you mind sending me a copy? sure - gone (it's open source, in case anyone's wondering :))Article: 121101
Assuming that is in you HDL code, it is part of the many things that are good for simulation but do not synthesize. It might be beneficial to read up on what constructs of your preferred HDL can actually be synthesized. ---Matthew Hicks > On Jun 25, 4:08 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > >> EEngineer wrote: >> >> ... >> >>>>> I suspect >>>>> that "after 10ns" constraint is not accurate enough. >> ... >> >>> I did not use the ucf constraints file for the delay. Here is the >>> actual line of code I am using: >>> clock_rd <= clock after 20ns WHEN frame_done = '0' ELSE >>> clock_dby8_logic; >>> This works fine for one part of my design but doesn't for the other. >>> >> The "after 20ns" is ignored for synthesis. >> >> -- Mike Treseler >> > Why is it ignored? It seems that it works fine in the other design. > > Dan >Article: 121102
In article <1182803302.836888.54170@g4g2000hsf.googlegroups.com>,
EEngineer <maricic@gmail.com> writes:
|> > The "after 20ns" is ignored for synthesis.
|> >
|> > -- Mike Treseler
|>
|>
|> Why is it ignored? It seems that it works fine in the other design.
Just by accident... How would you do the 20ns in HW? Remember that gate delay is
only specified as a maximum value. Everything below depends on voltage,
temperature, chip binning and tide level, ie. you can't count on it.
The only way to get a reliable delay is running with a fast clock (>5-10times
your delay) and doing clocked delay stages. But you have to live with the jitter
if your signal is asynchronous to the clock.
--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 121103
EEngineer wrote:
>>> I did not use the ucf constraints file for the delay. Here is the
>>> actual line of code I am using:
>>> clock_rd <= clock after 20ns WHEN frame_done = '0' ELSE
>>> clock_dby8_logic;
>>> This works fine for one part of my design but doesn't for the other.
>> The "after 20ns" is ignored for synthesis.
> Why is it ignored?
Because synthesis can only delay
in increments of one clock period
using a counter or shifter process.
> It seems that it works fine in the other design.
It is working with an unconstrained delay,
so that is just good luck. So far.
-- Mike Treseler
Article: 121104On Jun 25, 5:12 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > EEngineer wrote: > >>> I did not use the ucf constraints file for the delay. Here is the > >>> actual line of code I am using: > >>> clock_rd <= clock after 20ns WHEN frame_done = '0' ELSE > >>> clock_dby8_logic; > >>> This works fine for one part of my design but doesn't for the other. > >> The "after 20ns" is ignored for synthesis. > > Why is it ignored? > > Because synthesis can only delay > in increments of one clock period > using a counter or shifter process. > > > It seems that it works fine in the other design. > > It is working with an unconstrained delay, > so that is just good luck. So far. > > -- Mike Treseler > "after 20ns" is ignored for sinthesys Now this explains why I had some designs work perfectly only in simulations but not on chip. I was just lucky that it worked in the other case. I am adding some more code so I can use 4 times faster clock and split it by 2 twice so I can get needed clock and 4 possible stages that will be used instead of "after 10ns" and "after 20ns". DanArticle: 121105
Hi, I am trying to generate a blif from verilog by using the command, quartus_map; however, there are some issues with RAM, so I can't get my blif. In the qsf_assignment_description.pdf, it has command for disabling DSP,set_global_assignment -name "DSP_BLOCK_BALANCING" "Logic Elements", but there is no command for disabling RAM. Does anyone know the command for it or any suggestion? Thanks, TiffanyArticle: 121106
Hi, hitsx@hit.edu.cn wrote: > I have post an topic serveral days ago, and there is the link. > http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/ee8cd744f6c3c10b?tvc=2# > > The total computation is described below: > integer add 2442 Giga operations > float add 814 Giga operations > float substract 2424 Giga operations > float muliply 1610 Giga operations > float divide 809 Giga operations > > And I need these operations done in 1 ~ 3 minutes, so what kind of > FPGA is needed? And > should I use multiple FPGAs to finish the computation? Regardless of the FPGA you choose, or the implementation of your main processing loop, don't even start until you've done a thorough IO / memory bandwidth analysis. Even in 2007 we're still seeing papers saying "we got 20X speed up in the core, then when we put it on the memory bus we got 1.5X". A wise person once said to me "interfaces before implementation" - and he was right. Unless your algorithm gets its input from /dev/zero and sends its output to /dev/null (in which case why bother?), the most difficult part of your design will be the interfaces, not the computational kernel. Exceptions might be the rare occasion that you have a huge amount of computational work to do on a small data set (crypto key cracking maybe?). Also, see if you can trade the floats for fixed-point integer. The software people won't like it because they want the same 30 insignificant digits to compare with the software version, but it's your job to convince them otherwise. Good luck, JohnArticle: 121107
On Jun 25, 10:01 pm, Sebastian Goller <s...@hrz.tu-chemnitz.de> wrote: > I'm currently developing a design for the XUP development board. The > development software is Xilinx EDk 8.2 > The system requires several frequencies. > > Power PC : 100 MHz > PLB : 50 MHz > > User IP : 50 MHz, 2.5 MHz > > The EDK uses DCM_0 to divide the 100 MHz by 2. I use 2 cascaded DCMs to > generate the 2.5 MHz (first divides by 2, second divides by 10). > But when I want to generate the bitstream the following messages and > errors occur: > > INFO:NgdBuild:889 - Pad net 'plb_bram_if_cntlr_1_port_BRAM_Clk' is not > connected > to an external port in this design. A new port > 'plb_bram_if_cntlr_1_port_BRAM_Clk' has been added and is connected > to this > signal. > INFO:NgdBuild:889 - Pad net > > 'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1' > is not connected to an external port in this design. A new port > > 'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1' > has been added and is connected to this signal. > > Applying constraints in "xup_morpheus5.ucf" to the design... > > Checking timing specifications ... > INFO:XdmHelpers:851 - TNM "sys_clk_pin", used in period specification > "TS_sys_clk_pin", was traced into DCM instance > "dcm_0/dcm_0/Using_Virtex.DCM_INST". The following new TNM groups > and period > specifications were generated at the DCM output(s): > CLK2X: TS_dcm_0_dcm_0_CLK2X_BUF=PERIOD dcm_0_dcm_0_CLK2X_BUF > TS_sys_clk_pin/2 > HIGH 50% > CLKDV: TS_dcm_0_dcm_0_CLKDV_BUF=PERIOD dcm_0_dcm_0_CLKDV_BUF > TS_sys_clk_pin*2 > HIGH 50% > INFO:XdmHelpers:851 - TNM "dcm_0_dcm_0_CLKDV_BUF", used in period > specification > "TS_dcm_0_dcm_0_CLKDV_BUF", was traced into DCM instance > > "board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/dcm_10mbit_I > /DCM_INST". The following new TNM groups and period specifications were > generated at the DCM output(s): > CLKDV: > TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I_ > CLKDV_BUF=PERIOD > board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I_CLK > DV_BUF TS_dcm_0_dcm_0_CLKDV_BUF*2 HIGH 50% > INFO:XdmHelpers:851 - TNM > > "board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I > _CLKDV_BUF", used in period specification > > "TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbi > t_I_CLKDV_BUF", was traced into DCM instance > > "board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/dcm_10mbit_2 > _I/DCM_INST". The following new TNM groups and period specifications > were > generated at the DCM output(s): > CLKDV: > TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_2_ > I_CLKDV_BUF=PERIOD > board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_2_I_C > LKDV_BUF > TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I_ > CLKDV_BUF*10 HIGH 50% > > ERROR:NgdBuild:455 - logical net 'plb_bram_if_cntlr_1_port_BRAM_Clk' has > multiple driver(s): > pin PAD on block > > plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_port_BR > AM_Clk with type PAD, > pin O on block dcm_0/dcm_0/Using_BUGF_for_CLKDV.CLKDV_BUFG_INST > with type > BUFG > ERROR:NgdBuild:924 - input pad net 'plb_bram_if_cntlr_1_port_BRAM_Clk' > is driving non-buffer primitives: > pin C on block reset_block/reset_block/core_cnt_en with type FD, > pin C on block reset_block/reset_block/Bus_Struct_Reset_0 with type FD, > pin C on block reset_block/reset_block/Rstc405resetchip with type FD, > pin C on block reset_block/reset_block/Peripheral_Reset_0 with type FD, > pin C on block reset_block/reset_block/Rstc405resetsys with type FD, > pin C on block reset_block/reset_block/Core_Reset_Req_d3 with type FD, > pin C on block reset_block/reset_block/CORE_RESET/q_int_0 with type FDRE, > pin C on block reset_block/reset_block/CORE_RESET/q_int_1 with type FDRE, > pin C on block reset_block/reset_block/CORE_RESET/q_int_2 with type FDRE, > pin C on block reset_block/reset_block/CORE_RESET/q_int_3 with type FDRE, > pin C on block reset_block/reset_block/SEQ/pr_dec_0 with type FDR, > pin C on block reset_block/reset_block/SEQ/pr_dec_1 with type FDR, > pin C on block reset_block/reset_block/SEQ/chip_dec_0 with type FDR, > pin C on block reset_block/reset_block/SEQ/chip_dec_2 with type FD, > pin C on block reset_block/reset_block/SEQ/pr_dec_2 with type FD, > pin C on block reset_block/reset_block/SEQ/chip_dec_1 with type FDR, > pin C on block reset_block/reset_block/SEQ/bsr_dec_0 with type FDR, > pin C on block reset_block/reset_block/SEQ/bsr_dec_2 with type FD, > pin C on block reset_block/reset_block/SEQ/seq_clr with type FDR, > pin C on block reset_block/reset_block/SEQ/ris_edge with type FDR > > ERROR:NgdBuild:455 - logical net > > 'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1' > has multiple driver(s): > pin O on block > > board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/dcm_10mbit_I/ > CLKDV_BUFG_INST with type BUFG, > pin PAD on block > board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1 > with type PAD > > ERROR:NgdBuild:924 - input pad net > > 'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1' > is driving non-buffer primitives: > pin O on block > > board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/dcm_10mbit_I/ > CLKDV_BUFG_INST with type BUFG > > Does anybody know this problem. I did not apply any changes to the > PLB_BRAM_IF_CNTL. Do I have to specify the new clock lines in one of the > EDK files? > > Thanks in advance > Sebastian Goller It seems that you have connected more than one nets to the same output or inout port.Article: 121108
On 6 26 , 8 05 , John Williams <jwilli...@itee.uq.edu.au> wrote:
> Hi,
>
> h...@hit.edu.cn wrote:
> > I have post an topic serveral days ago, and there is the link.
> >http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/ee...
>
> > The total computation is described below:
> > integer add 2442 Giga operations
> > float add 814 Giga operations
> > float substract 2424 Giga operations
> > float muliply 1610 Giga operations
> > float divide 809 Giga operations
>
> > And I need these operations done in 1 ~ 3 minutes, so what kind of
> > FPGA is needed? And
> > should I use multiple FPGAs to finish the computation?
>
> Regardless of the FPGA you choose, or the implementation of your main
> processing loop, don't even start until you've done a thorough IO /
> memory bandwidth analysis. Even in 2007 we're still seeing papers
> saying "we got 20X speed up in the core, then when we put it on the
> memory bus we got 1.5X".
>
> A wise person once said to me "interfaces before implementation" - and
> he was right. Unless your algorithm gets its input from /dev/zero and
> sends its output to /dev/null (in which case why bother?), the most
> difficult part of your design will be the interfaces, not the
> computational kernel.
>
> Exceptions might be the rare occasion that you have a huge amount of
> computational work to do on a small data set (crypto key cracking maybe?).
>
> Also, see if you can trade the floats for fixed-point integer. The
> software people won't like it because they want the same 30
> insignificant digits to compare with the software version, but it's your
> job to convince them otherwise.
>
> Good luck,
>
> John
Memory bandwidth is quite a substantial problem.
In my algorithm, mostly of the computation is something like this:
double a,b,c,d;
int i,j,m;
for (i=1;i<ii;i++)
for (j=1;j<jj;j++)
for (k=1;k<kk;k++)
c = (a * b + c) / d;
And ii, jj ,kk is quite large.
The problem is how to put the algorithm into parallel computation, and
the memory bus would not be an issue.
Article: 121109As I know among the three outputs of pll(c0, c1, c2) only c2 can drive the dedicated PLL<#>_OUT pin, but when in a design, when I assign the PLL1_OUTP to c1, it can aslo works. Anyone know the reason? Thank you! LeonArticle: 121110
Hi Iam a newbie in linux. How to findout on an arm board that it has a debug port to use KGDB. I have an XSCALE(IQ80310) based board and want to use KGDB to debug my kernel module. I would like to know how to conclude that a development board has debugging supporting hardware. Thanks in advance.... Regards Imtiaz AhmedArticle: 121111
commone wrote: > As I know among the three outputs of pll(c0, c1, c2) only c2 can drive the > dedicated PLL<#>_OUT pin, but when in a design, when I assign the PLL1_OUTP > to c1, it can aslo works. Anyone know the reason? My _guess_ would be that driving 'PLL_OUTP' with C1 is essentially driving a regular IO pin from the global clock network. Hence you lose the ability to automatically compensate for the skew on the output wrt to the input. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 121112
Mark McDougall wrote: > My _guess_ would be that driving 'PLL_OUTP' with C1 is essentially driving > a regular IO pin from the global clock network. Hence you lose the ability > to automatically compensate for the skew on the output wrt to the input. And table 7-5 on page 7-9 of the Cyclone II handbook would tend to support this... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 121113
Hi, I need a VGA 1080x1920 chip supporting HDTV. Anyone here has used before such IC ? thank you, VasileArticle: 121114
Hi everyone. I have selected spartan 3E family for an FFT project due to its low cost. The FFT core (v 4.0) specs say that for spartan3E devices, the footprint is as follows (see table) and they "recommend" the device in the table. FFT =EF=BB=BFLength Slices Block RAMs 18x18 Mults Device ----------------------------------------------------------------------------------------------------------- 256 485 2 2 xc3s500e 1024 517 3 2 xc3s1200e 8192 578 18 2 xc3s1600e ------------------------------------------------------------------------------------------------------------ However, based on device datasheets, the devices recommended are way overkill. For example, lets take FFT length of 8192. We need 578 slices, 18 BRAM, 2 mults. Lets look at the family Spartan 3E: Device System Gates Slices BRAM 18x18mult ------------------------------------------------------------------------------ XC3S100E 100K 960 72kbit 4 ------------------------------------------------------------------------------ So according to this table, even the smallest device in the family will be able to fit the FFT 8192 design. Based on my experience, that's not going to happen, but the tables say it will. Can anyone explain why xilinx recommends a 1.6Mgate device for the FFT of 8192 points, whereas according to slices utilized it should fit into a 100kgate device? Thank you, Best regards, TelenochekArticle: 121115
hi, guys We design a hardware written in Verilog and synthesize by Synopsys Design Vision. The post-synthesis simulation is shown that the function of hardware is correct. Now, we are going to verify function of hardware by downloading it to Xilinx FPGA. We synthsize the hardware design by using ISE 7.1i. Unfortunately, the post-synthesis simulation failed ( all the output is unknown or high- impeadance). I tried to synthesize with keeping hierarchy, but it still unuseful. What can I do next step? We don't have much experience in this field. Thanks. RegardsArticle: 121116
Hi Telenochek,
acording to the numbers you gave the advice from Xilinx was correct.
In your case it's not the number of LUTs that defines the border, but
the BRAMS.
You need 18 BRAMs, each has a size of 18KBit in S3E devices.
Datasheet Page 4 says:
• Block RAM provides data storage in the form of
18-Kbit dual-port blocks.
so 18 x 18 x 1024 = 331776 Bits
and so the closest fitting device is the S3E500 with 360 KBits.
And that's what is said in the 4.1 Datasheet table 28 and 30.
In table 24 and 26 you find the s3E1600 Device, but the cores listed in
there need more BRAMS, and Multiplyers, so they don't fit in the S3E500
anymore. also, there are max Clock frequencies given in these tables.
Maybe these can't be acheived with the smaller devices due to mapping or
routing problems.
But anyway, if you are still unsure about the device you should choose
just make a test-synthesis and implementation. If there's something
wrong with the size of the chosen device you will know instantly, after
the error messages and warnings are printed out. Takes just a few minutes.
Have a nice synthesis
Eilert
Telenochek schrieb:
> Hi everyone.
>
> I have selected spartan 3E family for an FFT project due to its low
> cost.
> The FFT core (v 4.0) specs say that for spartan3E devices, the
> footprint is as follows (see table)
> and they "recommend" the device in the table.
>
> FFT Length Slices Block RAMs 18x18 Mults Device
> -----------------------------------------------------------------------------------------------------------
> 256 485 2 2
> xc3s500e
> 1024 517 3 2
> xc3s1200e
> 8192 578 18 2
> xc3s1600e
> ------------------------------------------------------------------------------------------------------------
>
> However, based on device datasheets, the devices recommended are way
> overkill.
> For example, lets take FFT length of 8192.
>
> We need 578 slices, 18 BRAM, 2 mults.
> Lets look at the family Spartan 3E:
>
> Device System Gates Slices BRAM 18x18mult
> ------------------------------------------------------------------------------
> XC3S100E 100K 960 72kbit 4
> ------------------------------------------------------------------------------
>
> So according to this table, even the smallest device in the family
> will be able to fit the FFT 8192 design.
> Based on my experience, that's not going to happen, but the tables say
> it will.
>
> Can anyone explain why xilinx recommends a 1.6Mgate device for the FFT
> of 8192 points,
> whereas according to slices utilized it should fit into a 100kgate
> device?
>
> Thank you,
> Best regards,
> Telenochek
>
Article: 121117Hello, Im in embedded software development, but interested in developing a device which can caputure trace information from a Nexus class-3 compliant processor. Possibly later changed to capture trace from any processor. The trace has to be modfied to be used by data-acquisition application running on a PC (interfaces: USB/Ethernet/Firewire) I figured out that using an FPGA would be ideal for such a application. But which one ? Any recommendations ? Which processor core to use (Hard/Soft Core -- cost ??) , IP's for I/O and Nexus. etc Is anyone working on such a concept/project ? Pointers and hints and welcome! Kind Regards, RavishankarArticle: 121118
Perry wrote:
> On Jun 25, 10:01 pm, Sebastian Goller <s...@hrz.tu-chemnitz.de> wrote:
>
>>I'm currently developing a design for the XUP development board. The
>>development software is Xilinx EDk 8.2
>>The system requires several frequencies.
>>
>>Power PC : 100 MHz
>>PLB : 50 MHz
>>
>>User IP : 50 MHz, 2.5 MHz
>>
>>The EDK uses DCM_0 to divide the 100 MHz by 2. I use 2 cascaded DCMs to
>>generate the 2.5 MHz (first divides by 2, second divides by 10).
>>But when I want to generate the bitstream the following messages and
>>errors occur:
>>
>>INFO:NgdBuild:889 - Pad net 'plb_bram_if_cntlr_1_port_BRAM_Clk' is not
>>connected
>> to an external port in this design. A new port
>> 'plb_bram_if_cntlr_1_port_BRAM_Clk' has been added and is connected
>>to this
>> signal.
>>INFO:NgdBuild:889 - Pad net
>>
>>'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1'
>> is not connected to an external port in this design. A new port
>>
>>'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1'
>> has been added and is connected to this signal.
>>
>>Applying constraints in "xup_morpheus5.ucf" to the design...
>>
>>Checking timing specifications ...
>>INFO:XdmHelpers:851 - TNM "sys_clk_pin", used in period specification
>> "TS_sys_clk_pin", was traced into DCM instance
>> "dcm_0/dcm_0/Using_Virtex.DCM_INST". The following new TNM groups
>>and period
>> specifications were generated at the DCM output(s):
>> CLK2X: TS_dcm_0_dcm_0_CLK2X_BUF=PERIOD dcm_0_dcm_0_CLK2X_BUF
>>TS_sys_clk_pin/2
>>HIGH 50%
>> CLKDV: TS_dcm_0_dcm_0_CLKDV_BUF=PERIOD dcm_0_dcm_0_CLKDV_BUF
>>TS_sys_clk_pin*2
>>HIGH 50%
>>INFO:XdmHelpers:851 - TNM "dcm_0_dcm_0_CLKDV_BUF", used in period
>>specification
>> "TS_dcm_0_dcm_0_CLKDV_BUF", was traced into DCM instance
>>
>>"board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/dcm_10mbit_I
>> /DCM_INST". The following new TNM groups and period specifications were
>> generated at the DCM output(s):
>> CLKDV:
>>TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I_
>>CLKDV_BUF=PERIOD
>>board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I_CLK
>>DV_BUF TS_dcm_0_dcm_0_CLKDV_BUF*2 HIGH 50%
>>INFO:XdmHelpers:851 - TNM
>>
>>"board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I
>> _CLKDV_BUF", used in period specification
>>
>>"TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbi
>> t_I_CLKDV_BUF", was traced into DCM instance
>>
>>"board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/dcm_10mbit_2
>> _I/DCM_INST". The following new TNM groups and period specifications
>>were
>> generated at the DCM output(s):
>> CLKDV:
>>TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_2_
>>I_CLKDV_BUF=PERIOD
>>board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_2_I_C
>>LKDV_BUF
>>TS_board1_unit_0_board1_unit_0_USER_LOGIC_I_eth_mac_if_3_1_CLK_DIV_dcm_10mbit_I_
>>CLKDV_BUF*10 HIGH 50%
>>
>>ERROR:NgdBuild:455 - logical net 'plb_bram_if_cntlr_1_port_BRAM_Clk' has
>> multiple driver(s):
>> pin PAD on block
>>
>>plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_port_BR
>> AM_Clk with type PAD,
>> pin O on block dcm_0/dcm_0/Using_BUGF_for_CLKDV.CLKDV_BUFG_INST
>>with type
>> BUFG
>>ERROR:NgdBuild:924 - input pad net 'plb_bram_if_cntlr_1_port_BRAM_Clk'
>>is driving non-buffer primitives:
>> pin C on block reset_block/reset_block/core_cnt_en with type FD,
>> pin C on block reset_block/reset_block/Bus_Struct_Reset_0 with type FD,
>> pin C on block reset_block/reset_block/Rstc405resetchip with type FD,
>> pin C on block reset_block/reset_block/Peripheral_Reset_0 with type FD,
>> pin C on block reset_block/reset_block/Rstc405resetsys with type FD,
>> pin C on block reset_block/reset_block/Core_Reset_Req_d3 with type FD,
>> pin C on block reset_block/reset_block/CORE_RESET/q_int_0 with type FDRE,
>> pin C on block reset_block/reset_block/CORE_RESET/q_int_1 with type FDRE,
>> pin C on block reset_block/reset_block/CORE_RESET/q_int_2 with type FDRE,
>> pin C on block reset_block/reset_block/CORE_RESET/q_int_3 with type FDRE,
>> pin C on block reset_block/reset_block/SEQ/pr_dec_0 with type FDR,
>> pin C on block reset_block/reset_block/SEQ/pr_dec_1 with type FDR,
>> pin C on block reset_block/reset_block/SEQ/chip_dec_0 with type FDR,
>> pin C on block reset_block/reset_block/SEQ/chip_dec_2 with type FD,
>> pin C on block reset_block/reset_block/SEQ/pr_dec_2 with type FD,
>> pin C on block reset_block/reset_block/SEQ/chip_dec_1 with type FDR,
>> pin C on block reset_block/reset_block/SEQ/bsr_dec_0 with type FDR,
>> pin C on block reset_block/reset_block/SEQ/bsr_dec_2 with type FD,
>> pin C on block reset_block/reset_block/SEQ/seq_clr with type FDR,
>> pin C on block reset_block/reset_block/SEQ/ris_edge with type FDR
>>
>>ERROR:NgdBuild:455 - logical net
>>
>>'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1'
>> has multiple driver(s):
>> pin O on block
>>
>>board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/dcm_10mbit_I/
>> CLKDV_BUFG_INST with type BUFG,
>> pin PAD on block
>>board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1
>> with type PAD
>>
>>ERROR:NgdBuild:924 - input pad net
>>
>>'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1'
>> is driving non-buffer primitives:
>> pin O on block
>>
>>board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/dcm_10mbit_I/
>> CLKDV_BUFG_INST with type BUFG
>>
>>Does anybody know this problem. I did not apply any changes to the
>>PLB_BRAM_IF_CNTL. Do I have to specify the new clock lines in one of the
>>EDK files?
>>
>>Thanks in advance
>>Sebastian Goller
>
>
> It seems that you have connected more than one nets to the same output
> or inout port.
>
I already checked the source code and the edif netlist
(design_analyzer). Everything is okay. The point that confuses me the
most is, that the error regarding plb_bram_if_cntlr_1_port_BRAM_Clk
occurs when I use the DCM_0 in the EDK. If I use the same frequency for
the PowerPC and the PLB there is no problem at all.
Same thing with the two cascaded DCMs in the user IP. No signal has more
than one driver.
The simulation of the behavioral model and the structural model works fine.
Is there anything I have to add to the .mhs or the .mpd or to another file?
I have already tried to modify the .ucf-file. I added the following lines
Net "sys_clk_s" TNM_NET = "sys_clk_s";
TIMESPEC "TS_sys_clk_s" = PERIOD "sys_clk_s" "TS_sys_clk_pin"/2;
Net "board1_unit0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1"
TNM_NET = "clkdv_dcm1";
TIMESPEC "TS_clkdv_dcm1" = PERIOD "clkdv_dcm1" "TS_sys_clk_s"/2;
After restarting NGDBUILD the following error occurs:
INFO:NgdBuild:889 - Pad net 'plb_bram_if_cntlr_1_port_BRAM_Clk' is not
connected
to an external port in this design. A new port
'plb_bram_if_cntlr_1_port_BRAM_Clk' has been added and is connected
to this
signal.
INFO:NgdBuild:889 - Pad net
'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1'
is not connected to an external port in this design. A new port
'board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1'
has been added and is connected to this signal.
Applying constraints in "xup_morpheus5.ucf" to the design...
INFO:NgdBuild:757 - Line 14 in 'xup_morpheus5.ucf': The constraint for NET
'sys_clk_s' is being attached to the equivalent NET
'plb_bram_if_cntlr_1_port_BRAM_Clk'.
ERROR:NgdBuild:756 - Line 16 in 'xup_morpheus5.ucf': Could not find net(s)
'board1_unit0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1' in the
design.
To suppress this error specify the correct net name or remove the
constraint.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file
"xup_morpheus5.ucf".
What I do not understand is that NGDBUILD gives me an information about
the signal
"board1_unit_0/board1_unit_0/USER_LOGIC_I/eth_mac_if_3_1/CLK_DIV/clkdv_dcm1"
and five seconds later the signal can not be found in the design.
Article: 121119Hello Amontec, Larry, Spefically for you, since I did not get any reposone from the Amontec site! Could you explain the features of the chameleon. How does it work ? Can it be configured to work with any debug connection. Specifically I want to debug a MPC8241 (COP connector) and possibly a TriCore controller. How will the chameleon help here.. It has DB-25 parallel ports on both sides (I - O ) , how is the debug-port (like COP) to be connected ? Kind Regards, RavishankarArticle: 121120
wht means speedgrade in xilinx fpgas? what rold speed grade plays in the design and selection of fpga for a design? If the speedgrade determines the delay etc..on wht basics they determine that. Plz mail the answers to vkmselva@gmail.com Regards, selva kumar.RArticle: 121121
"freeplatypus" <freeplatypus@gmail.com> wrote in message news:1182336040.301743.137350@n2g2000hse.googlegroups.com... > Well first of all: > 1. I am engaged in (high level) software development since this is the > way I can make a living during studies. Sometimes this is the only > choice (better then weekend work at supermarket). > 2. I enjoy programming logic, making tests for them and creating > firmware because I can see my result in physical implementation (at > the end, there is usually a device that does something) > 3. I would love to broader my knowledge, but sometime lack ideas, > because I live and work in limited environment That sounds a bit like me :-) Here's my story: I'm from Denmark. I got a degree including PhD in EE ten years ago, with the plan to do research in physics. However, at the time no job offers were available, so I started in the software development field. This, despite the complete lack of any credited skill in that area; I had basically only programmed some numerical simulations. But the job situation was good at the time, and they basically hired anything that could stand on two legs! I've survived the big bubble (crash of the IT market ca. five years ago), including the close-down of the branch I worked for. Almost 400 IT professionals managed to find new jobs within at most half a year. I've changed jobs since then, my recent job started four years ago. About two years ago I got tired of doing SW development, and I was very lucky to be able to relocate to FPGA programming within my present employment. I'm loving it every minute, and I feel very lucky to have gotten this opportunity, because I had absolutely no experience before. However, ten years ago I would never have dreamt I would be doing this kind of work. To summarize: 1) Your carreer may not necessarily develop linearly. Mine certainly has not. 2) In Denmark all the companies are screaming for IT professionals. We have a shortage of highly skilled professionals, and it's getting worse. Since you are in Europe, you should consider moving here. The weather really is not that bad :-) -Michael.Article: 121122
"freeplatypus" <freeplatypus@gmail.com> wrote in message news:1182336040.301743.137350@n2g2000hse.googlegroups.com... > That's why I am asking. How does it look in Europe? Maybe I am looking > at wrong message boards look for a job? Almost no internships offered. > Almost no entry level jobs ( or even better, job offer for entry > engineer but with multiple years of experience - I guess that salary > is for entry). Oh, and one more thing. Only about 1/4 of all jobs are advertised on message boards, bulletins, etc. These methods are only used, if the company looking to hire, cannot find a reasonable candidate any other way. It is a kind of "last resort" for most companies. Instead, they rely on word of mouth, a.k.a. networking. This is where you should focus your energy. Get to know other professionals in your field. Where are they working? What's it like working there? Are there any job openings coming up? Do they know of other companies looking to expand? Use all your friends, present colleagues, former colleagues, family, etc. Let all of them know what you are looking for. -Michael.Article: 121123
John Adair wrote: > > Finally first picture of Darnaw1 our PGA style FPGA board is here here > http://www.enterpoint.co.uk/moelbryn/darnaw1.html. More information on > pricing and spec in the next couple of days will appear on the > website. Those with eagle eyes can work it out the spec from the > picture. > > First shipments will have 16Mbit SPI flash to allow programming of the > FPGA but also to act as a code store for processors like MicroBlaze > implemented within the FPGA. There is also SDRAM on board. Small > numbers of this product will be available to ship next week. > > We would be interested to have feedback on this product and what you > like, and what we could improve on this product and the related series > of products we have planned. Just got the boards together with a parallel port download cable. Is there any special download software or does this cable work with Xilinx software? Is there some ready to run demo for the Darnaw1 board available (just some output to the LED'S maybe). Didn't find anything on your Website.Article: 121124
hitsx@hit.edu.cn <hitsx@hit.edu.cn> wrote: ... > for (i=1;i<ii;i++) > for (j=1;j<jj;j++) > for (k=1;k<kk;k++) > c = (a * b + c) / d; Did you try to write equation containig the indexes? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z