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Messages from 7875

Article: 7875
Subject: Re: Parallel-Serial Convertors for XC6200
From: "Alan P. Burke" <aburke@ibm.net>
Date: Sun, 26 Oct 1997 13:05:55 -0500
Links: << >>  << T >>  << A >>
Look for the "VELAB" beta release at Xilinx; try http://www.xilinx.com.
It contains a number of parameterized VHDL entities, including SERPAR
and PARSER, which do the kind of conversion you need, for the XC6200.

Alan

Reetinder P. S. Sidhu wrote:

> I'm doing bit-serial computation using the XC6216 FPGA and require
> parallel to serial and serial to parallel convertors. I would
> appreciate any info on how to implement them on FPGAs
> (esp. XC6200). Thanks in advance.
>
>                                                 Reetinder Sidhu




Article: 7876
Subject: example dct
From: ydoganc@elektron.et.tudelft.nl (y.doganc)
Date: 26 Oct 1997 18:16:48 GMT
Links: << >>  << T >>  << A >>
where can i find a design example (vhdl) for DCT
(discrete cosinus transform).
where can i find library  or how can i get it 
<ieee.std_logic_unsigned.all>.

Article: 7877
Subject: design sites
From: "Thielemans - Van Heghe" <robbren@skynet.be>
Date: 26 Oct 1997 19:28:50 GMT
Links: << >>  << T >>  << A >>
Hello everyone,

I would be very pleased if someone could send me interesting links to FPGA
design sites, information besides the vendors of course. Thanks in advance,

Robbie
Article: 7878
Subject: Re: FLEX8000 configuration
From: "Ido Kleinman" <kleinn@erez.cc.biu.ac.il>
Date: Sun, 26 Oct 1997 23:15:10 +0200
Links: << >>  << T >>  << A >>
Hi,

About the delay - I'll take it into account.
My problem was not the power supply - I tied the RD/WR signals from the CPU
to the Flex8000 device - and although those pins were supposed to be
tri-stated in the configuration process they were actully pulled to ground
so that crashed my CPU cause it couldn't read the RAM/ROM data as it should.

About CS/nCS - I tried CS to VCC and nCS is coming from my 386EX chip-select
unit.
About RDYnBUSY -- I am developing an embedded PCI card, not ISA. Even though
I thought about making the RDYnBUSY a waitstate generator with a little glue
logic and my 386EX READY# pin - I decided against it because the software is
a simpler solution.
About TTF - I included it as a array of bytes. What did you do with the RBF?
Are you reading from some mass-storage device? I only have Flashes.


--
--==  Ido Kleinman  ==--
kleinn@erez.cc.biu.ac.il

Ilija Hadzic wrote in message <62j2dr$42$1@netnews.upenn.edu>...
>Ido Kleinman (kleinn@erez.cc.biu.ac.il) wrote:
>: 1. I create a high-low-high transition in the nCONFIG line
>: 2. wait for nSTATUS to go high
>
>Make sure that the nCONFIG pulse is long enough (ca. 2 microseconds).
>Also before you start writing put some delay. Altera says that the delay
>should be about 5 microseconds and I have seen nSTATUS go up earlier
>(BTW, in my design I don't even test it, I just wait after the nCONFIG
>pulse and it works for me).
>
>: 3. I poll the RDYnBUSY line for ready state (high)
>: 4. I do a I/O write cycle to the FLEX address and write the next byte
from
>: the array.
>: 5. I check if nSTATUS gone low  = frame error.
>: 6. repeat steps 2-5 for the exact number of bytes needed to be loaded
>: (sizeof (arraybytes))
>: 7. wait for conf_done.
>
>This scheme works fine for me. BTW, what do you do with CS and nCS
>signals. I keep them high and low respecitvely (i.e. active) during the
>entire configuration.
>
>Also instead of polling RDYnBSY signal in software, you can use it to drive
>the IOCHRDY signal on the ISA bus and let the bus controller add wait
>states as necessary.
>
>Also make sure that you are reading the file properly. I prefer using RBF
>instead of TTF and read it as the binary file.
>
>Ilija


Article: 7879
Subject: Re: Xilinx Adder Trees in Viewlogic
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Sun, 26 Oct 1997 19:02:59 -0500
Links: << >>  << T >>  << A >>
feydo wrote:
> 
> Hi All,
>    I having a problem get Workview Office to do what I want.  I' m trying
> to make an adder tree which will add together five 16-bit numbers.  I' ve
> used Xilinx's Core Generator program to make the adders.  The first adder
> adds A[15:0] and B[15:0] resulting in S1[16:0].  The second adder adds
> C[15:0] and D[15:0] resulting in S2[16:0].  The third adder adds S1[16:0]
> and S2[16:0] resulting in S3[17:0].  Now comes the problem  ...  I want to
> add S3[17:0] and E[15:0].  The adder generated by CoreGen expects two 18
> bit inputs, but the one input is only 16 bits wide.  Obviously the upper
> two bits should be zero to make it 18 bits wide.  Does anyone know how to
> make WVOffice do this?  I have tried simply connecting the 16 wide bus E to
> the 18 wide input, but WVO lines up the 16 wide bus to the upper 16 bits of
> the 18 wide input, leaving the lower two bits zero (or unconnected?).  Any
> suggestions will be greatly appreciated.
> 
> Thanks,
> mark

You need to make the bus have more than one segment.  The bus segment
that attaches to the 16 bit adder output must have a label on it that
matches the width of the adder output (in your case bus[15:0]).  The
segment that connects to the next adder's input must also be labelled
with an appropriate label (in this case bus[17:0]).  The two extra bits
need to be driven by something that explicitly calls out the bits.  This
can either be a macro with a bus output or individual signals tied to
the bus.  Either case must have appropriate labels.  You may need to
sign extend to make your adder tree work right, in which case the extra
bits come from a sign extension macro consisting of a one bit input
driving an individual BUF for each bit you wish to sign extend.  In your
case you'd have a macro with two BUFs inside.  The inputs would be a
single signal (call it A internally) and a bus output with two outputs,
Y0 and Y1.  The input to the macro gets connected to the bus from the
adder and must be labelled bus15.  THe output gets a bus connection to
the same bus between the adders and the segment connecting this macro
gets labelled bus[17:16].

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka
Article: 7880
Subject: Re: XILINX pin compatible replacements
From: APS <APS@associatedpro.com>
Date: Sun, 26 Oct 1997 21:11:35 -0500
Links: << >>  << T >>  << A >>
ATMEL's new 40K family are pin for pin compatible with XILINX FPGAs.
They currently have the 40K20 chip available but will soon have others
available. They are
also working on getting some very reasonably priced tools out for these.

Their 6K family of FPGAs never quite caught on, but the potential for
the these new FPGAs is high. With the XILINX pin compatibility coupled
with the architecture features such as:

* diagonal routing lines
* a less course CLB structure where all flip flops can be accessed
without using LUT resources
* Internally distributed RAM with the RAM not using LUT resources.
* Claims of a faster Multiplier structure (i haven't quite figured this
out yet)
* LOWER COST SILICON

We are contemplating doing some low cost ATMEL kits including tech notes

and development boards. ATMEL has kindly dropped off a copy of the
software, and I will probably be using EXEMPLAR as the synthesis front
end for now. I have heard rumors to the effect that there will be some
low cost front end VHDL tools offered with the router at very reasonable

prices. Stay tuned to our website and our newsletter for future
developments along these lines.

http://www.associatedpro.com/aps


--Wade D. Peterson wrote:

> Does anybody know if anybody makes pin compatible replacement parts
> for XILINX XC4005, XC4006 or XC4008 devices?
>
> Thanks a bunch.
>
> Wade
>
> -----------------------------------------------------
> Wade D. Peterson         | TEL: 612.722.3815
> Consultant to Industry   | FAX: 612.722.5841
> 3525 E. 27th St. No. 301 |---------- EMAIL ----------
> Minneapolis, MN  55406   | peter299@maroon.tc.umn.edu
> ---------------- Committed to Quality ---------------



--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 7881
Subject: All Digital DLL or PLL with less than 20ps resolution
From: Ammann Michael <mammann@stud.ee.ethz.ch>
Date: Mon, 27 Oct 1997 09:09:33 +0100
Links: << >>  << T >>  << A >>
Does anybody have a good idea, how to design an All Digital DLL or
PLL on a 0.8 CMOS Process. The PLL or DLL should have a hold range
from 30kHz to 50kHz, and veri low jitter (less than 20ps !).
If you have some good ideas or you know a goog site concerning this
problem. 

Send me a mail please

------------------------------------------------------------------
Michael Ammann                                    +41 41 741 17 91
Keltenweg 20                  http://www.stud.ee.ethz.ch/~mammann/
CH-6312 Steinhausen                        mammann@stud.ee.ethz.ch
------------------------------------------------------------------

Article: 7882
Subject: Re: Xilinx 4000 on an ISA bus...
From: Charles Sweeney <CharlesSweeney@compuserve.com>
Date: Mon, 27 Oct 1997 10:23:39 +0000
Links: << >>  << T >>  << A >>
Jacob W Janovetz wrote:
> 
> Hello...
> 
>    I have a 'should it be done' question.  We have a PC/104 embedded
> system (ISA bus) and want to put a Xilinx part on a board with
> the PC/104 connector.  I'm wondering if it is ok to place the
> FPGA directly on the bus (ie without the traditional 74245
> bidirectional buffers).  When the Xilinx is programming or is
> unprogrammed, the pins are in a weak pullup state which should be
> ok for the ISA bus.
> 
>    I've tried this in a prototype situation and everything is
> working fine.  I can reprogram the Xilinx in-circuit and it doesn't
> screw up the PC/104 system.  I'm just wondering if this is a
> common practice and if it will be reliable between PC/104 systems
> and such.
> 
>    As an unrelated question, during an I/O write, data is latched
> (by the FPGA) on the rising edge of IOW*.  Does this mean a signal
> like this (IOW*) should be on a clock pin of the FPGA to allow a
> BUFG to be attached to it?
> 
>     Cheers,
>     Jake
> 
> --
>    janovetz@uiuc.edu    | Once you have flown, you will walk the earth with
>  University of Illinois | your eyes turned skyward, for there you have been,
>                         | there you long to return.     -- da Vinci
>         PP-ASEL         | http://www.cen.uiuc.edu/~janovetz/index.html

Shouldn't cause any problems in the unprogrammed or programming states,
the 4k's are used as PCI controllers so should be fine as ISA
controllers.

Ideally you should use a clock pin and a BUFG to avoid skew problems in
the xilinx.

In our RC1000-II ISA board I used a registered transceiver in the data
path between ISA and the 4010. The 4010 is programmed using our C-based
programming language Handel-C and the whole fpga is clocked by a single
clock which is asynchronous to the ISA bus clock. So the registered
transceiver decouples the ISA bus from the program running in the 4010
so there are no synchronization problems. We can licence the RC1000-II
design if you're interested.

Please take a look at our web site for info on the RC1000-II and
Handel-C.

Charles

Charles Sweeney, Engineering Director, Embedded Solutions Ltd
Tel/fax +44 1235 510456   <http://www.embedded-solutions.ltd.uk/>
Email CharlesSweeney@compuserve.com or
csweeney@embedded-solutions.ltd.uk
6 Main Road, East Hagbourne, Didcot, Oxfordshire. OX11 9LJ. UK.
Article: 7883
Subject: Configuring ALTERA in JTAG-chains
From: Erwin Ruoff <erwin.ruoff@phys.uni-karlsruhe.de>
Date: Mon, 27 Oct 1997 11:35:17 +0100
Links: << >>  << T >>  << A >>
Hey,

because ALTERA isn't interested in our problem I try to find help here.

We are trying to configure the following three ALTERA-device-chains via Bitblaster & MAX+plusII 
7.2:

	1) 10k20 -> 740 -> 10k10
	2) 10k10 -> 10k20 -> 740

While configuring we remarked the following:

- The I/O Pins are driven low and high for a short time
- We tried to configure different combination with different success as you can see in the table 
below. This means that configuration is successfull but the devices are not initialized.

+ means: with programming file or conf. successful and initialization
- means: no file or configuration successful but no intialization

10k20	740	10k10	initialization
-	+	-	+
-	-	+	-
+	-	-	+
+	+	-	+
-	+	+	-
+	-	+	-
+	+	+	-

10k10	10k20	740	initialization
-	-	+	+
-	+	-	-
-	+	+	+
+	-	-	+
+	-	+	+
+	+	-	+
+	+	+	+

In this chain we have also following phenomena:

When configuring:

- + - it isn't working. When directly after that configuring + - + then all
three devices are initialized correctly.


We connected the pins as recommended in ALTERA specification for configuring 10k devices.

Has anyone an idea how to solve the problem?

Erwin

*******************************************************
   Erwin Ruoff                                                      
   Institut fuer Experimentelle Kernphysik  
   University of Karlsruhe
   Postfach 3640
   76021 Karlsruhe
   Germany
   Phone: +49 7247 82 4254
   FAX:   +49 7247 82 3414
   mailto:Erwin.Ruoff@phys.uni-karlsruhe.de
******************************************************
Article: 7884
Subject: Re: design sites
From: edndipert@postoffice.worldnet.att.net (Brian Dipert)
Date: Mon, 27 Oct 1997 14:51:57 GMT
Links: << >>  << T >>  << A >>
>Hello everyone,
>
>I would be very pleased if someone could send me interesting links to FPGA
>design sites, information besides the vendors of course. Thanks in advance,

Two places to stard:
1) My 'work links' page at http://members.aol/com/bdipert/wrklinks.htm
2) Steven Knapp's Programmable Logic Jump Station site (which is
excellent) at http://www.optimagic.com/

Regards,
Brian Dipert
Technical Editor
EDN Magazine: The Design Magazine Of The Electronics Industry
1864 52nd Street
Sacramento, CA   95819
(916) 454-5242
(916) 454-5101 (fax)
edndipert@worldnet.att.net
Visit me at <http://members.aol.com/bdipert>
Article: 7885
Subject: Internal tri-state emulation.
From: Roger Yau <rogeryau@net.polyu.edu.hk>
Date: Mon, 27 Oct 1997 22:52:43 +0800
Links: << >>  << T >>  << A >>
Hello,

I wanted to translate my old design ( XC5202 ) to Altera Flex8282A.
When I completed and compile it, it can't fit into Flex8282ATC100.
Later, I find that the "Internal tri-state emulation" of the Altera
use up many resource (over 40 LE's). Is there any function(s) of the
compiler to solve this problem ? Xilinx's internal tri-state do not
consume any logic cell!

Roger Yau
Easson Precision Ltd.
Article: 7886
Subject: Re: Anyone know of an I2C Controller design for an FPGA?
From: mike@unconfigured.xvnews.domain (Mike Walsh)
Date: 27 Oct 1997 16:21:08 GMT
Links: << >>  << T >>  << A >>
In article <01bce150$55136920$3f15440c@lincoln-labs>, "John McGibbon" <john_mcgibbon@memecdesign.com.stop.spams.please> writes:
>Memec Design Services has a module for Xilinx FPGA's. It has been used and
>is available. I'm not sure of cost and features but a datasheet is
>available on their website:
>
>http://www.memecdesign.com/xf-twsi.htm
>
>Austin Franklin <darkroo4m@ix.netcom.com> wrote in article 
>> Is there anyone who has done an I2C controller in an FPGA?
>> 
>
>
>


Mentor Graphics offers an I2C core as well.  You can view the
datasheet at:  http://www.mentorg.com/inventra/softcore/catalog/mi2c_pf.pdf


-- 
...Mike

No Guts, No Glory.

+--------------------------------------------------------------+
| Michael P. Walsh                     mike@rtp-nc.mentorg.com |
|                                       mike_walsh@mentorg.com |
| Technical Account Manager - Ericsson                         |
| Mentor Graphics Corporation                 V:(919) 484-2505 |
| 2525 Meridian Parkway, Suite 260            F:(919) 544-0701 |
| Research Triangle Park, North Carolina 27713                 |
+--------------------------------------------------------------+


Article: 7887
Subject: Re: All Digital DLL or PLL with less than 20ps resolution
From: mjohnson@netcom4.netcom.com (Mark Johnson)
Date: Mon, 27 Oct 1997 17:02:56 GMT
Links: << >>  << T >>  << A >>
In article <34544C3D.6771@stud.ee.ethz.ch> Ammann Michael <mammann@stud.ee.ethz.ch> writes:
  >
  > Does anybody have a good idea, how to design an All
  > Digital DLL or PLL on a 0.8 CMOS Process. The PLL or
  > DLL should have a hold range from 30kHz to 50kHz,
  > and veri low jitter (less than 20ps !).  If you have
  > some good ideas or you know a goog site concerning this
  > problem. 
  >

The man who literally WROTE THE BOOK on Phase Locked
Loops (_Phaselock_Techniques_, published by John Wiley
and Sons) is a consulting engineer; perhaps you might
like to hire him to do some of the work.

His name is Floyd M. Gardner and his consultancy
business has an advertisement in the classified
ads of _IEEE_Spectrum_ magazine.  He appears to
be based in Palo Alto, California, USA.

 -Mark Johnson
Article: 7888
Subject: Re: Internal tri-state emulation.
From: aquantz@ibm.net (Aaron Quantz)
Date: Mon, 27 Oct 1997 17:15:26 GMT
Links: << >>  << T >>  << A >>
Roger Yau <rogeryau@net.polyu.edu.hk> wrote:

>Hello,
>
>I wanted to translate my old design ( XC5202 ) to Altera Flex8282A.
>When I completed and compile it, it can't fit into Flex8282ATC100.
>Later, I find that the "Internal tri-state emulation" of the Altera
>use up many resource (over 40 LE's). Is there any function(s) of the
>compiler to solve this problem ? Xilinx's internal tri-state do not
>consume any logic cell!
>
>Roger Yau
>Easson Precision Ltd.

I generally use muxes. The Altera parts don't have tri-state
capability except at the I/O pins.

Regards,
Aaron Quantz                    \^ ^/
                                )@ @(
+---------------------------oOO--(_)------------------------------------+
+ Mgr Software Development, Turret Control Systems                      +
+ HR Textron                        | Phone: (805) 253-5471             +
+ 25200 W. Rye Canyon Rd.           | Fax:   (805) 253-5962             +
+ Valencia, CA USA 91355-1265       | Email: aquantz@ibm.net            +
+ Visit the Textron web site: http://www.textron.com                    +
+-----------------------------------Oooo--oOO---------------------------+
                              oooO (   )
                             (   )  ) /
                              \ (  (_/
                               \_)
Article: 7889
Subject: Re: design sites
From: tom_curran@memecdesign.com (tom curran)
Date: Mon, 27 Oct 1997 18:52:44 GMT
Links: << >>  << T >>  << A >>
Hi Robbie,

I'll give my own company a plug.  Go to...

www.memecdesign.com

We are Xilinx design experts, so we are naturally biased to Xilinx,
but don't let that scare you.  It is always best to use whatever
vendor and tool best serves your needs.

take care,
tom

On 26 Oct 1997 19:28:50 GMT, "Thielemans - Van Heghe"
<robbren@skynet.be> wrote:

>Hello everyone,
>
>I would be very pleased if someone could send me interesting links to FPGA
>design sites, information besides the vendors of course. Thanks in advance,
>
>Robbie

Article: 7890
Subject: XILINX pin compatible replacements
From: peter299@maroon.tc.umn.edu (Wade D. Peterson)
Date: Mon, 27 Oct 1997 19:33:41 GMT
Links: << >>  << T >>  << A >>
Does anybody know if anybody makes pin compatible replacement parts
for XILINX XC4005, XC4006 or XC4008 devices?

Thanks a bunch.

Wade


-----------------------------------------------------
Wade D. Peterson         | TEL: 612.722.3815
Consultant to Industry   | FAX: 612.722.5841
3525 E. 27th St. No. 301 |---------- EMAIL ----------
Minneapolis, MN  55406   | peter299@maroon.tc.umn.edu
---------------- Committed to Quality ---------------

Article: 7891
Subject: Counter Problem
From: winf176@ab200.rz.uni-karlsruhe.de (Teilnehmer Informatik I)
Date: 27 Oct 1997 20:42:14 GMT
Links: << >>  << T >>  << A >>
Hello!

I'm implementing several counters in a Lattice ispLSI1016.
For larger counters in a syncronous design, you need lots of ProductTerms.
-> Split in many MacroCells. Grrrr.
With an asyncronous counter on the other hand, you need 2 Macrocells
(FlipFlop + Carry) per bit. Aaaaargh.
What could I do to save resources???

Thanks
Armin



Article: 7892
Subject: Re: generic library for lattice isp
From: Tom Bowns <bowns@data-io.com>
Date: Mon, 27 Oct 1997 21:18:01 GMT
Links: << >>  << T >>  << A >>
Robert E. Engle Jr. wrote:
> 
> i have a sizable library of generic modules i have written for the
> synario system, that works with the versin lattice gives away.

The explanation goes without saying, I suppose: The .SYM and .ABL files
of the desired function or functions must be included as part of the
project. That means not only loading the symbol into your schematic, but
importing the .ABL associated with it as a source module in your ISP
Synario project.

Otherwise you get that little "?" thing  in the sources window.

-TBB
Article: 7893
Subject: Re: Counter Problem
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 27 Oct 1997 14:52:24 -0800
Links: << >>  << T >>  << A >>
You can create an internediate carry signal that you then feed to all
the higher-order bits, and thus you still have a fully synchronous
counter. Or you build a synchronous counter of maximum efficient length,
then use its output as the clock for a new more significant counter. It
all depends how highly you value synchronous operation, and whether you
are loadable or even up/down.

Peter Alfke, Xilinx.

Article: 7894
Subject: Re: XILINX pin compatible replacements
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 27 Oct 1997 15:01:03 -0800
Links: << >>  << T >>  << A >>
Xilinx makes the pin-compatible functional supersets XC4000E ( 5 V) and
XC4000XL (3.3 V ) and the XC5200 family ( 5 V ) which has compatible
pin-outs, in case you are allergic to the original XC4000 ( why?).

Nobody makes pin- and functional compatible substitutes, and it is
unlikely that there will be much second-sourcing in the future. At most,
there might be devices that happen to have their supply pins in the same
location, whatever significance that has.

Peter Alfke, Xilinx Applications
 
 
 

Article: 7895
Subject: Re: XILINX pin compatible replacements
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Mon, 27 Oct 1997 15:12:34 -0800
Links: << >>  << T >>  << A >>
The answer depends a lot on your goal.

If you want devices that are directly pin-compatible and
function-compatible, then you probably want to look at the following
devices:

XC4005  --> XC4005E  -->  XC4005XL (3.3 volt with 5 volt tolerant I/O)
XC4006  --> XC4006E
XC4008  --> XC4008E

The Xilinx XC5200 family also has devices that are pin compatible to the
XC4000 family but with a different internal architecture.  Most designs
are easily transferred, except for those that contain RAM.

Supposedly, the new Atmel's new AT40K family is pin compatible with the
XC4000 family, but also with a different internal architecture.

-----------------------------------------------------------------------
Steven K. Knapp                 'Great designs happen "OptiMagic"-ally'
OptiMagic, Inc.
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
 Phone:  1-408-454-1811


Wade D. Peterson wrote in message <632ja0$4g3@epx.cis.umn.edu>...
|Does anybody know if anybody makes pin compatible replacement parts
|for XILINX XC4005, XC4006 or XC4008 devices?
|
|Thanks a bunch.



Article: 7896
Subject: DSP functions on FPGAs
From: geraldwilliams@hotmail.com
Date: Mon, 27 Oct 1997 18:22:13 -0600
Links: << >>  << T >>  << A >>
I am looking at a host of DSP applications (some high fidelity audio,
some telephony quality ... multiple channels), and am interested in
implementing them in FPGAs.

I am interested understanding from designers who have implemented their
own DSP functions about the challenges and pitfalls of implementing DSP
functions in FPGAs.

(I am also interested in the relative merits of the 'core/megafunction'
offerings from Xilinx and Altera).

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Article: 7897
Subject: Re: All Digital DLL or PLL with less than 20ps resolution
From: "Huang, Yueqiang" <yueqiang@sal-sun122.usc.edu>
Date: 27 Oct 1997 17:51:37 -0800
Links: << >>  << T >>  << A >>
Please see the paper:

J. Dunning et al., ``An All-Digital Phase-Locked Loop with 50-Cycle 
Lock Time Suitable for High-Performance Microprocessor'' in IEEE J. 
of Solid-State Circuits, April 1995, pp. 412-422.

Best regards,
yueqiang

On Mon, 27 Oct 1997, Ammann Michael wrote:

> Does anybody have a good idea, how to design an All Digital DLL or
> PLL on a 0.8 CMOS Process. The PLL or DLL should have a hold range
> from 30kHz to 50kHz, and veri low jitter (less than 20ps !).
> If you have some good ideas or you know a goog site concerning this
> problem. 
> 
> Send me a mail please
> 
> ------------------------------------------------------------------
> Michael Ammann                                    +41 41 741 17 91
> Keltenweg 20                  http://www.stud.ee.ethz.ch/~mammann/
> CH-6312 Steinhausen                        mammann@stud.ee.ethz.ch
> ------------------------------------------------------------------
> 
> 
> 

-- 
Best regards,
yueqiang
Article: 7898
Subject: Altera EPC1 and Chipmaster 6000
From: Russell Magee <bigruss@cheetah.spots.ab.ca>
Date: 28 Oct 1997 06:24:24 GMT
Links: << >>  << T >>  << A >>
 Hi all,

   We've hit a snag here at work, trying to program the Altera EPC1 configuration
EPROM using the Chipmaster 6000 from Logical Devices Inc. Logical Devices says they
have verified the 6000 with the EPC1, but we can't seem to program any with our unit
(it always fails on verify pass).
   Has anyone else experienced problems with the EPC1 part? We've heard rumours
(from another EPROM programmer maker) that Altera has somehow changed the programming
requirements of the EPC1 *without* changing the part number! If so, all I can say is
"$%@#!$!". We would have bought Altera's own programming unit, but the delivery lead
time was many weeks. Sigh..

  Any advice appreciated,
   -Russ Magee


Article: 7899
Subject: Re: Counter Problem
From: jim granville <Jim.Granville@xtra.co.nz>
Date: Tue, 28 Oct 1997 22:33:23 +1300
Links: << >>  << T >>  << A >>
Teilnehmer Informatik I wrote:
> 
> Hello!
> 
> I'm implementing several counters in a Lattice ispLSI1016.
> For larger counters in a syncronous design, you need lots of ProductTerms.
> -> Split in many MacroCells. Grrrr.
> With an asyncronous counter on the other hand, you need 2 Macrocells
> (FlipFlop + Carry) per bit. Aaaaargh.
> What could I do to save resources???
> 
> Thanks
> Armin

I don't have the Lattice data handy, but the secret to large counters
is either

TOGGLE flip flops. ( can build Up.Dn.Load )
 or
D FF, with a CLOCK Enable product term

 If you have neither, then you are stuck with growing width terms...

- jg

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