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Messages from 6575

Article: 6575
Subject: FPGA'98 Call For Papers
From: hauck@ece.nwu.edu (Scott A. Hauck)
Date: Tue, 03 Jun 1997 14:10:05 -0500
Links: << >>  << T >>  << A >>
                                 FPGA `98
                             Call for Papers

                1998 Sixth ACM International Symposium on
                     Field-Programmable Gate Arrays

                  DoubleTree Hotel, Monterey, California
                          February 22-25, 1998

                   http://www.ece.nwu.edu/~hauck/fpga98

        ==========================================================
As Field-Programmable Gate Arrays become more essential to the design of
digital systems there is increased pressure to improve their performance,
density and automatic design. This symposium follows the largest ever
gathering of this kind last year in Monterey at FPGA `97. For FPGA `98,
we are once again soliciting submissions describing novel research and
development in one or more of the following (or similar related) areas
of interest:

FPGA architecture: logic block & routing architectures, I/O structures
                   and circuits, new commercial architectures.
CAD for FPGAs:     placement, routing, logic optimization, technology
                   mapping, system level partitioning, testing and
                   verification.
Interactions:      between CAD, architecture, applications, and
                   programming technology.
Fast prototyping:  for System level design, Multi-Chip Modules.
Applications:      use of FPGAs in novel circuits, as emulators and
                   compiled accelerators.
Field-programmable interconnect chips and devices (FPIC/FPID.)
FPGA-based compute engines.
Field-programmable analog arrays.

        ==========================================================
Authors should submit 20 copies of their paper (12 pages maximum) by
September 26, 1997. Notification of acceptance will be sent by December 1,
1997. The authors of the accepted papers will be required to submit the
final camera ready copy by December 15, 1997. A proceedings of the accepted 
papers will be published by ACM, and included in the ACM/SIGDA CD-ROM
publications. All submissions should be sent to:

                           Sinan Kaptanoglu
                               FPGA `98
                          Actel Corporation
                       955 East Arques Avenue,
                       Sunnyvale, CA 94086 USA
                        e-mail:sinan@actel.com
                        phone: (408) 522-4319
                          fax: (408) 522-8041

        ==========================================================

General   Chair: Jason Cong,       UCLA,
Financial Chair: Carl Ebeling,     U. of Washington,
Program   Chair: Sinan Kaptanoglu, Actel,
Publicity Chair: Scott Hauck,      Northwestern U.

============================
Technical Program Committee:
============================

Michael Butts,             Quickturn
Jason Cong,                UCLA
Eugene Ding,               Lucent
Carl Ebeling,              U. of Washington
Scott Hauck,               Northwestern U.
Dwight Hill,               Synopsys
Brad Hutchings,            BYU
Sinan Kaptanoglu,          Actel
David Lewis,               U. of Toronto
Fabrizio Lombardi,         Texas A&M
Jonathan Rose,             U. of Toronto
Rob Rutenbar,              CMU
Malgorzata Marek-Sadowska, UCSB
Gabriele Saucier,          IMAG
Martine Schlag,            UCSC
Tim Southgate,             Altera
Steve Trimberger,          Xilinx
John Wawrzynek,            UCB
Martin Wong,               UT at Austin

============================================================================
Sponsored by ACM SIGDA, with support from Actel, Xilinx, Altera, and Lucent.
============================================================================
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
|               Scott A. Hauck, Assistant Professor                         |
|  Dept. of ECE                        Voice: (847) 467-1849                |
|  Northwestern University             FAX: (847) 467-4144                  |
|  2145 Sheridan Road                  Email: hauck@ece.nwu.edu             |
|  Evanston, IL  60208                 WWW: http://www.ece.nwu.edu/~hauck   |
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
Article: 6576
Subject: Best value for Verilog Simulation!
From: Alexandru Seibulescu <alex@fintronic.com>
Date: Tue, 03 Jun 1997 13:43:14 -0700
Links: << >>  << T >>  << A >>
PRESS RELEASE

06/02/97  10:00 Fintronic releases Super FinSim. Aggressive pric-
ing!

San Mateo CA (June 2, 1997) Fintronic USA, Inc. the  supplier  of
high quality Verilog Simulators (with over 800 Verilog simulators
installed worldwide) announces today that it has introduced Super
FinSim  to  its  product  line.  Super FinSim supports the entire
Verilog language, as well as a  complete  simulation  environment
based  on PLI, SDF, and VCD. Super FinSim provides any mixture of
compiled and  interpreted  simulation  in  order  to  achive  the
fastest turnaround time. Short simulations are run in interpreted
mode whereas long simulations are run in  compiled  mode.  State-
ments that are seldom executed are interpreted whereas statements
often executed are compiled.

Technology: With Super FinSim Fintronic has introduced the  first
mixed  event and cycle simulator for Verilog. A smart partitioner
analyzes the design and decides which areas can be  simulated  by
the Enhanced Cycle Simulation (ECS) kernel. The rest is simulated
by the event driven kernel. Therefore Super FinSim does  not  re-
quire  any special design methodology. It preserves accurate tim-
ing information, can handle modules with path  delays,  and  sup-
ports simulation values of Xs and Zs.

Super  FinSim supports all popular display tools including Design
Acceleration's SignalScan, Veritools's Undertow, and IK Technolo-
gy's  Ishizue.  FinSim, which does not include the ECS kernel nor
the optimizations made possible by the detailed analysis required
for  the  ECS partitioning, is the simulator used in the Veribest
Design System.

As an option, Super FinSim supports FinCov a  tightly  integrated
code coverage with very low overhead (under 35%), making it a vi-
able solution for regression code coverage.

Super FinSim supports co-verification of C code and  hardware  by
providing an efficient interface between the simulated C code and
the hardware simulation.

Pricing and Availability: Super FinSim provides  the  best  value
for  the  money. List prices include one year maintenance. Prices
on the PC platform have recently dropped. The new line  of  Super
FinSim  simulators  range in price from $799 to $28,000 depending
on product configuration and platform. Fintronic has a  Web  page
at  http://www.fintronic.com,  which  can be used for placing or-
ders, requesting demo licenses, checking prices,  etc.  Fintronic
provides hotline support and software distribution via the Inter-
net.  For more information send e-mail to  info@fintronic.com  or
contact Dr Alec Stanculescu by calling 415 349 0108/x105.

Mission:  Fintronic  USA has a mission to supply the highest per-
formance Verilog simulators available at the  best  price/perfor-
mance ratio.

Fintronic  will  exhibit at DAC 97 in booth no 546 in the Anaheim
Convention Center, June 9-12, 1997. Fintronic's vendor  presenta-
tion will be held in rooms A6/A7 on June 9, at 9:20am.
Article: 6577
Subject: Memory workshop, San Jose
From: fmeyer@cs.tamu.edu (Jackie Meyer)
Date: 3 Jun 1997 21:12:57 GMT
Links: << >>  << T >>  << A >>
The annual IEEE workshop on

                     MEMORY Technology, Design, and Testing

will be held       August 11-12    in     San Jose, California

An abstract of the keynote address is attached.  Further details can be
found at <ftp://ftp.cs.tamu.edu/pub/fmeyer/service/mtdt97/abstracts.html>.

We are having sporadic problems with our file system.  If you have any
trouble retrieving stuff, please just <mailto:fmeyer@cs.tamu.edu>.



                               KEYNOTE ADDRESS

     
              Matching Memory to the Power of Personal Computers


                               Dr. Richard Foss

                      MOSAID Technologies, Incorporated


                                   ABSTRACT

     
For almost a decade, the makers of DRAM ignored the growing problems
of accessing data at rates matching the exponentially growing demands
of new microprocessors. The increase in memory densities meant that
the traditional form of DRAM, with features and performance unchanged
since the mid-70's, actually worsened with each generation from a
systems perspective. A present-day DRAM offers an eighth or less of
its capacity as an active memory: the remainder of the chip is dead
capacitance even in an active cycle. In addition, the data is not in a
useful format and the analog mess of timing parameters is a system
designer's nightmare. Patches designed to increase raw bandwidth
helped only marginally at the cost of making the timing specifications
almost unworkable.

A major advance came with the thrashing out of a new approach to the
format of DRAM in the JEDEC committee of the EIA.  The Synchronous
DRAM (SDRAM) represented the first significant re-think of the
functions of a DRAM since the 4K.  All address, control, and data
inputs were referenced to a master clock, latency was introduced and
made programmable and programmable burst sequences allowed the memory
to handle specific processors and clock speeds.  As a key feature,
multi-banking increased the probability of data hits on open pages of
data. Despite some early skepticism, the SDRAM and its Graphics
cousin, the SGRAM, is now seen as becoming the dominant form of main
memory chip by millennium.  Inevitable, what both system and chip
designers have learned from the SDRAM revolution is what should really
have been done! The still mounting pressure for more effective (as
opposed to raw and hence generally unusable) bandwidth also drives
work on potential successors to SDRAM or to future variants and
enhancements of SDRAM.  Simply upping the clock frequency is not
enough.  It is necessary to optimize the memory system by having chips
which meet the following needs:

1) High effective bandwidth by matching the control and address bus
rates to data rates both within a chip (bank to bank) and from chip to
chip using an efficient protocol.

2) Resolution of real-world bus timing issues at high clock rates
without imposing high system level cost or power burdens.
     
These goals need to be met while simultaneously allowing an expandable
and versatile system, conforming to an open standard capable of being
implemented in a variety of ways.  An attractive resolution of these
somewhat conflicting demands has been achieved by an industry-wide
consortium under IEEE auspices as SL DRAM.  Adapting what has been
learned from SDRAM, it has added capability in the areas noted while
simultaneously reducing system power demands by control-driven power
management.
     
The pattern of future standards for the Memory business is thus being
set by world wide groupings of the major players in this Multi-Billion
dollar industry.  There are numerous issues still to be fully
resolved, not least those of economical production testing.  The
address will highlight some of these key topics.
Article: 6578
Subject: Re: Altera Versus Xilinx
From: jhallen@world.std.com (Joseph H Allen)
Date: Tue, 3 Jun 1997 22:33:13 GMT
Links: << >>  << T >>  << A >>
In article <33934047.3888020@nntp.netcruiser>,
Stuart Clubb <s_clubb@netcomuk.co.uk> wrote:

>Altera FLEX10K is not PCI compliant. Doesn't matter how much marketing
>spin you put on it, or how many glossy adverts you throw at the
>market, or how much html you use on your web site.

>1
>The Clock pin capacitance breaks the spec. This is due to be changed,
>so they will be compliant on this checkbox at some point in the
>future.

>2
>The pci_a core as it stands has some signals from the PCI bus driving
>two pins on the FLEX10K device. That breaks the spec, and puts a
>maximum 20 pF load on the pin.

>Today, they are not compliant with the PCI specification, end of story

Hey, don't have a cow man!  It's nothing that a few series resistors can't
fix.  They have to be large enough so that the input impedance with the
resistor would equal the reactance of a PCI single pin, but small enough so
that outputs can still drive the bus with enough current (assuming any
output pins are doubled up).  Around 10-27 ohms should work fine- make sure
there's no ground plane under the resistor (to reduce capacitance).

-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 6579
Subject: Your recommendation needed
From: jlou@sahand.usc.edu (Jinan Lou)
Date: 3 Jun 1997 15:40:04 -0700
Links: << >>  << T >>  << A >>
Hi, all,

We are about to make a decision on purchasing a FGPA synthesis tool.
The candidates are FPGA Express from Synopsys and Synplify from
Synplicity. The target FPGA is Lucent OR2C40A (40k gates), and the design
is about 100k in size.

We would like to know which one can handle the size of the design well,
which one will produce a better result, and which one will run faster.
Your comments are really appreciated.


Please send your comments to Jinan.Lou@tanner.com.


Thank you in advance


Jinan


Article: 6580
Subject: Alternate Verilog FAQ : New release
From: rajesh@comit.com
Date: 4 Jun 1997 00:20:44 GMT
Links: << >>  << T >>  << A >>
Hi All



	I have released new version of alternate Verilog FAQ.

I added following things.



1] A new "Technical Topics" section. This time information

   about state machine design is added.



2] Book section is modified. J. Bhasker's new book is added 

   in the list.



URL is :  http://www.comit.com/~rajesh/verilog/faq/alt_FAQ.html



Please email me suggestions.

Rajesh

rajesh@comit.com


--

Posted using Reference.COM                         http://www.reference.com
Browse, Search and Post         Usenet and Mailing list Archive and Catalog.

InReference, Inc. accepts no responsibility for the content of this posting.
Article: 6581
Subject: Re: Your recommendation needed
From: "Dr. Endric Schubert" <endric@exemplar.com>
Date: Tue, 03 Jun 1997 18:55:45 -0700
Links: << >>  << T >>  << A >>
Jinan Lou wrote:
> 
> Hi, all,
> 
> We are about to make a decision on purchasing a FGPA synthesis tool.
> The candidates are FPGA Express from Synopsys and Synplify from
> Synplicity. The target FPGA is Lucent OR2C40A (40k gates), and the design
> is about 100k in size.
> 
> We would like to know which one can handle the size of the design well,
> which one will produce a better result, and which one will run faster.
> Your comments are really appreciated.
> 
> Please send your comments to Jinan.Lou@tanner.com.
> 
> Thank you in advance
> 
> Jinan


Hi Jinan!

Didn't you forget one tool: Exemplar Logic's Galileo?

Yes, I work for Exemplar! No, I am not a marketing nor a sales guy, and
I know what it means to synthesize 100K gate designs...

I really want to encourage you to look at our new GALILEO EXTREME. We
put into it a lot of new technology to speed up the synthesis and
improve the results. Go and find some information on www.exemplar.com or
just visit our booth at DAC and have a look at it.

Endric 

-- 
-----------------------------------------------------------------------
Dr. Nils Endric Schubert                            endric@exemplar.com
Exemplar Logic
815 Atlantic Avenue, Suite 105
Alameda, CA 94501

Tel.: (510) 337 3761
Fax.: (510) 337 3799
-----------------------------------------------------------------------
Article: 6582
Subject: Re: VHDL PCI FPGA Implementation
From: "Austin Franklin" <darkroo4m@ix.netcom.com>
Date: 4 Jun 1997 02:47:17 GMT
Links: << >>  << T >>  << A >>
Stuart,

> >The design I 'use' does not have this problem for target or master... 
;-)
> 
> Sorry Austin, I should have responded faster. I bow to your superior
> engineering skills (to Xilinx). Have they offered you money yet?

Well, funny you should ask that...  Before they 'contracted' High Gate
Design to do their PCI interface design, they were in negotiation with me
to buy my PCI design (which, by the way, was done about a year before the
High Gate design was...), but then, suddenly, they decided to go with High
Gate...

Well, I did beta site the High Gate version, found many many many bugs and
misunderstandings of the PCI spec etc.  I do not recommend using their
design, except for a possible template with which you can re-use 'some' of,
but be prepared to do a lot of work on it...

They (Xilinx) called me a while ago and asked if I would tell them how I
did my design....and I told them that I was interested in telling them, but
since they poopooed me on a few things over the years, I wasn't really
happy with them....so we'll see if they pony up!

> I therefore summarise my comments to:
> 
> Lucent is fully PCI compliant.
> Xilinx is fully PCI compliant, if you redesign the core they sell you.

Or use Austin's design ;-)

> Altera is not PCI compliant.
> 
> Deathly silence from 2610 Orchard Parkway. Hmm, maybe I should put a
> press release out...

Who'se at that address?

Later,

Austin

Article: 6583
Subject: Re: Memory workshop, San Jose
From: mjohnson@netcom12.netcom.com (Mark Johnson)
Date: Wed, 4 Jun 1997 03:55:39 GMT
Links: << >>  << T >>  << A >>
Poor old Dick Foss.  He appears unwilling to admit that
SDRAMS (on which his company holds patents and from which
he hopes to profit) have lost the war.  Indeed the entire
53-line abstract carefully avoids mentioning the winner: Rambus.
Not only does Foss make zero buxx from Rambus' complete and
total victory, he loses face because he backed the wrong horse:
first CTT, then SSTL, now DDR. So, with head firmly implanted in
sand, he goes around giving misguided talks about the superiority
of SDRAM while studiously neglecting to say that it's already lost.
 
Perhaps he'll even sic his lapdog (PdM) on me for pointing
out the bankruptcy of his abstract, and, one presumes,
the talk itself.  Watch for posts from mosaid.com and/or
Kanata, Ontario.

Mark Johnson
Silicon Valley, California
Article: 6584
Subject: Re: In circuit programming of flash with Xilinx devices??
From: Martin Mason <nospam_mtmason@ix.netcom.com>
Date: Tue, 03 Jun 1997 23:44:57 -0700
Links: << >>  << T >>  << A >>
John McGibbon wrote:

>  It could also be used for
> reconfiguring serial flash proms from Atmel.
> 
> John
> john_mcgibbon@memecdesign.com

If yo would like more information on Atmel ISP FPGA configuration memories 
check out http://www.atmel.com/atmel/products/prod182.htm and the AT17C FAQ 
at url http://www.atmel.com/atmel/products/fpga/fpga1.html.  These parts now 
support both 5.0V and 3.3V (LV) ISP read and/or write.  The protocols used to 
program the devices in-system can be designed in FPGA hardware *relatively* 
easily you will find the link below useful if you are interested in going 
that path.

You can contact Atmel at configurator@atmel.com if you have any futher 
questions.

Martin Mason
martin@atmel.com
AT17 Series Apps and Marketing
Atmel Corp.

and Uffe Tyrsted Toft wrote:

>Take a look on the following homepage. You will find an I2C bus controller 
>a.o.
>
>http://www.acte.no/freecore
>
>Regards
>Uffe Tyrsted Toft
>-------------------------------------------
>ACTE NC Denmark A/S
Article: 6585
Subject: Re: New Reconfigurable Computing newsgroup?
From: Martin Mason <nospam_mtmason@ix.netcom.com>
Date: Tue, 03 Jun 1997 23:58:06 -0700
Links: << >>  << T >>  << A >>
How about comp.arch.fccm

Those of us remotely involved in the industry know this term - right ???

Martin Mason
martin@atmel.com
FPGA/AT17C
Atmel Corp.
Article: 6586
Subject: Re: ECL FPGA Demo at DAC
From: Tim Forcer <tmf@ecs.soton.ac.uk.nojunk>
Date: Wed, 04 Jun 1997 09:48:43 +0100
Links: << >>  << T >>  << A >>
Eric Fleischman wrote:
> 
> If you are attending the Design Automation Conference, don't miss
> DynaChip's demonstration of their Fast Field Programmable Gate Array.
> These unique FPGAs use Active Repeaters to propagate signals with
> extremely short routing delays.
> 
> At the demo you will see:
> 
>    - Over 100 MHz system-level performance using HDL synthesis flows
>    - Short, predictable routing delays that are not affected by fanout
>    - Ultra high speed I/O structures that support up to 200 MHz clock
> and data
>    - ECL, PECL and GTL interface levels
>  ... cut...

At the UK's Annual Advanced PLD & FPGA Day on May 14, Xilinx reported
implementing three designs that clocked at 200MHz "worst-case guaranteed
over temperature and voltage".  The essential technique was to keep all
the high speed circuitry close together and as small as possible -
lower-rate signals were propagated elsewhere on the IC.  The
presentation (but not the published paper) stated that the main
difficulty was in providing EXTERNALS (eg PCB layout) that didn't
compromise the very high rate signals which the IC itself was happy
with.

What Xilinx certainly did not offer was 200MHz across a whole FPGA.  Is
this what can be expected from DynaChip?

Tim Forcer               tmf@ecs.soton.ac.uk
Department of Electronics & Computer Science
The University of Southampton, UK

The University is not responsible for my opinions
Article: 6587
Subject: Ripp10 Board
From: elvis@dcs.rhbnc.ac.uk
Date: Wed, 04 Jun 1997 10:45:03 +0100
Links: << >>  << T >>  << A >>
Hi all,



Is anyone out there using the RIPP 10 Board?  If so, do you have or

know where you can get a template ACF file for the FLEX81188 chip in

socket U5?



Cheers, Barry Rising



 barry@dcs.rhbnc.ac.uk

 Research Postgraduate

 Dept of Comp Sci

 Royal Holloway

 University of London
Article: 6588
Subject: RIPP10 Board: Correct EMAIL Address
From: Barry Rising <barry@dcs.rhbnc.ac.uk>
Date: Wed, 04 Jun 1997 10:49:56 +0100
Links: << >>  << T >>  << A >>
Hi all,

(Who messed with my netscape preferences!?!)


Is anyone out there using the RIPP 10 Board?  If so, do you have or know
where you can get a template ACF file for the FLEX81188 chip in socket
U5?



Cheers, Barry Rising



 barry@dcs.rhbnc.ac.uk

 Research Postgraduate

 Dept of Comp Sci

 Royal Holloway

 University of London
Article: 6589
Subject: Summer Student Job
From: "David G. Stork" <stork@crc.ricoh.com>
Date: Wed, 04 Jun 1997 10:58:16 +0000
Links: << >>  << T >>  << A >>
Please distribute widely but
                   delete after June 15, 1997

===================================================================

                      SUMMER STUDENT JOB

Ricoh Silicon Valley has a summer research position for an
exceptionally talented graduate student in computer science.  The
central task is to analyze implementations of image processing
and pattern recognition algorithms on novel, parallel configurable
supercomputer hardware.

The ideal candidate will have experience in the following:

General knowledge

   * Computer architecture, especially DSP architectures
   * Parallel computing
   * Theoretical Computer Science
           . analysis of algorithms
           . computational complexity
   * Configurable computing
   * FPGAs
   * Image processing and pattern recognition

Specific skills

   * C/C++/UNIX
   * SUIF compiler toolkit
   * MPI (Message Passing Interface)


TERMS

   The employment period is flexible and can accommodate the
   successful applicant's schedule, but is roughly three months
   and can start immediately.  Salary is competitive.


ELIGIBILIGY

   Applicants must have an appropriate visa, work permit or green
   card.


BACKGROUND LITERATURE

*  "Increased FPGA capacity enables flexible, scalable CCMs:  An
   example from image processing" by Jack Greenbaum and Michael
   Baxter, IEEE Symposium on Field Programmable Custom Computing
   Machines (FCCM 97) Napa Valley, CA, pp. 252--258 (1997).

*  "Configurable Computing" by John Villasenor and William H.
   Mangione-Smith, Scientific American, pp. 67--71 (June 1997).


RICOH SILICON VALLEY

   The California Research Center of Ricoh Silicon Valley is a
   small research lab focussing on information and image
   processing, recognition and communication.  It is close to
   Stanford University and numerous Silicon Valley landmarks,
   including University of California's Berkeley and Santa Cruz
   campuses.  The culturally rich cities of San Francisco and
   San Jose are nearby, as are holiday sites such as the Pacific
   Ocean, Sierra Nevada mountains and Yosemite National Park.  The
   lab's atmosphere is collegial and informal, yet highly
   challenging and professional.


QUESTIONS

   Please consult our web site

                  http://www.rsv.ricoh.com

   for general background and

                  http://www.crc.ricoh.com/~stork/MLPSummerJob.html

   for more specific information.  Feel free, too, to contact
   Dr. Stork, at the below addresses.


TO APPLY

   Please e-mail an application letter, resume in clear-text ASCII
   (including relevant courses taken, papers, and your telephone
   number) as well as the names, e-mail addresses and phone
   numbers of at least two people familiar with your work.  E-mail
   your application to

                      stork@rsv.ricoh.com

   before June 15.  (Put "Summer student position" in the message
   header.)


Ricoh Silicon Valley is an Equal Opportunity Employer, and strongly
encourages qualified women and minority students to apply.


--Dr. David G. Stork
  Chief Scientist
  Ricoh Silicon Valley
  2882 Sand Hill Road #115
  Menlo Park, CA 94028-7820
  stork@rsv.ricoh.com
  415-496-5720
  http://www.crc.ricoh.com/~stork

===================================================================
Article: 6590
Subject: + Last Year's (1996) DAC Trip Report +
From: jcooley@world.std.com (John Cooley)
Date: Wed, 4 Jun 1997 13:49:52 GMT
Links: << >>  << T >>  << A >>

  [ Enclosed is a review of last year's (1996) DAC in Las Vegas.  If you 
    see me at DAC next week in Anaheim, tell me what you think's hot and
    what's not, so I can include it in this year's review!   :^)   - John ]

-------------

    !!!     "It's not a BUG,                           jcooley@world.std.com
   /o o\  /  it's a FEATURE!"                                 (508) 429-4357
  (  >  )
   \ - /              The Fourth Annual ESNUG/DAC Awards:
   _] [_                 "Teamsters, Vegas & DAC '96"
                                   - or -
      "One Engineer's Review of DAC '96 in Las Vegas, NV, June 3-7, 1996"

                               by John Cooley

        Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
      Legal Disclaimer: "As always, anything said here is only opinion."


        [ Check out pg. 16 in this week's (June 17th) EE Times or
          "cooley.gif" at "http://techweb.cmp.com/eet/eda/graphics/"
          for the photo of the DAC freebies and their awards!  - John ]


Once I saw the AFL/CIO (the Teamsters) also having a conference in the same
hotel as DAC, I had this weird sense that Vegas more their town than ours.
These live-for-the-moment truckers drank like fish, would gamble away a
month's pay in an hour at a blackjack table, and could keep an army of those
"private nude dancers" busy in their hotel rooms until dawn.  In contrast,
my fellow more analytical engineers tended to drink lightly, only gambled a
little money at the best odds (which we carefully calculated), and were way
too afraid of AIDS to ever do anything more than look at a "private dancer."

While truckers impress each other with the inside scoop on Jimmy Hoffa, we
engineers "wow" each other by discussing undocumented Synopsys commands.
Truckers get belly laughs from telling offensive jokes about every race,
creed, gender and color; engineers get their kicks safely reading "Dilbert."
Clever engineers fret over which hot new start-up to join; clever truckers
try to figure out how to skim off of the Teamsters Retirement Fund.  (Even
marketing people see us as "different".  For conference freebies, truckers
got fun everyday guy stuff like 6-packs of beer, boxes of cereal, and
condoms.  We engineers only got cheap T-shirts, coffee mugs and puzzles...)

Although, I'm quite happy as an engineer, there's part of me now wondering:
"Is it too late to sign up for tractor trailer training school?"

Anyway, on with the 4th Annual ESNUG DAC Awards!



GREENPEACE AWARD: If EDA companies were living creatures, they'd be in one
healthy eco-system.  DAC grew 10 percent (to over 16,000 attendees) and the
exhibit floorspace itself increased 25 percent.  The exhibitor count jumped
from last year's 152 to this year's 164.  32 of last year's companies didn't
come back with their own booths this year -- only to be replaced by 37 new
companies.  Although i-Logix, Vista, and Harmonix moved on, most of the
missing 32 (like Attest, Exemplar, and Silerity) were gobbled up by larger
companies as part of the EDA food chain.  A few did simple name changes
like Intergraph becoming VeriBest; a few even mutated, like the RaviCad's
consulting becoming Virtual Chips, a PCI-IP company, -- but most of the
new 37 are companies with new ideas.

   "I don't know why they keep showing that stuff.  After three years
    they've still never had a single customer outside of IBM."

            - A user commenting on IBM EDA still showing BooleDozer
              and EinsTimer at this year's DAC.

   "Jesus!  We beg and grovel for a bloody $2 billion and these slimeballs
    just saunter on in with $7 billion!"

            - An EDA vendor commenting that the jewelry convention also in
              Vegas during DAC displayed $7 billion of merchandise.  (The
              EDA industry as a whole only nets about $2 billion per year.)

BIG CHICKEN AWARD: When Nanette Collins (who does PR for VHDL International)
asked me to attend DAC's first Workshop for Women in EDA (as an observer), a
little angel in my right ear said: "John, now you can share that Bill Clinton
part of you which strongly supports Equal Opportunity.  It'll be a teary-eyed
moment to celebrate our human diversity."  Then a little devil in my left ear
said: "Are you kidding!?!  Nanette wants blood for all that press about
sparsely attended VIUF's.  She knows the Rush Limbaugh side of you dislikes
Affirmative Action and is more than clever enough to make her fantasy
EE Times headline 'COOLEY KILLED BY ANGRY MOB OF EDA FEMINISTS' come true!" 
(Self-preservation being a stronger instinct, I chickened out.  I later heard
101 women and two men attended: Bob Bellinger of EE Times and an unnamed
weasel/headhunter who kept asking everyone for their business cards.)


WORST FIRST IMPRESSIONS PARTY: Simplex Solutions took customers to see the
movie "Mission Impossible"; those who went were left stranded at a distant
theater with no taxi's.  Four AT&T engineers groused: "The final kicker was
when 5 Simplex people jumped in their car laughing and just drove away."

   "I guess the moral is, don't entrust your life to a CAD vendor."

            - Eric McCaughrin of SGI, who took a defective Veritools water
              bottle on a 3 day camping trip in the Grand Canyon.

MOST UNORIGINAL "NEW" PRODUCT IDEA AT DAC: Cycle-based simulators.  At least
a dozen companies (SpeedSim, Frontline, Fintronic, Synopsys, Vantage,
Chronologic, Pendulum, Cadence, Cadence Alta, Synopsys, Mentor (rumored),
and CAE Plus) have or are working on one.  It's like the R&D staffs from
these companies all call the same psychic hotline for advice.

FIRST 3-D DEMO AT DAC: Mimicing the crowds of people in the 1950's who went
to watch 3-D movies, nearly 300 DAC attendees donned special polarizing
glasses to watch LogicVision's Built In Self Test (BIST) demo -- a DAC first.


VERILOG VS. VHDL (PART 2): This time it's analog.  The Verilog-A LRM was
approved at this DAC.  Cadence, Meta-Software and Apteq are alreay finalizing
their Verilog-A simulators.  (Nanette wasn't too happy informing me that the
VHDL-A LRM, which was supposed to be done by this DAC, was again delayed.)

   "I still stand by those words."

             - Cadence CEO Joe Costello about his IVC quote that VHDL "was a
               $400 million mistake."  (Ironically, Cadence also sells a VHDL
               simulator that has done quite well in the public benchmarks.)

IP WAS HOT: Companies like VLSI Libraries, 3Soft, Technical Data Freeway,
Virtual Chips, SAND, CAST and Synopsys were all getting attention from
customers wanting re-usable designs.  Not wanting to be left out, Xilinx
pushed its LogicCore program, Altera released its LPM to the public domain,
and Crosspoint touted its CoreBank program for third party designs.  (There
were even hot rumors that these companies were in the act of forming some
sort of "IP Alliance" at DAC.)  Some even saw Casacade as an IP company.

FUNCTIONAL VERIFICATION WAS HOTTER: Eagle Design, DS Diagonal Systems,
Chronology, Cadence Alta, NuThena, and even the tiny Levetate got special
consideration from engineers trying to verify designs.  But what most users
ranted about was the newbie InSpec.  While most companies in this category
(which was easily confused with HW/SW Co-design) pretty much offered waveform
viewers and a framework all wrapped up in a glitzy GUI, InSpec gave users
an automatic way to generate functional test vectors combined with a clever
graphical analysis tool that quickly points out coverage holes.  System
Science also offers a dialect of Verilog that makes test generation easier.

MOST IMPROVED COMPANY: ViewLogic.  They're no longer hemorrhaging employees
(in fact, they're growing), the legal battle with the old Chronologic staff
is *finally* over, and instead of giving out cheesy white T-shirts, this year
they gave out golfer's putters which tied with Altera's basketballs for
BEST DAC FREEBIE.  View/Silerity's datapath compiler can now use accurate
View/Quad MOTIVE timing plus interface to the third party Synopsys Design
Compiler.  View/Chronologic's VCS got ASIC sign-off status from Motorola,
LSI, Toshiba, and Lucent.  VCS Roadrunner is beefed up 5X to 10X plus it's
now integrated with the View/Quad MOTIVE static timing analyzer and the
View/Sunrise ATPG tools.  View/Chronologic's universally-executable-yet-
still-encrypted Verilog Model Compiler (VMC) is perfectly poised to take
advantage of the growing IP boom.  Good rebound, Viewlogic!

   "We started the user group and let it go.  Like many fledglings, it
    struggled for a bit and died.  I even think Sean Murphy was the
    Chairman the user's group at the time."

            - Viewlogic CEO Alain Hanover responding to Sean Murphy's
              asking about needing a user group to develop innovative tools.
              (Sean was never involved with Viewlogic's users group.)

   "To Alain Hanover, CEO of Viewlogic: What happened to the IC PowerTeam
    concept?  I don't hear about it anymore."

            - Daniel Payne, Mentor Graphics, who was the Viewlogic
              marketing manager for IC PowerTeam before joining Mentor.

"YES, YOU CAN TEACH AN OLD DOG NEW TRICKS" AWARD: Unlike Savantage's SavanSys,
which is more of an engineer's business analysis tool to juggle costs and a
system's physical implementation (by answering: "Would this work better as
5 small PCB's and a backplane or as 2 bigger PCB's with connectors?"),
Omniview's FIDELITY is truely a system-level synthesis tool.  An offshoot of
the Carnegie-Mellon "Micon" project, it works as an add-on to Mentor's
Design Architect and Viewpoint Editors.  The user enters in a block diagram
a very detailed, highly parameterized design which FIDELITY then breaks
down into specific commercial IC's.  It's a lot like schematic capture on 
steroids and with a slightly higher IQ.


POWER! POWER! POWER!: The power freaks at this year's DAC got off on EPIC's
AMPS (a swapper that could optimize 30,000 transistor designs based on power,
delay and area), Simplex (for their circuit-level power analysis tools that
shows IC hot spots), Sente's WattWatcher (an RTL-level pre-synthesis power
analysis tool), System Science's toolset, and Cadabra's LILA.  Synopsys Power
Compiler got some interest, but there were far too many companies with SPICE
level/mixed signal solutions to choose from at DAC: Agape, Anagram, Analogy,
Ansoft, Bell Labs, CAD-Migos, Cadence, Contec, Deutsch Research, Interactive
Image, Mentor, Meta-Soft, Microsim, OEA, Symetry, TMA, and VeriBest.

   "After 15 years in this business, you stop believing in physics."

            - Gary Smith of Dataquest, after a professor just explained how
              it's physically impossible to design at 0.18 microns.

   "We call them 'Cheech & Chong'."

             - An EDA competitor referring to Cooper & Chyan Technology.

MOST DRAMATIC NEW PRODUCT ANNOUNCEMENT: The Friday before DAC, Simon Perry,
Chief Editor of a British electronics publication phoned around in the EDA
community asking "What's Synopsys' big secret annoucement at DAC?"  On the
Free DAC Monday, Synopsys had a security guard standing next to a workstation
covered with black drapes and a big "?" sign.  There was an extra sign saying
"You can find out at 2:30 today."  At 2:30 they had over 200 people standing
around this draped workstation.  Moments before the big Synopsys 2:30 press
announcement, the Synopsys people even caught and kicked out Synplicity CEO
Alisa Yaffa while she protested: "Hey, this is a press announcement!!!  It's
public information!!!"  Turns out that Synopsys was annoucing FPGA Express,
a PC based FPGA synthesis tool that will directly compete with Synplicity.
(Oddly enough, I thought I heard Nanette whisper "YES!" when they said FPGA
Express had a built-in VHDL tutorial but no Verilog tutorial.)

   "Seventy percent of my sales are on the PC.  Seventy percent of my
    revenues are from UNIX."

            - ViewLogic CEO Alain Hanover two years ago justifying why
              he bought so many top of the line UNIX-based EDA companies.

   "Take a gamble on us!  SYNOPSYS"

            - The logo on the freebie pocket protectors Synopsys gave out
              at their DAC party four hours after announcing FPGA Express.

   "I'd be happy to provide them the catsup for the crow they're now eating."

            - Dan Ganousis of VeriBest, who pushed EDA on Windows NT for 3
              years, noticing how the big EDA companies are now jumping in.

MOST CURIOUS NEW COMPANY: TriQuest offers a finite state machine thingy
that does all sorts of bizarre optimizations, decompositions and
transmogrifications on RTL level state machine code.  Whoa!

"NICHE WITHIN A NICHE" AWARD: Promoting a funky sort of BIST, CrossCheck
sells the ability to make low power designs, fabbed only at Asian foundries,
fully testable.  Frequency Technology offers a sub-half-micron, interconnect
calculator that specializes in troublesome 3-D geometeries.  Two runners up:
Incases makes a 3-D radiation simulation tool for PCB design and K2 offers
"automated reticle synthesis and high speed viewing."

MOST LIKELY TO GET SUED: While other EDA vendors are trying to get
Synopsys to put their proprietary compiler directives and pragmas into the 
public domain, ACEO Technology is already openly using them.


MOST APPROPRIATE FREEBIE: Cadence gave away free stopwatches so engineers
could time, in minutes, how long they still had a job once a Cadence
Spectrum Services salesman found their VP of Engineering.  You can even set
it to time in seconds once the Spectrum Technical Assessment Team arrives
at your site!  Cool!

   "OK, Spectrum Consulting may not be for everyone.  No one is making
    you use it.  I've never held a gun to anyone's head...   yet."

            - Cadence CEO Joe Costello responding to John Cooley's
              pointed questions about his consulting division.

BEST DAC PARTY: A tie between Quickturn and Mentor/Sun/HP.  Users loved the
Monday night party where Quickturn took everyone to see Penn & Teller's
comedy/magic show.  A lot of them enjoyed the quips Penn (the one who
speaks) took at engineers and Quickturn.  One such Penn quote: "Welcome to
Quickturn.  This is all mirrors, deception, misdirection and slight of
hand...   Oh, I'm speaking for Penn & Teller, not Quickturn right now."
Teller (the one who never speaks) even spoke to answer questions!  On Tuesday
night the hot party to crash was Mentor Graphic's 15th Anniversary (which was
also co-sponsored by Sun and HP.)  They rented the entire MGM Theme Park
where users got to see an acrobatic dualing pirate show, go on water rides
and simulated underground rides, see all sorts of roving musicians and odd
characters roaming the park (like clowns, giant mice, and Elvises) plus two
free drinks and dessert.  ("Beer and cake, yum!")  Everyone got a stuffed
dog doll and a nice Mentor/Sun knit shirt as freebies.

   "We had one influential Asian customer ask that we send both a male and
    a female stripper to his hotel room.  Nobody knows what happened for
    those two hours -- but it cost my company $700."

            - An anonyous voicemail from someone claiming to be an EDA
              vendor responding to a survey question.

   "What's 'parasitic extraction' ?!  Getting your ex-wife off of alimony?"

            - Overheard by a PR agent immediately after a press briefing.

"WHEN HARRY MET SALLY" FAKING IT AWARD: Escalade.  Most of the ESDA vendors
competed in the "Great ESDA Shootout" at the last HP Design SuperCon.  It
had an impact on these companies.  Wally Rhines, CEO of Mentor, said his
System Architect is being changed to make it more useable because of what
happened in the Shootout.  After clearing up a reporting snafu that Speed
Electronics did, I resynthesized Speed's design using FSM Compiler two
days before DAC, getting results of 1.80 nsecs -- placing Speed up with the
hand coders in the shootout.  And Summit Design should get some sort of DAC
FREQUENT FLYER BONUS AWARD for how much mileage they got out of doing so well
in the Shootout.  The kicker was that although Escalade chickened out of
the ESDA Shootout, they apparently were telling customers on the DAC floor
some incredible synthesis numbers they got from doing this shootout!

MOST CONTENT-FREE (AND ANNOYING!) FLOOR SHOW: For the *second year* in a row,
both users and EDA vendors felt the HP floor show was the most content-free
in all of DAC.  "I got so bored I didn't even wait around to get whatever
freebie they were giving out." said on EDA user.  The EDA vendors (especially
any within a four booth radius) were especially pissed with HP because they
had a very loud simulated earthquake every 20 minutes that was very annoying.


CAN'T KEEP IT UP AWARD: Many were frustrated that DACnet was down for most of
DAC.  "This year it vasn't vorth hacking.  It vas down so much nobody could
use it.", said the Swiss president of RubiCAD, Michael Reinhardt, who hacked
DACnet last year to send junk e-mail to potential customers.

   "Is there a technical person in the house?"

            - John Cooley to a room filled with hundreds of engineers
              when the microphones went dead on the DAC/CEO panel.

   "It's also an early warning system.  If you're at work and you're
    seriously thinking of opening and eating it, it's time to go home."

            - Michael McClure of Chronology, which gave away humorously
              relabelled cans of SPAM winning the FUNNIEST FREEBIE AWARD.

MOST "OUT OF SYNC" DAC PARTY: The official DAC "Black & Blue" biker party
was kept quite true to theme.  They gave everyone black T-shirts with a
red flaming DAC logo, they had lots of good food, an open bar that kept
serving until about midnight, and a band that played very dance-able music.
(I even saw Nanette dancing with her husband while she was wearing her
"VHDL Uber Alles!" T-shirt.)   They even had a temporary tatoo parlor plus
vintage Harlies occassionally going through the room.  The only problem was
this theme had virtually *nothing* to do with Las Vegas -- but it would have
fit in *perfectly* with last year's DAC in San Francisco where various
subcultures there truely love leather, tatoos, and men on motorcycles!


INTERESTING ODDS & ENDS: Design Acceleration, Veritools, Simutest, and
InterHDL offered Verilog tools like waveform displays to source code "lint"
programs to an optimizer for VCD files to queueing tools to Verilog/VHDL
translators.  On the VHDL side, LEDA offers another set of tools including
a VHDL encypter and Intellx demo-ed a VHDL analyzer.  Chronology's
TimingDesigner did automated timing diagrams and analysis on RTL-level code.
Design Acceleration, Veda, and Simulation Technologies are all plugging
Verilog/VHDL code coverage tools.  The SysAdmin types liked Platform
Computing's LSF, a workstation load balancer which helped users schedule
EDA tool runs over networks, Runtime's VOV, a tool that graphs dependencies
between thousands of files in a project, and Spectra Logic's carousel that
juggles either 60 4mm DAT's or 40 8mm cassettes to automatically back-up
240 to 280 gigabytes of disk.

   "I dunno.  I thought it said 'VeriCow' the first time I read it."

            - A user reacting to Simulation Technologies sign
              announcing their "VeriCov" coverage tool.

   "Our simulators are so hot, they knocked him out!"

            - Dan Ganousis, VeriBest, whose DAC booth manager passed out from
              heat exhaustion 10 minutes before the DAC floor show started.

TESTING FOR THE TRUELY PICKY: Not to be confused with wishy-washy functional
testing, these companies focus on finding *all* the bugs in a design.  ATG
plugged INTELLECT, a killer partial scan technology that can handle gated
and derived clocks, asynch logic, FF's, latches, RAM's and ROM's.  Attest
and Simucad are in the fault simulation software business.  Synopsys,
Mentor/CheckLogic, Viewlogic/Sunrise and Syntest were all doing ATPG demos.
Intellitech, Syntest and LogicVision barked about BIST and BSDL.  And still
in the new paradigm department, Chrysalis displayed the industry's first
interactive formal verification tool: Design Explore.

   "Formal verification isn't a nice thing to have on a project; it's an
    absolute must have!"

             - Alex Silbey, Silicon Graphics on the DAC verification panel.

"OBJECTS IN MIRROR ARE CLOSER THAN THEY APPEAR" AWARD: Although many users
feel Quickturn has the current lead over IKOS, Zycad, Aptix, Mentor/Meta-
Systems, and Synopsys/Arkos in the special-hardware-for-hardware-designers
market (especially since some of these aren't even on the market yet!), some
are now openly noticing how the growing gate counts in FPGA's from Xilinx,
Altera and Lucent might unexpectedly be changing this landscape.

MOST SUICIDAL DAC FREEBIE: Interactive Image gave away 300 completely free,
unrestricted copies of their $600 Electronic Workbench ($180,000 in total).
Hasn't anyone told these guys EDA vendors come to DAC to *sell* tools?

   "By the turn of the century, you will have 5 devices on your body with
    their own IP addresses.  Where you put them is your own business..."

             - Netscape CEO Jim Clark in his DAC Keynote address.

   "Yea, a few of us out dropped out of the EDA business to get into
    the Internet business.  Less hype and more money."

            - Overheard from an ex-CrossCheck employee.

THE SHAPE OF THINGS TO COME: The most immediate response engineers give is
"higher levels of abstraction" so they talk about Synopsys's Behavioral
Compiler and High Level Design System's RTL-level floor planner.  Others
speculate: "Because silicon is cheap, ASIC design is going to be replaced by
embedded controllers -- so we best start learning to use HW/SW co-design
tools like Mentor/Microtec's XRAY toolset or Hyperceptions's DSP-specific
RIDE tool.", while many of the hype driven EDA developers aren't thinking
specific tools as much as: "Hey, the Internet is hot! -- let's make JAVA
based EDA tools that we sell on Web pages!"   


BACK TO THE "REAL" WORLD: After 5 days in mercenary Las Vegas, I was quite
happy to get back home.  The lights and glitz are fun, but it's not reality.
After sleeping two days to recover, I knew I was back into my normal routine
when I had started writing an EE Times column about the attendance numbers
for the recent co-located IVC and VIUF conferences.  Apparently over 650
attended the pro-Verilog IVC while less than 225 attended the pro-VHDL VIUF.
(Nanette's going to scream bloody murder!)

                               - John Cooley
                                 part-time EDA industry gadfly
                                 full-time contract ASIC/FPGA designer

P.S. If you thought this review was on-the-money or out-to-lunch, please tell
me.  I love getting frank, honest feedback from fellow engineers.

P.P.S. In replying, *please* don't copy back this entire article; a 14,400
baud modem attached to a 386 on a sheep farm can handle only so much! :^)

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 4258 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."

Article: 6591
Subject: XILINX CONFIGUTATION CRCs
From: Cyril Muller <muller@polytechnique.fr>
Date: Wed, 04 Jun 1997 18:10:16 +0200
Links: << >>  << T >>  << A >>
I want to be able to modify a xilinx 4020E at will.
As the modifications are localised (always in the same CLB, and
i just want to change the function generators), the fastest way is
to change the bitstream.

It could change the ".lca", but it's too slow (it takes a lot
of time to recreate the bitstream and then send it to the FPGA).
(the main target is fast reconfiguration..., so i cant wait 30
seconds or more between 2 reconfigurations)

Here came my problems.

It's easy to locate the position of the tables coding the function
generators inside the bitstream.
BUT, i must calculate the "4 Error Check Bits" comming at the end
of each "data frame". (The DataBook says very few things on that)

THEN ?

Could you please send me details on
-how to make the 4 control bits
-what (and where) is inside the bitstream
for a XC4000E.

Thanks.
Article: 6592
Subject: Re: XILINX CONFIGUTATION CRCs
From: fliptron@netcom.com (Philip Freidin)
Date: Wed, 4 Jun 1997 17:05:07 GMT
Links: << >>  << T >>  << A >>

For dynamic changing of the bitstream as you describe, there are actually 
two possibilities.

1) Turn CRC off (an option in the makebits of your baseline bitstream)
   in which case, you only need to patch your function generator bits.
   You can see that the CRC field (last 4 bits of each frame) is the
   same 4 bit constant, and you dont need to change it in your modified
   bitstream (the code is 0110). You do need to run makebits with CRC 
   off, not just set all the fields to 0110, as this wont work. The 
   reason is that there is 1 more bit that needs to be flipped, to tell
   the chip that CRC is off. After this baseline bitstream is created,
   you can change it as much as you want, and the chip will eat it up
   and load it into the chip, no matter what the content. Be careful.

2) Modify the bitstream as you have suggested, and then modify the CRC
   field at the end of the frame. The way the CRC is calculated, requires 
   that ALL CRC fields starting at the one that is at the end of the
   first frame that you modify, and continuing to the last CRC field
   in the last frame (which is 11 bits long).

   If you want to do this method, may I recomend a review of patent
   5321704, which should be available from the excelent IBM patent
   server on the WWW.

Note: The CRC field provides a check of your storage media for the
bitstream (prom, eeprom, disk, RAM, core, notches on a stick ...) and
the mechanism by which you transmit the bitstream to the FPGA. In well
designed systems that have reliable storage, and well designed 
configuration hardware (failures are usually caused by poor signal 
integrity design) ,  CRC detected errors do not occur.

The CRC does not check that the bitstream is functionally correct, but
since the only way to create a base line bitstream is with makebits, and 
it performs a DRC on your design while creating the bitstream with CRC, 
you are pretty much guaranteed that the bitstream is ok. When you start 
playing with the bits, you are on your own. If you only change function 
generator bits, you are pretty safe. Start playing with bits that control 
routing and you can create designs with internal contention.

For your application I suspect that my first suggestion is what you 
should do.

Philip Freidin.



In article <33959368.167E@pam.devinci.fr> Cyril Muller <muller@polytechnique.fr> writes:
>I want to be able to modify a xilinx 4020E at will.
>As the modifications are localised (always in the same CLB, and
>i just want to change the function generators), the fastest way is
>to change the bitstream.
>
>It could change the ".lca", but it's too slow (it takes a lot
>of time to recreate the bitstream and then send it to the FPGA).
>(the main target is fast reconfiguration..., so i cant wait 30
>seconds or more between 2 reconfigurations)
>
>Here came my problems.
>
>It's easy to locate the position of the tables coding the function
>generators inside the bitstream.
>BUT, i must calculate the "4 Error Check Bits" comming at the end
>of each "data frame". (The DataBook says very few things on that)
>
>THEN ?
>
>Could you please send me details on
>-how to make the 4 control bits
>-what (and where) is inside the bitstream
>for a XC4000E.
>
>Thanks.


Article: 6593
Subject: The Advanced FPGA Design Demonstration at DAC
From: "Adam J. Elbirt" <aelbirt@viewlogic.com>
Date: Wed, 04 Jun 1997 13:33:50 -0400
Links: << >>  << T >>  << A >>
Viewlogic will be presenting the Advanced FPGA Design Demonstration at DAC.

The ADVANCED FPGA DESIGN demonstration highlights:
*** ViewSynthesis as a totally redone and highly optimized FPGA synthesis tool.  ViewSynthesis 
supports 100% Synopsys compatible VHDL language and has vendor specific optimizations for excellent 
use of resources and speed optimizations.  It's new GUI features one button use with preset vendor 
specific defaults, but still offers controls for advanced users.

*** IntelliFlow and ViewSynthesis in taking a mixed schematic and VHDL design from start all the way 
through place and route, final post-route timing simulation, and. creation of a PCB symbol and 
timing model.  The demonstrator will be able to select parts and run flows for Actel, Altera, 
Lattice, Lucent, Vantis, or Xilinx. 

*** The design being used contains a state machine and data path to highlight the various 
optimization capabilities of ViewSynthesis.  The design is created using ViewDraw for a top-level 
block diagram which instantiates four separate VHDL modules.

*** The demonstration shows that Viewlogic has integrated our FPGA tools along with the vendor place 
and route tools into an easy to use methodology (flow) without taking away any of the control from 
the designer.  It targets all FPGA designer, both infrequent users as well as the most advanced, 
since it uses default settings which will generally give the best results first time through, but 
gives the most experienced designers the ability to access every command switch in every tool for 
ultimate control.  The demonstration shows this control by setting different ViewSynthesis control 
settings for the four different VHDL modules in the design. 

Please stop by booth #1751 for a demonstration!

Thanks.

Adam J. Elbirt
Senior Programmable Solutions Engineer
Viewlogic Systems, Inc.
Article: 6594
Subject: Re: Memory workshop, San Jose
From: cecchi@signa.rchland.ibm.com (Del Cecchi)
Date: 4 Jun 1997 18:54:29 GMT
Links: << >>  << T >>  << A >>
In article <MJOHNSON.97Jun3205539@netcom12.netcom.com>, mjohnson@netcom12.netcom.com (Mark Johnson) writes:
|> Poor old Dick Foss.  He appears unwilling to admit that
|> SDRAMS (on which his company holds patents and from which
|> he hopes to profit) have lost the war.  Indeed the entire
|> 53-line abstract carefully avoids mentioning the winner: Rambus.
|> Not only does Foss make zero buxx from Rambus' complete and
|> total victory, he loses face because he backed the wrong horse:
|> first CTT, then SSTL, now DDR. So, with head firmly implanted in
|> sand, he goes around giving misguided talks about the superiority
|> of SDRAM while studiously neglecting to say that it's already lost.
|>  
|> Perhaps he'll even sic his lapdog (PdM) on me for pointing
|> out the bankruptcy of his abstract, and, one presumes,
|> the talk itself.  Watch for posts from mosaid.com and/or
|> Kanata, Ontario.
|> 
|> Mark Johnson
|> Silicon Valley, California

The aclaim for Rambus is by no means universal.  I guess that makes IBM a lapdog
for Dick Foss?  Just out of curiosity, what is the standby current of say, 10 GB
of RDRAM?.  

I don't see any of the server companies lining up behind Rambus, unless one
counts Intel as a server company.  And I haven't seen anything from them besides
an article in EETimes.  Do the new Pentium II chipsets use RDRAM? We're a little
isolated here, so clue us in.  What is the story out there in silicon valley?
-- 

Del Cecchi  
Frozen Tundra, Minnesota
Opinions mine all mine.

ps Who are you working for?  Or do you just have Rambus stock?  Mighty vitrolic
attack for a normally staid technical newsgroup.
Article: 6595
Subject: Re: Alternate Verilog FAQ : New release
From: knicks@cirrus.com (Ram Prabhakar)
Date: 4 Jun 1997 19:32:35 GMT
Links: << >>  << T >>  << A >>

Hi,

I was looking for a free copy of a vhdl-to-verilog translator. Does
anyone know of any such thing available on the net.

Pl. reply to my address knicks@corp.cirrus.com

Thanks

Article: 6596
Subject: Re: FPGA gate counting: No truth in advertising
From: Blair@QuickLogic.com
Date: Wed, 04 Jun 1997 14:02:36 -0600
Links: << >>  << T >>  << A >>
Let me see, you signed your name and your company and your domain and you
are in the MN phone book and you supplied your email address,  yep you
are correct you did supply that information.  I just wanted to clarify
your identity without users having to search for your name, company,
domain, email or the MN phone book in order to be aware of that
particular piece of un-obvious information. Now, if that is a personal
attack then you are a pretty sensitive kind of guy.

Regards,
Ben Blair
Manager Field Applications
QuickLogic Corporation

The above comments are my own and in no way express the views of
QuickLogic Corporation.  (Typical legal disclaimer) :^)


In article <19970531210528300253@1cust93.max1.minneapolis2.mn.ms.uu.net>,
  john@customer1st.com (John Sievert) wrote:
>
> Nothing hidden here!
>
> Let me see, I signed my name, my company name is in my domain name, both
> my name and my company's name are in the phone book,  and the POP I
> connected from is listed right in the email.  What's wrong with being
> the sales engineer here?  Aren't you a QL employee? Aren't we all
> involved in this industry?
>
> The issue isn't who works for who, but what's in the summary judgement -
> and therefore, who owns what. That isn't mud slinging, its a fact and
> now a matter of public record.   How is that mud slinging? What's your
> problem?
>
> If you've got something to say on this case, I'd be interested in
> hearing it.  This court case is complex, but interesting and worthy of
> discussion.  If you want to make personal attacks, I guess I'd consider
> that a waste of time.  But, if that's the image you want to project for
> you and your company, I guess that's your business.
>
> Regards
> John Sievert
> Customer 1st, Inc.
>
> <Blair@QuickLogic.com> wrote:
>
> > In article <19970526224329123272@cust4.max1.minneapolis.mn.ms.uu.net>,
> >   john@customer1st.com (John Sievert) wrote:
> > >
> > > Technology, which it appears, probably came from Actel (per summary
> > > judgement against QuickLogic on patent infringement.).
> > >
> > > <kevintsmith@compuserve.com> wrote:
> > >
> > > > In this case, it's not marketing hype, just superior
> > > > technology.
> > >
> > > --
> > > Regards,
> > > John Sievert
> >
> > Aren't you the Actel Manufacturers Rep in the MN area?
> >
> > It would behoove you to not sling mud and try to hide your identity.
> >
> > Regards,
> > Ben Blair
> > Manager Field Applications
> > QuickLogic Corporation
> >
> > -------------------==== Posted via Deja News ====-----------------------
> >       http://www.dejanews.com/     Search, Read, Post to Usenet
>
> --
> Regards,
> John Sievert

-------------------==== Posted via Deja News ====-----------------------
      http://www.dejanews.com/     Search, Read, Post to Usenet
Article: 6597
Subject: PCI how to
From: ivan@caseware.com (Ivan Hamer)
Date: Wed, 04 Jun 1997 20:53:04 GMT
Links: << >>  << T >>  << A >>

   I would like to make a simple PCI interface card that would allow
me to do some basic I/O with 'outside world'. I found quite some
information about the ISA interfaces,  but basically nothing usefull
about PCI. I would be very thankfull if someone could tell me how I
should approach this problem (point me to some resources on net, or
literature).

  Ivan Hamer (ivan.hamer@toronto.edu).
Article: 6598
Subject: Re: VHDL PCI FPGA Implementation
From: s_clubb@netcomuk.co.uk (Stuart Clubb)
Date: Wed, 04 Jun 1997 21:59:06 GMT
Links: << >>  << T >>  << A >>
So let me get this straight...

You had a working, fully compliant design before Xilinx even got off
the ground with their buggy, half speed interface. They were "in
negotiation" with you to purchase your design, yet decided that their
future customers would be much better served by an unproven, non
functional, non compliant product that needs a lot of hard work before
it is usable.

Naah. Doesn't sound like Xilinx's customer orientated approach to me!
;-)

>They (Xilinx) called me a while ago and asked if I would tell them how I
>did my design....and I told them that I was interested in telling them, but
>since they poopooed me on a few things over the years, I wasn't really
>happy with them....so we'll see if they pony up!

May you squeeze them 'till the pips squeek!

>Or use Austin's design ;-)

Surely that should read "Or buy Austin's design."? Or are you about to
become the ultimate PCI Philanthropist?

>Who'se at that address?

Altera.

Stuart
Article: 6599
Subject: Re: Altera Versus Xilinx
From: s_clubb@netcomuk.co.uk (Stuart Clubb)
Date: Wed, 04 Jun 1997 21:59:10 GMT
Links: << >>  << T >>  << A >>
On Tue, 3 Jun 1997 22:33:13 GMT, jhallen@world.std.com (Joseph H
Allen) wrote:

>Hey, don't have a cow man!  It's nothing that a few series resistors can't
>fix.  They have to be large enough so that the input impedance with the
>resistor would equal the reactance of a PCI single pin, but small enough so
>that outputs can still drive the bus with enough current (assuming any
>output pins are doubled up).  Around 10-27 ohms should work fine- make sure
>there's no ground plane under the resistor (to reduce capacitance).

And this has been characterised and proven compliant?

I'm not "having a cow" as you so eloquently put it. It just concerns
me that some engineers are reading, and swallowing, every piece of
"marketing" seen on a web site or pdf file.

Marketing joke:
A mathematician, an engineer, and an FPGA marketing VP are all asked
how much two plus two is.

The mathemetician says "It is exactly four point zero."
The engineer says "Four. Now can I have a pay rise?"
The FPGA marketing VP says: "What do you want it to be?"

Stuart


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