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Messages from 7900

Article: 7900
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Date: Tue, 28 Oct 1997 03:32:24 -0800
Links: << >>  << T >>  << A >>
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Article: 7901
Subject: Looking for FAE for Asia Pacific region
From: membarry@news.hk.super.net (Mr Barry Tso)
Date: 28 Oct 1997 13:10:55 GMT
Links: << >>  << T >>  << A >>
    We are looking for a Field Application Engineer in Xilinx Asia
Pacific based in Hong Kong.
The candidate should require:
    - good communication and presentation skills
    - fluent english and prefer mandarin
    - programmable logic or ASIC experience highly desirable
    - familiarity with CAE/CAD software and its use on PC/workstation
    - technical degree

    Xilinx offers a complete compensation package including a bonus
plan, profit sharing and stock options.  Send details of experience and
expected salary to Stacy Fender, Xilinx Asia Pacific, Unit 4312, Tower
2, Metroplaza, Hing Fong Road, Kwai Chung, N.T., Hong Kong. Fax:
852-2494-7159. Tel.: 852-2424-5200.  Email: stacy.fender@xilinx.com


Article: 7902
Subject: Modeling using Altera devices
From: Oliver WOOD <o.wood@mmu.ac.uk>
Date: Tue, 28 Oct 1997 13:25:16 +0000
Links: << >>  << T >>  << A >>
Has anyone tried to model a processor based structure on either a PLD or
FPGA altera device.  Please could you post any success/faliure stories.

Thanks in advance

Oliver J. Wood
Article: 7903
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From: ATTRACT WOMEN NOW<miker45@crmaen.net>
Date: 28 Oct 1997 16:06:11 GMT
Links: << >>  << T >>  << A >>
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Article: 7904
Subject: Info on Gatefield ???
From: ccwest@ix.netcom.com (Bill Seiler)
Date: Tue, 28 Oct 1997 18:13:20 GMT
Links: << >>  << T >>  << A >>
Anybody out there with experence with Gatefields GF2500F series.

I have a 30,000 gate Verilog design I would like to operate at 54 Mhz.

Can Gatefield do it?

How are the tools?

Thanks
Bill Seiler
Divx / Circuit City
3255-4 Scott Blvd, Suite 105
Santa Clara, CA 95054
408 982 5420 Direct
408 982 5430 FAX
ccwest@ix.netcom.com 

Article: 7905
Subject: Re: Counter Problem
From: tom_curran@memecdesign.com (tom curran)
Date: Tue, 28 Oct 1997 20:37:04 GMT
Links: << >>  << T >>  << A >>
If all you need from the counter is the terminal count, then use a
Linear Feedback Shift Register (LFSR).

My company has written a design guide -- and created a library -- for
using LFSRs in FPGAs.  You can get it for free at:

www.memecdesign.com/tr03010.htm

Hope it works for you...

tom


On 27 Oct 1997 20:42:14 GMT, winf176@ab200.rz.uni-karlsruhe.de
(Teilnehmer Informatik I) wrote:

>Hello!
>
>I'm implementing several counters in a Lattice ispLSI1016.
>For larger counters in a syncronous design, you need lots of ProductTerms.
>-> Split in many MacroCells. Grrrr.
>With an asyncronous counter on the other hand, you need 2 Macrocells
>(FlipFlop + Carry) per bit. Aaaaargh.
>What could I do to save resources???
>
>Thanks
>Armin
>
>
>

Article: 7906
Subject: Re: ORCA Foundry Back Annotation Quesiton
From: app01@aol.com (APP01)
Date: 29 Oct 1997 01:45:02 GMT
Links: << >>  << T >>  << A >>
As far as back annotation usually (especially for Period), the  timing should
 match. A few questions:

1. do you have all of the patches installed for 9.1 (i.e. patches a-f)?
They have also released orca foundry 9.1.5 which is the latest and you do not
 need to install any patches.
2. Does your sdf file look correct? For example are other delay numbers correct
 or is everything way off? Look into the sdf file and see if many of the
 entries are 0's.
3. What simulation tool are you using?  If there is any problem with the sdf
 file, the tool could be defaulting to default values.

I have created numerous Orca designs and have back annotated to vhdl and
 usually the timing is very close. One thing that I have found is that if there
 is as difference, the trace reports are usually more accurate.

Regards,

Tony

Article: 7907
Subject: Re: PROM for FLEX10K
From: Scott Bierly <sbierly@erols.com>
Date: Tue, 28 Oct 1997 20:53:56 -0500
Links: << >>  << T >>  << A >>
Has anyone successfully used a FLASH memory to configure Altera 10K parts?  I am
about to look into this, for the purpose of having non-volatile ISP in my product,
for field upgradeability.  On boards containing Xilinx, I believe that this will
work rather smoothly, as they have an inherent parallel programming mode that works
fine with EPROMs, so I just need a FLASH that emulates a conventional EPROM for
reading (although, I must somehow still provide write access to the local PCI
port).  Anyway, just seemed like a good thread to ask this question.  I would
appreciate copying any replies to sbierly@sed.stel.com, since I can't read this
group at work.

Thanks,
--Scott

Steve Dewey wrote:

> Let me be the first to flame :
>
> EPC1 is an EPROM supplied in OTP package. It is not an EEPROM, something
> many altera customers would like. It is not always convenient to use the
> byteblaster to programme Altera's FLEX 10K parts when prototyping.
>
> Some have suggested the atmel 17Cxxx serial EEPROMs, but these parts do not
> generate their own clock, which is essential for programming the FLEX 10K parts
> without additional external logic.
>
> Steve
>
> In article <HRe7ADAT76S0Iwh9@broadside.demon.co.uk>
>            david@broadside.demon.co.uk "David Atkins" writes:
>
> > Yup
> >
> > they have both 8 pin DIL and 28 pin PLCC,
> >
> > all in the data book, and I think its an EPC1, but don't quote me on
> > that
> >
> > In article <627peh$1vga@info4.rus.uni-stuttgart.de>, Andreas Wehr
> > <wehr@mikro.uni-stuttgart.de> writes
> > >
> > >Hi,
> > >
> > >can anybody tell me if there are serial EEPROMs available for
> > >ALTERA FLEX10K devices?
> > >
> > >Thanks,
> > >Andreas
> > >
> >
> > --
> > David Atkins
> >
>
> --
> Steve Dewey
> Steve@s-dewey.demon.co.uk
> Too boring to have an interesting or witty .sig file.



--
--------------------------------------------------------
-     Scott Bierly - sbierly@erols.com
--------------------------------------------------------


Article: 7908
Subject: Configuration of XC4000 FPGAs with JTAG
From: britta.becker@t-online.de (Rainer Becker)
Date: 29 Oct 1997 08:41:10 GMT
Links: << >>  << T >>  << A >>
All Xilinx XC4000 FPGAs support the JTAG standard and even
configuration is possible over the JTAG interface.

But Xilinx does not support this feature with their software,
only the XC9500 series is supported.

Is there any tool for configuring the XC4000 devices over
the JTAG interface?

Regards

Rainer

-- 

-----------------------------------------------------------------
Rainer Becker                                  rainer@pentatec.de
PentaTec GmbH                               Tel. +49 89 456918-21
Hermann-Oberth-Str. 18, 85640 Putzbrunn        Fax +49 89 6884310
Article: 7909
Subject: Re: Altera EPC1 and Chipmaster 6000
From: "Koichi Suzuki" <f3183694@ca.aif.or.jp>
Date: Wed, 29 Oct 1997 23:16:29 +0900
Links: << >>  << T >>  << A >>
 Hi Russ,

 I am using Chipmaster6000.
Configering FLEX10K100 on EPROM(27C2001) by PPA mode.
I strike a snag first time.Config was did not done.
I reserched that effect HEX file have problem.
Then the problem was sloved.
That way following.

 1. Open HEX file.
 2. Search for ":02000004xxxx??".(extention address recode)
 3. "xxxx" 4bit left shift.
     ex. 0001 -> 0010
 4. "??" is checksum.
     ex. :020000040010??
     100h - ( 02 + 00 + 00 + 04 + 00 + 10 ) = EA
     :020000040010EA
 5. Change all ":02000004xxxx??".
 6. File save.

I don't know which error MaxPlus2 or Chipmaster6000.
Please let me know effect.
Good luck.

from Tokyo Japan
f3183694@ca.aif.or.jp
Koichi Suzuki


Russell Magee wrote in article <6340eo$m00@nr1.calgary.istar.net>...

> Hi all,
>
>   We've hit a snag here at work, trying to program the Altera EPC1
configuration
>EPROM using the Chipmaster 6000 from Logical Devices Inc. Logical Devices
says they
>have verified the 6000 with the EPC1, but we can't seem to program any with
our unit
>(it always fails on verify pass).
>   Has anyone else experienced problems with the EPC1 part? We've heard
rumours
>(from another EPROM programmer maker) that Altera has somehow changed the
programming
>requirements of the EPC1 *without* changing the part number! If so, all I
can say is
>"$%@#!$!". We would have bought Altera's own programming unit, but the
delivery lead
>time was many weeks. Sigh..
>
>  Any advice appreciated,
>   -Russ Magee
>
>

Article: 7910
Subject: Programmable Logic News & Views
From: Murray <mdisman@ix.netcom.com>
Date: 29 Oct 1997 16:42:39 GMT
Links: << >>  << T >>  << A >>
The Programmable Logic News & Views Web site has been update with 
a summary of the August 1997 issue.

http://www.plnv.com

Murray Disman

Article: 7911
Subject: Polynomial division tool for LFSR/MISR simulation
From: Theodor Calin <calin@verdon.imag.fr>
Date: Wed, 29 Oct 1997 18:32:09 +0100
Links: << >>  << T >>  << A >>
Hi,

Does anybody know if there's any logic BIST simulation tool available
(free)
to perform polynomial division and simulate LFSR/MISR operation ? 

Which type of commercial CAD tools (besides BIST synhthesis) provide
such functions ?


I need to implement some polynomial division algorithms for test
patterns generated 
for ISCAS benckmarks. Could anybody suggest me some useful hints and
references for the
case I must do it myself ?

I would appreciate any help given. 

Regards,

Theodor Calin



------------------------------------------------------------------
Theodor Calin                                     +33 476 57 48 34
46, Av. Felix Viallet                      http://tima-cmp.imag.fr
38031 Grenoble                                calin@verdon.imag.fr
------------------------------------------------------------------
Article: 7912
Subject: Re: Internal tri-state emulation.
From: kopka@sbox.tu-graz.ac.DELETE.at (Reinhard Kopka)
Date: Wed, 29 Oct 1997 18:02:25 GMT
Links: << >>  << T >>  << A >>
On Mon, 27 Oct 1997 17:15:26 GMT, aquantz@ibm.net (Aaron Quantz)
wrote:

>>I wanted to translate my old design ( XC5202 ) to Altera Flex8282A.
>>When I completed and compile it, it can't fit into Flex8282ATC100.
>>Later, I find that the "Internal tri-state emulation" of the Altera
>>use up many resource (over 40 LE's). Is there any function(s) of the
>>compiler to solve this problem ? Xilinx's internal tri-state do not
>>consume any logic cell!
>I generally use muxes. The Altera parts don't have tri-state
>capability except at the I/O pins.

MaxPlus can convert TRIs from the design into MUXs. But that needs a
lot of place.

RK
For EMAIL remove DELETE from the adress !
Article: 7913
Subject: Re: design sites
From: lharold@mrc.uidaho.edu (Len Harold)
Date: 29 Oct 1997 19:32:04 GMT
Links: << >>  << T >>  << A >>
>Hello everyone,
>
>I would be very pleased if someone could send me interesting links to FPGA
>design sites, information besides the vendors of course. Thanks in advance,

My page at:

  <URL: http://www.mrc.uidaho.edu/fpga/ >
  
is probably somewhat useful.

Len
--
  ___     ___    ___  ________  ______
 /|  |   /\  \  /|  \|\   _   \/\   __\      Len Harold
| |  |   \ \   - |   \ \  \_\ /_ \  \_/
| |   \   \ \  \ _|\  \ \   _   \ \  \___    Phone: 208-885-7034
| |    \   \ \__\/\ \__\ \__\ \__\ \_____\   Fax:   208-885-6840
| |*    |   \/__/  \/__/\/__/\/__/\/_____/   Email: len@mrc.uidaho.edu
|/\     |/\                                  Web:   www.mrc.uidaho.edu
 \/        \_/\
 /|            |   Microelectronics Research
| |            |   and Communications Institute
| |____________|   at the University of Idaho
|/____________/
Article: 7914
Subject: Re: design sites
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Wed, 29 Oct 1997 12:43:07 -0800
Links: << >>  << T >>  << A >>
The Programmable Logic Jump Station at http://www.optimagic.com offers a
comprehensive resource for nearly all aspects of programmable logic.
Please visit the following links for more information.

Complete site map:  http://www.optimagic.com/sitemap.html
Major programmable logic news:  http://www.optimagic.com

Programmable logic companies:  http://www.optimagic.com/companies.html
Summary of available devices:  http://www.optimagic.com/summary.html
Market statistics and share of market:
http://www.optimagic.com/market.html

Free and low-cost development software:
http://www.optimagic.com/lowcost.html
Programmable logic development software:
http://www.optimagic.com/software.html
Synthesis and HDL tutorials:  http://www.optimagic.com/tutorials.html

Programmable logic boards:  http://www.optimagic.com/boards.html
Consultants for programmable logic:
http://www.optimagic.com/consultants.html
Programmable logic research:  http://www.optimagic.com/research.html
Relevant news groups:  http://www.optimagic.com/newsgroups.html
Relevant conferences:  http://www.optimagic.com/conferences.html
Relevant books:  http://www.optimagic.com/books.html
Information search resources:  http://www.optimagic.com/search.html

-----------------------------------------------------------------------
Steven K. Knapp                 'Great designs happen "OptiMagic"-ally'
OptiMagic, Inc.
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
 Phone:  1-408-454-1811



Thielemans - Van Heghe wrote in message
<01bce24c$440c9b40$380ceec3@login.skynet.be>...
|Hello everyone,
|
|I would be very pleased if someone could send me interesting links to
FPGA
|design sites, information besides the vendors of course. Thanks in
advance,
|
|Robbie


Article: 7915
Subject: Re: Polynomial division tool for LFSR/MISR simulation
From: "Kenneth Elmkjaer Larsen" <elmkjaer@post3.tele.dk>
Date: 29 Oct 1997 20:49:18 GMT
Links: << >>  << T >>  << A >>
Hi Theodor,
check Mentor's DFT tools.
/Kenneth

Theodor Calin <calin@verdon.imag.fr> skrev i artiklen
<34577319.DB6@verdon.imag.fr>...
> Hi,
> 
> Does anybody know if there's any logic BIST simulation tool available
> (free)
> to perform polynomial division and simulate LFSR/MISR operation ? 
> 
> Which type of commercial CAD tools (besides BIST synhthesis) provide
> such functions ?
> 
> 
> I need to implement some polynomial division algorithms for test
> patterns generated 
> for ISCAS benckmarks. Could anybody suggest me some useful hints and
> references for the
> case I must do it myself ?
> 
> I would appreciate any help given. 
> 
> Regards,
> 
> Theodor Calin
> 
> 
> 
> ------------------------------------------------------------------
> Theodor Calin                                     +33 476 57 48 34
> 46, Av. Felix Viallet                      http://tima-cmp.imag.fr
> 38031 Grenoble                                calin@verdon.imag.fr
> ------------------------------------------------------------------
> 
Article: 7916
Subject: Re: Modeling using Altera devices
From: "Mark Adams" <us017033@mindspring.com>
Date: Wed, 29 Oct 1997 17:47:56 -0800
Links: << >>  << T >>  << A >>
Oliver,
If by modeling a processor based structure you mean implementing a processor
(or processor like structure), yes I have. The first was in an 81500 , (long
story about part choice - determined by out of date tools at company).,
anyway, that design was a 10 MIP microcoded 16 bit processor and peripherals
used to implement a digital trap-drive motor controller (40khz voltage and
current loops with a 16 bit 4 quadrant multiplier, motor commutation, etc.).
My current processor (24 Bit) is more general purpose and significantly
faster (approx. 40 MIPS). I expect it to fit completely (including
registers) into approx. 1/2 - 2/3 of a 10K20. Should be interesting, as I am
considering implementing hardware supported data and program frame
management. BTW, the Altera parts (10Kxx) are a very good match for the
processor architecture I  am designing, also, I recently (last week)
purchased a constellation board from Nova engineering ( www.mova-eng.com )
with a 10K50V-3 on it for hardware modeling - nice board, good service, good
delivery, not too bad a price, all in all, a very positive experience.

                                               Mark A. Adams
                                               us017033@mindspring.com


Article: 7917
Subject: Re: Modeling using Altera devices
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Wed, 29 Oct 1997 19:46:03 -0800
Links: << >>  << T >>  << A >>
Yes, there have been numerous examples of successful processor
implementations in an FPGA.  Below are some specific links that may be
of interest:


Homebrewing RISC Microprocessors In FPGAs:
http://www3.sympatico.ca/jsgray/homebrew.htm


List of FPGA-based Computing Machines:
http://www.io.com/~guccione/HW_list.html


List of papers presented at FCCM'97:
http://www.fccm.org/prog.txt

Various FPGA Research including processors and reconfigurable computing:
http://www.optimagic.com/research.html

-----------------------------------------------------------------------
Steven K. Knapp                 'Great designs happen "OptiMagic"-ally'
OptiMagic, Inc.
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
 Phone:  1-408-454-1811




Oliver WOOD wrote in message <3455E7BC.67A7@mmu.ac.uk>...
|Has anyone tried to model a processor based structure on either a PLD
or
|FPGA altera device.  Please could you post any success/faliure stories.
|
|Thanks in advance
|
|Oliver J. Wood


Article: 7918
Subject: Help about ALTERA FPGA!!
From: Songsong <ss@zjumail.ml.org>
Date: Thu, 30 Oct 1997 21:46:31 +0800
Links: << >>  << T >>  << A >>
Hi, everyone:

I need your help.

I use ALTERA's FPGA to design a controller. The first time, I assign the
time for some pins, and fit successfully. But the pins are not
distributed as I wanted. When I assign the pins location, I found it
cann't fit or cann't get the specified time.

I want to compile a design at first, when it success, back_annonate the
design, but I find if I back_annonate the disign, I cann't modify the
pins and logic cells in Floorpan editor. I think it can work, I don't 
know the answer, who can tell me.

If you have used ALTERA's FPGA, please give me some advices.

Thanx

Songsong.
Article: 7919
Subject: VIUF Fall 1998 Call for Topics
From: Peter Ashenden <petera@ececs.uc.edu>
Date: Thu, 30 Oct 1997 09:15:20 -0500
Links: << >>  << T >>  << A >>
VIUF International Users' Forum (VIUF)
			      Fall 1998

			   CALL FOR TOPICS

		 "Idea Factory: VHDL for Power Users"


Over the past ten years, the EDA Industry has seen VHDL and some of
its satellite standards evolve from infancy to maturity.  The VHDL
International Users' Forum (VIUF) has contributed significantly toward
the introduction of VHDL and its companion standards to the user
community.  However, feedback from users has indicated that VIUF must
do more to address the needs of the "experienced" user.  In light of
this, the Steering Committee for VIUF Fall 1998 has chosen to devote
the majority of its focus to the needs of experienced users and the
practical, real-world applications of VHDL.  (Of course, we promise
not to forget the novice user in our plans, so don't worry if you're
just getting started using VHDL.)

The format of the Fall Forum is also changing, i.e., in addition to
providing a forum for instruction and presentation of the latest
information available concerning the practical application of VHDL,
the Steering Committee is working on a format for VIUF Fall 1998 that
will promote information interchange among the attendees.  We also
hope to offer you more, in a tangible sense, than just a copy fo the
"Proceedings" to take home with you.  However, in order to better meet
your needs, we need your help.  In short, we need to know which topics
related to VHDL and its companion standards are of the greatest
interest to you.

The VIUF Fall 1998 Steering Committee invites you to submit one or
more topics that are of interest to you and/or your colleagues.
Please send your suggestions to the Program Chair, Peter Ashenden, via
electronic mail to:

	petera@ececs.uc.edu

or by regular mail to:

	Peter Ashenden
	Dept ECECS, PO Box 210030
	University of Cincinnati
	Cincinnati, OH 45221-0030
	USA

	Phone: (513) 556 4756
	Fax:   (513) 556 7326

Submit your suggestions by no later than December 1, 1997.

Subsequent to receiving your suggestions, the official "Call for
Participation" will be distributed later this year.  This is your
forum, so please assist us in serving you better by offering your
suggestions.  Thanks in advance for your help.
Article: 7920
Subject: Pin compatible
From: membarry@news.hk.super.net (Mr Barry Tso)
Date: 30 Oct 1997 16:07:28 GMT
Links: << >>  << T >>  << A >>
May be the best substitute is the E part from Xilinx :>
They deliver better performance and lower cost.

Although Atmel claims they have pin compatible part, they 
can't have all the architecture feature from Xilinx.

Article: 7921
Subject: Re: Counter Problem
From: Tom Bowns <bowns@data-io.com>
Date: Thu, 30 Oct 1997 17:35:27 GMT
Links: << >>  << T >>  << A >>
Teilnehmer Informatik I wrote:
> 
> Hello!
> 
> I'm implementing several counters in a Lattice ispLSI1016.
> What could I do to save resources???

Two possibilities:

1) Look-ahead carry would be helpful for D flip-flops. Use a macrocell
here and there to "gather" carry information from previous counter
stages, to tell the next stage when to count. You use a few more
macrocells than actual counting bits, but it will stay within the GLB
p-term limits of the ispLSI1016.

2) Also, use the hard-XOR gates available on the registers in a GLB to
create a psuedo-toggle flop. In ABEL-HDL, this is done by specifying
discrete XOR equations and declaring those registers as "istype XOR". 

-TBB
Article: 7922
Subject: Re: [Reposted due to Enlow UCE cancel]: PROM for FLEX10K
From: gibson@innocon.com
Date: Thu, 30 Oct 1997 13:58:03 -0500
Links: << >>  << T >>  << A >>
Andy NEGOI wrote:
> 
> On 17 Oct 1997, Andreas Wehr wrote:
> 
> >
> > Hi,
> >
> > can anybody tell me if there are serial EEPROMs available for
> > ALTERA FLEX10K devices?
> >
> > Thanks,
> > Andreas
> >
> 
> Hi Andrea,
> 
> For FLEX 10k, the EPROM is called EPC1 (Altera reference).
> There are no EEPROMS. If you need a re-programmable solution for testing,
> you can use a Bitblaster download cable, that you can deconnect after the
> data has been transfered. This is what I'm using.
> 
> Andy Negoi
> 
We used one of the smaller 7000 series Altera parts in a socket that
controlled an EEPROM. New code is easily put into the EEPROM and a reset
to the 7000 part would reset the FLEX 10K and load it with the code.
Doug
Article: 7923
Subject: Re: Altera EPC1 and Chipmaster 6000
From: ying@soda.CSUA.Berkeley.EDU (Ying C.)
Date: 30 Oct 1997 21:17:19 GMT
Links: << >>  << T >>  << A >>


Russell,

What version of Max+plus II are you using to generate the pof file? I know
in in the newester version, 8.1, the default POF file generated for 10k10,
10k20 and 10k30 is for EPC1441, not EPC1. You have to perform combine
programming file to covert it to EPC1 format. Perhaps that is your
problem?

Ying
ying@csua.berkeley.edu

In article <6340eo$m00@nr1.calgary.istar.net>,
Russell Magee  <bigruss@cheetah.spots.ab.ca> wrote:
> Hi all,
>
>   We've hit a snag here at work, trying to program the Altera EPC1 configuration
>EPROM using the Chipmaster 6000 from Logical Devices Inc. Logical Devices says they
>have verified the 6000 with the EPC1, but we can't seem to program any with our unit
>(it always fails on verify pass).
>   Has anyone else experienced problems with the EPC1 part? We've heard rumours
>(from another EPROM programmer maker) that Altera has somehow changed the programming
>requirements of the EPC1 *without* changing the part number! If so, all I can say is
>"$%@#!$!". We would have bought Altera's own programming unit, but the delivery lead
>time was many weeks. Sigh..
>
>  Any advice appreciated,
>   -Russ Magee
>
>


-- 
-----------------------------------
http://www.csua.berkeley.edu/~ying
Article: 7924
Subject: Re: Pin compatible
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Thu, 30 Oct 1997 16:52:16 -0500
Links: << >>  << T >>  << A >>
Mr Barry Tso wrote:
> 
> May be the best substitute is the E part from Xilinx :>
> They deliver better performance and lower cost.
> 
> Although Atmel claims they have pin compatible part, they
> can't have all the architecture feature from Xilinx.

The Atmel AT40K is pin compatible in that it can be used in a Xilinx
socket (dedicated pin assignments are the same, xilinx configuration
modes and protocol are supported).  The internal architecture is quite
different however.  Which part is the better one really depends on the
application.  Atmel's pricing is very aggressive (I think it is about
$40 for a 20K gate part in small quantities) so it is worth a look,
especially in cost sensitive projects.

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


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