Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 8025

Article: 8025
Subject: Re: scsi host adapter
From: Steve Goodwin <steve@p2cl_DSPM.demon.co.uk>
Date: Sat, 8 Nov 1997 17:09:38 +0000
Links: << >>  << T >>  << A >>
In article <EJB0yA.CDD@iglou.com>, Hul Tytus <htytus@iglou1.iglou.com>
writes
>
>       Anyone know of a SCSI-1 host adapter for the PC ISA buss for which a 
>listing of the control & data ports and their functions is available? This 
>would seem a simple quest but the opposite appears true. 

I too had difficulty finding information on SCSI adaptors. I had a look
at the Linux source listings which do contain the kind of information
you need but are not really structured in a way that makes it easy to
get at. Maybe you could see if the Adaptec 1505 or 1510 have drivers
within Linux.

In the end I used the ASPI interface as my unit ran under DOS and that
has helped with multi sourcing 'cos every adaptor you can buy has an
ASPI driver. Whether its an appropriate copurse for you is obviously
another matter.

Good luck anyway and I'd be interested in anything you did find.

Regards
-- 
Steve Goodwin...  De-spamming active, remove any _DSPM from address
Article: 8026
Subject: ALPHA AXP architecture
From: "Steven(Xunhua) Wang" <xwang@cs.uwm.edu>
Date: Sat, 8 Nov 1997 14:54:39 -0600
Links: << >>  << T >>  << A >>
Who has some electronic materials about the lastest development of the
Digital's Alpha AXP?

Please give replies to my own email box.   Thanks!

Article: 8027
Subject: Re: Division using FPGAs
From: "Prof. Vitit Kantabutra" <vkantabu@computer.org>
Date: Sat, 08 Nov 1997 21:01:13 -0700
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> 
> Reetinder P. S. Sidhu wrote:
> >
> > Hi all
> >
> >         Could anyone provide info on design techniques used to
> > implement arithmetic division on FPGAs (both LUT and sea-of-gates)?
> >
> >         Thanks in advance.
> 
> Division is not trivial as you've probably realized by now.  .....



Would you like to try a new, simple, high-radix approach?  There's no
charge for non-profit use.  I came up with new, comparator-based
high-radix division algorithms, which can be read at
http://math.isu.edu/~vkantabu/radix8.pdf

If anyone implements any of these algorithms, I'd love to know the delay
& area data.
Article: 8028
Subject: FPGA basics please ?
From: Adam Seychell <aseychell@cybec.com.au>
Date: Mon, 10 Nov 1997 01:52:05 +1100
Links: << >>  << T >>  << A >>
Ok, as great as the internet is with information, I couldn't find any
online documentation, (or PDFs) that would answer me with basic
questions to start me off on learning about this great technology.

  Are FPGAs re-porgrammable ?

  If so is there a limit to the number programming ?

  Where does the word "field" come from in FPGA ?

I've heard of people using programmable logic devices for building
hardware that has the capability to be reconfigured at any time. Would
this be FPGA ?
Does this implementation have a name ?

Obviously I am a beginner to programmable logic. Over the last few
weeks of looking at whets around I see its a huge and growing
industry. For some reason  FPGAs seem to be most popular over other
technologies.

Adam


Article: 8029
Subject: Heed converter
From: "Victor Levandovsky" <vic@alpha.podol.khmelnitskiy.ua>
Date: 9 Nov 1997 15:48:29 GMT
Links: << >>  << T >>  << A >>

I`m looking for a converter
which may transform *.pds or *.jed -files (PLDasm/ ALTERA`s PLDShell Plus)
to  *.tdf - files (MAX+PLUS II)

vic@alpha.podol.khmelnitskiy.ua
-- 
Victor Levandovsky
Technological University of Podolia
Khmelnitsky, Ukraine
Article: 8030
Subject: Altera FLEX 10K10 prototype board
From: kkibbe@golden.net (Kevin Kibbe)
Date: Sun, 09 Nov 1997 17:48:49 GMT
Links: << >>  << T >>  << A >>
Little offer here for people who do not have access to the Altera
program but would like to use one for a project.
 
I have a proto type board that has an Altera FLEX 10K10 on it. This is
a Programmable logic device with 134 input/output pins and 10,000
logic gates. I have designed the PCB to use the surface mount version
of this chip and the board is 2.5" by 4". The board brings all the I/O
pins to wire wrap connectors on a 0.1" grid. The board has a socket to
plug the 10K10's programming PROM. (this configures the device).
 
What I am offering is the chip/board fully wired. You supply the
schematic I will program the PROM. The way the programming software
works is that you must have a key.(The software is very expensive)
This chip is very powerful, just about any logic you could think of
you can put into this chip. Just about any type of 74 series chip for
example.
 
I will provide the boards/ chips at my cost. I will program the chips
to your specification for ~$30. (Note this is not design just entering
the schematic and a basic test. If you want more we can talk about
it.) I feel that I can provide the board and chip for about $55. If a
change in your schematic is required I will do the change and send you
a new EPROM for ~$20. 
 
This is a for sale type post but I think that anyone can see it's not
a money making venture to say the least. I just want the experience
and some of you could benefit as well. If you don't see it that well
please forgive the intrusion.
 
Anyway if this is of any use to you please email me at
kkibbe@golden.com 
Article: 8031
Subject: FCCM'98 Call For Papers
From: jmarnold@potomac.znet.com (Jeffrey M. Arnold)
Date: 9 Nov 1997 13:48:11 -0800
Links: << >>  << T >>  << A >>
                     C A L L    F O R    P A P E R S

			   THE SIXTH ANNUAL
		 IEEE SYMPOSIUM ON FIELD PROGRAMMABLE
		      CUSTOM COMPUTING MACHINES
			   Napa, California
			  April 15-17, 1998

			 http://www.fccm.org


PURPOSE: To bring together researchers to present recent work in the
use of reconfigurable logic as computing elements.  This symposium
will focus primarily on the current opportunities and problems in this
new and evolving technology for computing.  Contributions are
solicited on all aspects of custom computing, including but not
limited to:

Architecture of reconfigurable computing devices and systems,
including coprocessors, attached processors, and hybrids.

Languages, compilation techniques, tools, and environments for
programming and run time support;

Application domains;

Prototyping for architecture emulation.

SUBMISSIONS: Authors are invited to send submissions for either full
length papers (10 page maximum) or extended abstracts (2 page maximum)
for posters by January 5, 1998, to Jeffrey Arnold.  Notification of
acceptance will be sent in early March.  Final papers will be due on
the first day of the Symposium. The proceedings will be published
following the Symposium.

Authors are encouraged to submit PostScript, Microsoft Word, or
FrameMaker manuscripts by FTP.  For instruction on electronic
submission, please see the Web page or contact Jeffrey Arnold
(jmarnold@znet.com).

SPONSORSHIP: The IEEE Computer Society and the Technical Committee on
Computer Architecture.

CO-CHAIRS:
Kenneth L. Pocek
Intel
Mail Stop RN6-18
2200 Mission College Boulevard
Santa Clara, California  95052
Voice: 408-765-6705  Fax: 408-765-5165
kenneth_pocek@ccm11.sc.intel.com

Jeffrey M. Arnold
10686 Mira Lago Terrace
San Diego, CA 92131
Voice: 619-547-9257  Fax: 619-547-9010
jmarnold@znet.com


PROGRAM COMMITTEE:
Peter Athanas, Virginia Tech.
Donald Bouldin, University of Tennessee, Knoxville
Duncan Buell, Center for Computing Sciences
Michael Butts, Quickturn Design Systems, Inc.
Steve Casselman, Virtual Computer Corp.
Pak Chan, Univ. California, Santa Cruz			
Apostolos Dollas,  Technical Univ. of Crete		
Scott Hauck, Northwestern Univ.
Brad Hutchings, Brigham Young Univ.
Tom Kean, Xilinx, Inc. (U.K). 
Phil Kuekes, HP Labs.
Wayne Luk, Imperial College
John McHenry, NSA
Robert Parker, Institute for Information Sciences
Herman Schmit, Carnegie Mellon University
Mark Shand, Digital Equipment (Paris)
Satnam Singh, Univ. of Glasgow
Stephen Smith, Altera Corp.

-- 
Jeffrey M. Arnold		jma@super.org or jmarnold@znet.com
10686 Mira Lago Terrace		Tel: 619-547-9257
San Diego, CA 92131		Fax: 619-547-9010
USA
Article: 8032
Subject: Re: Anyone using Protel Schematic 3 for XILINX?
From: z80@ds.com (Peter)
Date: Mon, 10 Nov 1997 08:51:52 GMT
Links: << >>  << T >>  << A >>

>Protel has not yet discovered what hierarchy means.  Multiple instantiations
>of a single library part means ridiculous workarounds.  Until that's fixed,
>I won't touch it for FPGA work.

Can you give more detail? What happens if one does it? Of course, this
should work.

Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiXYZserve.com but
remove the XYZ.
Article: 8033
Subject: Get YOUR free pager, or get PAID to give them away!!!
From: spamfree.usa1@gov.abuse.net
Date: Mon, 10 Nov 1997 01:05:35 PST
Links: << >>  << T >>  << A >>
It's time to get YOUR free pager.
It's as simple as calling the number below!!
NO YEAR CONTRACTS, all service is month-to-month.
YOUR CHOICE OF COLORS!!
These are NEW MOTOROLA PAGERS.
NO GIMMICKS, JUST CALL THE NUMBER BELOW
AND GIVE THEM THE FOLLOWING ACCESS #.

CALL:  (800) 784-6452
ACCESS#:  4095038

Ask how YOU can get paid to give away
free pagers!!!!
Article: 8034
Subject: Re: FPGA basics please ?
From: Alan Donovan <adonovan@eu.fore.com>
Date: Mon, 10 Nov 1997 10:03:11 +0000
Links: << >>  << T >>  << A >>
Adam Seychell wrote:
> 
> Ok, as great as the internet is with information, I couldn't find any
> online documentation, (or PDFs) that would answer me with basic
> questions to start me off on learning about this great technology.
> 
>   Are FPGAs re-porgrammable ?
> 
>   If so is there a limit to the number programming ?
> 
>   Where does the word "field" come from in FPGA ?
> 

The answers are Yes, No, As in "in the field".

Field Programmable Gate Arrays can be reprogrammed, in the field (ie
where your end user is), a large number of times (there may be a limit
but I don't know it). Some models can even be reprogrammed while
running.

alan

-----------------------------------------------------------------------
 Alan Donovan, FORE Audio & Video, 14 Regent Street, Cambridge CB2 1DB
 Tel: +44 1223 518325     adonovan@eu.fore.com     http://www.fore.com 
-----------------------------------------------------------------------
Article: 8035
Subject: Re: FPGA basics please ?
From: dstewart@REMOVE.THIS.dmicros.com (Derek Stewart)
Date: Mon, 10 Nov 1997 14:03:01 GMT
Links: << >>  << T >>  << A >>
On Mon, 10 Nov 1997 10:03:11 +0000, Alan Donovan
<adonovan@eu.fore.com> wrote:

>Adam Seychell wrote:
>> 
>> Ok, as great as the internet is with information, I couldn't find any
>> online documentation, (or PDFs) that would answer me with basic
>> questions to start me off on learning about this great technology.
>> 
>>   Are FPGAs re-porgrammable ?
>> 
>>   If so is there a limit to the number programming ?
>> 
>>   Where does the word "field" come from in FPGA ?
>> 
>
>The answers are Yes, No, As in "in the field".
>
>Field Programmable Gate Arrays can be reprogrammed, in the field (ie
>where your end user is), a large number of times (there may be a limit
>but I don't know it). Some models can even be reprogrammed while
>running.
>
>alan
>
>-----------------------------------------------------------------------
> Alan Donovan, FORE Audio & Video, 14 Regent Street, Cambridge CB2 1DB
> Tel: +44 1223 518325     adonovan@eu.fore.com     http://www.fore.com 
>-----------------------------------------------------------------------
Not all FPGAs are re-programmable, e.g. ACTEL;  which use antifuse
technology rather than SRAM.  This means that they are not
reprogrammable "in the field",  although they are still called FPGAs.
This can have its advantages where reprogrammability is not a
requirement (i.e. cheaper/more reliable/instant operation from
boot-up).
The number of re-programming cycles depends on the device.  It can be
anything from a couple of hundred to tens of thousands of times.
The best way to get basic information is to get some data books from
the manufacturers,  and have a look at them.  If your familiar with
PLDs,  then FPGAs shouldn't be much of a problem.

Derek
Article: 8036
Subject: Re: ABEL HDL state machine question
From: Tom Bowns <bowns@data-io.com>
Date: Mon, 10 Nov 1997 15:17:02 GMT
Links: << >>  << T >>  << A >>
Austin Franklin wrote:
> 
> Why not just declare ifoobar (for internal foobar) and foobar...
> so you only need to set foobar to 1 in state 3
> 
> Marc Heuler <marc@aargh.mayn.de> wrote in article
> <TbclB*xte@aargh.mayn.de>...
> > I'm defining a state machine in ABEL HDL.
> >
> > Some nodes are LOW only during 1 state of 16.... 
> > This is very tiring and invites to forget it once...


Another suggestion would be to leave the assertion of foobar out of the
state machine section entirely, and put it in the equations section.
Thus:


equations

	foobar = (StateMachineRegs != 3);


This causes foobar to be 1 whenever the state machine is in any state
other than 3. With no driving logic, the output will go to zero.

-TBB
Article: 8037
Subject: Re: FPGA basics please ?
From: Jason.Wright@ebu.ericsson.com (Jason T. Wright)
Date: Mon, 10 Nov 1997 17:11:54 GMT
Links: << >>  << T >>  << A >>
On Mon, 10 Nov 1997 10:03:11 +0000, Alan Donovan
<adonovan@eu.fore.com> wrote:

>Adam Seychell wrote:
>> 
>> Ok, as great as the internet is with information, I couldn't find any
>> online documentation, (or PDFs) that would answer me with basic
>> questions to start me off on learning about this great technology.
>> 
>>   Are FPGAs re-porgrammable ?
>> 
>>   If so is there a limit to the number programming ?
>> 
>>   Where does the word "field" come from in FPGA ?
>> 
>
>The answers are Yes, No, As in "in the field".
>
 The answers are "It depends."  Some FPGAs are re-programmable, some
are not -- i.e., Actel's.  Some are RAM-based, so have "inifinite"
re-programmability.  Some are based on Flash or EEPROM-technology
based, so can be programmed "lots and lots"--probably more than anyone
would care.

Jason

>Field Programmable Gate Arrays can be reprogrammed, in the field (ie
>where your end user is), a large number of times (there may be a limit
>but I don't know it). Some models can even be reprogrammed while
>running.
>
>alan
>
>-----------------------------------------------------------------------
> Alan Donovan, FORE Audio & Video, 14 Regent Street, Cambridge CB2 1DB
> Tel: +44 1223 518325     adonovan@eu.fore.com     http://www.fore.com 
>-----------------------------------------------------------------------

Article: 8038
Subject: Re: FPGA basics please ?
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Mon, 10 Nov 1997 09:52:52 -0800
Links: << >>  << T >>  << A >>

Adam Seychell wrote in message <3465CE15.E8ADFCA8@cybec.com.au>...
>Ok, as great as the internet is with information, I couldn't find any
>online documentation, (or PDFs) that would answer me with basic
>questions to start me off on learning about this great technology.
>
>  Are FPGAs re-porgrammable ?

Some FPGAs are re-programmable, namely those built using SRAM technology and
those using FLASH memory technology.  There is another technology called
anti-fuse that is used in some FPGA devices.  It can only be programmed once
but has some advantages for design security.

See http://www.optimagic.com/faq.html#Memory_Technology for additional
information.
>
>  If so is there a limit to the number programming ?

For SRAM-based parts, there is no limit to the number of programming cycles
as there is no know wear-out mechanism for SRAM technology.  FLASH-based
devices do have a maximum rating which varies from one vendor to another.
>
>  Where does the word "field" come from in FPGA ?

Good question.  I think it hails back to the days of 'field programmable
logic arrays'.  My guess is that 'field' means that it can be programmed in
the field and does not have to be programmed in the factory.
>
>I've heard of people using programmable logic devices for building
>hardware that has the capability to be reconfigured at any time. Would
>this be FPGA ?

Most probably they are referring to SRAM-based FPGAs.  They may also be
referring to FLASH- or EEPROM-based FPGAs or CPLD devices.

>Does this implementation have a name ?

Some more generic names include 'reconfigurable computing' (RC),
configurable computing, reconfigurable hardware.  If you are interested in
this technology, take a look at the following pages:

http://www.netcom.com/~optmagic/reconfigure

http://www.optimagic.com/research.html
http://www.optimagic.com/boards.html


>
>Obviously I am a beginner to programmable logic. Over the last few
>weeks of looking at whets around I see its a huge and growing
>industry. For some reason  FPGAs seem to be most popular over other
>technologies.
>
>Adam
>
>

You may be interested in our site as it contains a fairly comprehensive set
of links related to programmable logic.  You can find The Programmable Logic
Jump Station at http://www.optimagic.com.

-- Steve Knapp


Article: 8039
Subject: Re: FPGA basics please ?
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Mon, 10 Nov 1997 13:50:30 -0500
Links: << >>  << T >>  << A >>
Alan Donovan wrote:
> 
> Adam Seychell wrote:
> >
> > Ok, as great as the internet is with information, I couldn't find any
> > online documentation, (or PDFs) that would answer me with basic
> > questions to start me off on learning about this great technology.
> >
> >   Are FPGAs re-porgrammable ?
> >
> >   If so is there a limit to the number programming ?
> >
> >   Where does the word "field" come from in FPGA ?
> >
> 
> The answers are Yes, No, As in "in the field".
> 
> Field Programmable Gate Arrays can be reprogrammed, in the field (ie
> where your end user is), a large number of times (there may be a limit
> but I don't know it). Some models can even be reprogrammed while
> running.
> 
> alan
> 

More accurately depends, depends, like he said.

SRAM based FPGAs (Xilinx 3K,4K,5K,6K;Atmel 6K,40K;Altera 10K etc) are
infinitely reprogrammable and must be reloaded after power is cycled. 
In these cases the FPGA configuration is stored in volatile registers
int he device.  Some of these devices also accept partial reprogramming
so that a portion of the circuit remains while the rest is replaced.

Other devices use different technologies for storing the device
configuration.  Actel and Quicklogic use antifuses which can be
programmed only once.  While these are a throwaway device if the
programming needs to be changed, there is also no need for programming
circuitry on your board.

Still others use EEPROM technology which allow the device to be
reprogrammed.  In this case the program is non-volatile, but there is
typically a limit on the number of program / erase cycles that can be
done.

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka
Article: 8040
Subject: Re: Division using FPGAs
From: "John L. Smith" <jsmith@univision.com>
Date: Mon, 10 Nov 1997 14:10:57 -0500
Links: << >>  << T >>  << A >>
> Reetinder P. S. Sidhu wrote:
> >
> > Hi all
> >
> >         Could anyone provide info on design techniques used to
> > implement arithmetic division on FPGAs (both LUT and sea-of-gates)?
> >
> >         Thanks in advance.
> >
> >                                                 Reetinder Sidhu

Simple long division, as taught in grade school, can be implemented
in Xilinx 4000 series FPGAs in a simple manner. The high speed
carry logic of the part is configured to perform the subtractions
at each stage, and the carry out is used to control multiplexors
which provide either the difference (if positive), or the subtrahend(?)
(if difference is negative). The muxes are configured into the LUTs
associated w/ the carry logic. The operations can be pipelined
for maximum speed. This may not be the most area-efficient way to
go, but is probably the easiest to design and get running.

Don Husby has posted on this previously, you may want to
search the archives.
Article: 8041
Subject: switching between clock domains in Xilinx FPGA's
From: Arrigo Benedetti <arrigo@vision.caltech.edu>
Date: 10 Nov 1997 14:23:20 -0800
Links: << >>  << T >>  << A >>
Dear all,

a while ago an FPGA designer told me that Xilinx does not guarantee
any minimum skew between clock signals from different clock sources.
This means that if I have two clock signals ck_1, ck_2 with a duty
cycle of 50%, frequency f_1, f_2 = 2*f_1 and little skew (say 1-2 ns)
at the FPGA input pins, there is no gurantee that the skew remains the
same due to inpredictable delays in the internal clock distribution
network. For this reason I can't exchange data between different clock
domains by simply connecting the output of a register clocked by ck_1
to, say, the input of a register clocked by ck_2. I did not find any
guidelines for dealing with this problem, so I would like to know how
these isses are usually handled by the experts.

thanks in advance

-Arrigo Benedetti
Article: 8042
Subject: Re: switching between clock domains in Xilinx FPGA's
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Mon, 10 Nov 1997 15:29:55 -0800
Links: << >>  << T >>  << A >>
You might be interested in the following Adobe Acrobat document available on
the Xilinx web site.  I believe that it directly addresses the problem that
you posed.

Trouble-Free Switching Between Clocks
http://www.xilinx.com/xcell/xl24/xl24_20.pdf


-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

Arrigo Benedetti wrote in message ...
>Dear all,
>
>a while ago an FPGA designer told me that Xilinx does not guarantee
>any minimum skew between clock signals from different clock sources.
>This means that if I have two clock signals ck_1, ck_2 with a duty
>cycle of 50%, frequency f_1, f_2 = 2*f_1 and little skew (say 1-2 ns)
>at the FPGA input pins, there is no gurantee that the skew remains the
>same due to inpredictable delays in the internal clock distribution
>network. For this reason I can't exchange data between different clock
>domains by simply connecting the output of a register clocked by ck_1
>to, say, the input of a register clocked by ck_2. I did not find any
>guidelines for dealing with this problem, so I would like to know how
>these isses are usually handled by the experts.
>
>thanks in advance
>
>-Arrigo Benedetti


Article: 8043
Subject: Re: Where can I find documents talking about constraining FPGA?
From: gcanderson@aol.com (Gcanderson)
Date: 11 Nov 1997 02:15:05 GMT
Links: << >>  << T >>  << A >>
Jack

Following is from Xilinx's online documentation in the M1 Design tools.  It is
 an example and definition of a UCF(User Constraint File).

Gus Anderson
Field Applications Engineer
Nu Horizons
305 710 6894


CPLD Attributes Used in a User Constraint File (UCF)

Copyright © 1984÷1997  ALDEC, Inc.


·	INST inst_name BUFG=CLK|OE|SR; on an IBUF symbol. 
or
NET net_name BUFG=CLK|OE|SR; on an input pad net.
(Assigns global buffers to input pins in top-level design.)

·	INST inst_name COLLAPSE; on a logic symbol.
or 
NET net_name COLLAPSE; on a logic net.
(Forces a logic mode to be collapsed into all of its fanouts.)

·	INST inst_name FAST | SLOW; on an OBUF, OBUFE or OBUFT type symbol. 
or
NET net_name FAST | SLOW; on an output pad net.
(Selects output slew rate for output pins in top-level design.)

·	INST inst_name INIT=R|S; on a flip-flop or other registered macro
 symbol. 
or
NET net_name INIT=R|S; on the output net of a flip-flop or other registered
 macro symbol. 
(Defines initial state of registers.)

·	INST inst_name KEEP; on a logic symbol. 
or
NET net_name KEEP; on a logic net.
(Preserves internal nodes during design implementation.)

·	NET net_name LOC=Ppin_number|BGA_pin_name; [eg. NET ABC LOC=P23; or NET
 XYZ LOC=AC17;] on any pad net.
(Assigns a device pin number to an input or output pad of the design.)

·	INST inst_name LOC=FBnn; [eg. INST U3 LOC=FB3;] on a logic symbol.
or
NET net_name LOC=FBnn; on a logic net or an output pad net.
(Assigns an internal Function Block number to logic driving an internal node or
 device output; typically used only to control XC9500 local feedback routing.)

·	INST inst_name NOREDUCE; on a logic symbol.
or
NET net_name NOREDUCE; on a logic net.
(Preserves redundant logic terms during design implementation.)

·	NET net_name OFFSET=IN:delay:BEFORE:clock_net_name; on an input pad
 net.
(Defines an input pad setup time constraint before the active edge of the named
 clock input pad.)

·	NET net_name OFFSET=OUT:delay:AFTER:clock_net_name; on an output pad
 net.
(Defines a clock-pad-to-output-pad propagation delay timing constraint.)

·	INST inst_name PWR_MODE=LOW|STD; on a logic symbol.
or
NET net_name PWR_MODE=LOW|STD; on a logic net. 
(Selects macrocell power mode for nodes or outputs in CPLD designs.)

·	INST inst_name TNM=group_name; [eg. INST FLOP1 TNM=MY_GROUP1;] on any
 flip-flop symbol. 
or
NET net_name TNM=group_name; on any logic net or pad net.
(Tags signals with a Timing-group Name to be used in a Timespec.)

·	TIMESPEC TSnn=FROM:source_group:TO:dest_group:delay; [eg. TIMESPEC
 TS02=FROM:PADS(IBUS*):TO:MY_GROUP1:16;].
(Defines a point-to-point timing constraint.)

·	TIMESPEC TSnn=PERIOD:clock_group:delay; [eg. TIMESPEC
 TS10=PERIOD:CLK1_GRP:12;].
(Defines a clock period timing constraint.)

Note: The Foundation Project Manager automatically creates an empty template
 UCF file with the same name as your project and the fitter automatically reads
 it. You can add constraints to the UCF file by double-clicking its file name
 in the Project Manager’s window. 
  

Copyright © 1984÷1997  ALDEC, Inc.


Article: 8044
Subject: Re: switching between clock domains in Xilinx FPGA's
From: nospam@notime.nohow (Bob Perlman)
Date: Tue, 11 Nov 1997 05:05:46 GMT
Links: << >>  << T >>  << A >>
Hi - 

"Steven K. Knapp" <sknapp@optimagic.com> wrote:

>You might be interested in the following Adobe Acrobat document available on
>the Xilinx web site.  I believe that it directly addresses the problem that
>you posed.

>Trouble-Free Switching Between Clocks
>http://www.xilinx.com/xcell/xl24/xl24_20.pdf

I think that the circuit you've cited addresses a different question,
namely, how to safely multiplex between two clocks.  The original
poster was asking how to safely transfer data between logic domains,
one of whose clocks is an integral multiple of the other, when the
skew between the two clock trees inside the FPGA isn't well specified.
Good question.

I can suggest several techniques:

 - use only the N*f1 clock.  In the domain where you want to clock at
f1, use an enable that's active every N clocks.  With only one clock
tree, skew shouldn't be a problem.  Of course, power dissipation may
increase.  This is my favorite approach.

 - Ensure through your design that there's some minimum amount of
logic between the registers connecting the two domains.
Unfortunately, FPGA vendors do not specify minimum delays, and those
minimum delays get smaller all the time, as parts are migrated to
faster and faster processes.   But, you may be able to rationalize
that the clock trees, and thus the skews, are getting smaller and
smaller, too.  You'd have to be a sounder sleeper than I am, though.

 - Avoid using clock edges that are close to one another.  If, for
example, you are trying to transfer data from a 10MHz domain to a
20MHz domain, and the 10 and 20MHz rising edges are close to one
another, consider clocking the data into the 20MHz domain on the
falling edge of 20MHz, then reclocking it into another set of
registers on the 20MHz rising edge.  This works, but with some
drawbacks.  First, it chews up registers.  Second, you have less than
half a 20MHz clock in which to transfer data between domains, because
you're penalized by the potential skew between the two clocks, and by
the potential logic HIGH pulse shrinkage of the 20MHz clock (which
usually isn't well specified, either).  But it works, if you're
careful.

 - Ignore the whole issue and hope for the best.  In my experience
this is the most unsatisfactory solution but the also the most
popular.

[Aside: I had a chance to look at the article referred to, titled
"Trouble-Free Switching Between Clocks," and it looks pretty scary to
me.  Given a pair of clocks with an arbitrary phase relationship and a
clock select that's not synchronized to at least one of them, the
circuit appears to be Metastability Central.  Can someone explain how
this is supposed to work?  Or is "Trouble-Free" a typo for "Free
Trouble?"  Or maybe I'm missing the point, which has happened before.]

Bob Perlman
------
"Never wrestle with a pig: you both get dirty and the pig likes it."
To send me e-mail: my login ID is bobperl, my ISP is best.com.

Article: 8045
Subject: Re: FPGA basics please ?
From: Richard Schwarz <aps@associatedpro.com>
Date: Tue, 11 Nov 1997 07:29:52 -0500
Links: << >>  << T >>  << A >>
Check at http://www.associatedpro.com/aps for some great FPGA informatioon
and deals on low cost eda software.

Adam Seychell wrote:

> Ok, as great as the internet is with information, I couldn't find any
> online documentation, (or PDFs) that would answer me with basic
> questions to start me off on learning about this great technology.
>
>   Are FPGAs re-porgrammable ?
>
>   If so is there a limit to the number programming ?
>
>   Where does the word "field" come from in FPGA ?
>
> I've heard of people using programmable logic devices for building
> hardware that has the capability to be reconfigured at any time. Would
> this be FPGA ?
> Does this implementation have a name ?
>
> Obviously I am a beginner to programmable logic. Over the last few
> weeks of looking at whets around I see its a huge and growing
> industry. For some reason  FPGAs seem to be most popular over other
> technologies.
>
> Adam



Article: 8046
Subject: Re: switching between clock domains in Xilinx FPGA's
From: fliptron@netcom.com (Philip Freidin)
Date: Tue, 11 Nov 1997 18:30:39 GMT
Links: << >>  << T >>  << A >>
Philip Freidin comments on Bob Perlman's post about switching clocks:

In article <648phq$g6o$1@nntp2.ba.best.com> nospam@notime.nohow (Bob Perlman) writes:
>Hi - 
>
>"Steven K. Knapp" <sknapp@optimagic.com> wrote:
>
>>You might be interested in the following Adobe Acrobat document available on
>>the Xilinx web site.  I believe that it directly addresses the problem that
>>you posed.
>
>>Trouble-Free Switching Between Clocks
>>http://www.xilinx.com/xcell/xl24/xl24_20.pdf
>
>I think that the circuit you've cited addresses a different question,
>namely, how to safely multiplex between two clocks.  The original
>poster was asking how to safely transfer data between logic domains,
>one of whose clocks is an integral multiple of the other, when the
>skew between the two clock trees inside the FPGA isn't well specified.
>Good question.
>
>I can suggest several techniques:
>

Bob suggests several techniques, and comments on design practice in general.

>[Aside: I had a chance to look at the article referred to, titled
>"Trouble-Free Switching Between Clocks," and it looks pretty scary to
>me.  Given a pair of clocks with an arbitrary phase relationship and a
>clock select that's not synchronized to at least one of them, the
>circuit appears to be Metastability Central.  Can someone explain how
>this is supposed to work?  Or is "Trouble-Free" a typo for "Free
>Trouble?"  Or maybe I'm missing the point, which has happened before.]
>Bob Perlman

Bob has not missed the point. The Xilinx article is indeed JUNK, and 
should not be used for switching clocks, as it is indeed an example of
a design that can go metastable, and the results will be yeuchy.

For those of you who care, the article is titled:
"Trouble-Free Switching Between Clocks"
and was in the XCELL-24 magazine, Q1 1997
If you have the Xilinx AppLINX CD, there is a copy on it too.

Here is the scenario:
Assume that the select line is high, and clock B is therefore enabled.
Lets say that clock B is at 10MHz, and clock A is at 51.44MHz, with no phase 
relationship.

At the time of clock B falling, the select line goes low, violating the
setup/hold requirement of the lower flip flop. The flip flop goes
metastable and its output transitions low, and then returns high, after
maybe 10nS. Assuming that select remains low, it will transition more
permanently to a low level on the following falling edge of clock B, 90nS
later. While it was low for 10nS though, the gate feeding the upper flip
flop was supplying a high, and a falling edge of clock A came along. 
The upper flip flop would now be set also, and the following high on clock
A will be passed to the ouput, and will merge in an uncertain way with 
clock B. Real Junk.

Here's another failure mode:

Clock B at 66MHz (15.151nS cycle time). Setup changes async to clock B,
and the flip flop goes metastable. It goes low for 10nS, then returns
high. When it returns high, we are 2.424 nS into the clock high time of B,
and the and gate for B into the or gate is re-enabled. The result is a runt
clock high pulse of 5.151 nS. Obviously, for all possible metastability
recovery times, there is a range of runt widths from 0nS to just less than
the correct width. 

Here's another failure mode:

Select changes, disabling B, but the arrival of the B flip flop signal to 
enable the A flip flop is such that the async relationship with the A 
clock causes the A flip flop to go metastable, with the above runt clock 
problem as described above, but on the A side.

Here's three more failure modes:
Swap A and B in all of the above scenarios.


Bob did not miss the point, there was none. The design is JUNK.

Philip Freidin.

(I really hate when applications information from a vendor is just
patently wrong)

Article: 8047
Subject: Re: Heed converter
From: "John M. Moore" <jmoore@netgate.net>
Date: Tue, 11 Nov 1997 13:45:48 -0800
Links: << >>  << T >>  << A >>
Victor Levandovsky wrote:

> I`m looking for a converter
> which may transform *.pds or *.jed -files (PLDasm/ ALTERA`s PLDShell Plus)
> to  *.tdf - files (MAX+PLUS II)
>
> vic@alpha.podol.khmelnitskiy.ua
> --
> Victor Levandovsky
> Technological University of Podolia
> Khmelnitsky, Ukraine

Altera  provides (free of charge) a 'pla-to-tdf' program that will convert
the pla output of Abel to Altera's tdf format. I don't have a copy handy, but
I'm sure if you contact Altera, they'll point you to one. Might be on their
website as well.

Good luck.
-john

Article: 8048
Subject: Re: FPGA basics please ?
From: dthiele@ccmail.esd.ray.com
Date: Tue, 11 Nov 1997 17:02:35 -0600
Links: << >>  << T >>  << A >>
In article <3465CE15.E8ADFCA8@cybec.com.au>,
  Adam Seychell <aseychell@cybec.com.au> wrote:
>
> Ok, as great as the internet is with information, I couldn't find any
> online documentation, (or PDFs) that would answer me with basic
> questions to start me off on learning about this great technology.
>
>   Are FPGAs re-porgrammable ?
>
>   If so is there a limit to the number programming ?
>
>   Where does the word "field" come from in FPGA ?
>
> I've heard of people using programmable logic devices for building
> hardware that has the capability to be reconfigured at any time. Would
> this be FPGA ?
> Does this implementation have a name ?
>
> Obviously I am a beginner to programmable logic. Over the last few
> weeks of looking at whets around I see its a huge and growing
> industry. For some reason  FPGAs seem to be most popular over other
> technologies.
>
> Adam



Adam
Try the Xilinx web site (www.xilinx.com) they have a lot of info on FPGAs.
Deb

-------------------==== Posted via Deja News ====-----------------------
      http://www.dejanews.com/     Search, Read, Post to Usenet
Article: 8049
Subject: Re: Where can I find documents talking about constraining FPGA?
From: NgOsSmPiAtMh@passport.ca (Gregory Smith)
Date: Tue, 11 Nov 1997 23:42:46 GMT
Links: << >>  << T >>  << A >>
In article <01bceb68$efb9f940$fd4f27ca@jack.hinet.net>, "Jack Huang" <jacktch@tpts1.seed.net.tw> wrote:
>Hello,
>
>I'm now using Fundation design entry and M1implementation tools on XILINX
>XC4000 series. Where can I find any document talking about the keywords or
>parameters
>I can use in the UCF file?
>
>Jack
>
I went through the same thing, so I'm not being sarcastic:
Put the CD that says 'docs' in, install the browser software, and 
look through the table of contents. It's pretty easy to spot there.
Well, I have the Alliance stuff. I imagine the docs are in much
the same format though.


Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search