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Messages from 8450

Article: 8450
Subject: Xilinx Stock
From: "Sanford Hayes" <shayes@plainfield.bypass.com>
Date: Tue, 16 Dec 1997 00:49:50 -0500
Links: << >>  << T >>  << A >>
Anbody care to comment on why Xilinx stock has been dropping this year ?


Article: 8451
Subject: Re: bus design in Altera 10K, how to increase speed
From: "rk" <stellare@erols.com.NoSpammersAllowed>
Date: 16 Dec 1997 06:47:48 GMT
Links: << >>  << T >>  << A >>
Eric Pearson <ecp@focus-systems.on.ca> wrote in article
<EL9KCn.Dx6@focus-systems.on.ca>...
: In article <670s6d$jv7$1@news.netvision.net.il>,
: Alex Koegel <alex.koegel@dspis.co.il> wrote:
: >In article <3491bc91.80619134@news.walltech.com>,
: >   muzok@pacbell.net (muzo) wrote:


          <snip altera speed discussion>

hi guys,

i think it's interesting seeing how fast different fpga's will run
different types of circuits.  but, i think we'all (south of mason-dixon
line now, gotta use a bit of a southern accent) ought to quote temp and
voltage conditions as well as speed grades.

just a thought,

--------------------------------------------------------------
rk

"there's nothing like real data to screw up a great theory" 
- me (modified from original, slightly more colorful version)
--------------------------------------------------------------

p.s. actel a14100b-2, worst-case process, 4.75V, 70C => 116 MHz for 12
input 16-bit mux
                  -3 => 130 MHz

p.s.s. can somebody run this on the q-logic pasic3?  haven't downloaded
their s/w yet.
	
Article: 8452
Subject: Re: parallel counters: which device is suitable?
From: s_clubb@die.spammer.netcomuk.co.uk (Stuart Clubb)
Date: Tue, 16 Dec 1997 14:16:30 GMT
Links: << >>  << T >>  << A >>
On Mon, 15 Dec 1997 16:59:55 GMT, Michael.Schumacher@pamas.de (Michael
Schumacher) wrote:

>Hi everybody, we are currently thinking about a project where we need
>at least 16 24bit counters in one device? These counters (approx 2MHz)
>have to be latched syncronously (?)  to registers. These registers
>must be accessed from a microcontroller bus (C167).
<snip>

Question:

Do the counters all run off the same clock, or are they to be run from
different clocks?

Initial comment:

For long length counters, the following (in alphabetical order) could
be used: Altera FLEX8K & FLEX10K,  Lucent ORCA, Xilinx XC5200 and
XC4000x.

In muxing out to the 167 bus you'll use a lot of logic in Altera just
to do the 24x 16 to 1 multiplexers needed. (Check the thread on the
problems they appear to have with a 12:1 multiplexer). Each 16 to 1
mux in Altera is 10 LE's, so you just lost 240 Look up tables as a
minimum. Theoretically, in Xilinx and Lucent architectures, you can
use a load of tristate busses (free logic in this case) plus a single
decoder 4 input LUT for each counter address. I make that 16 LUT's.
Let's also assume that you want to mux to an 8bit bus, with 4 bytes
per counter, then we have another muxing requirement of eight 3:1
muxes (5 input function). Let's assume that this will add 16 LUT's to
each architecture. Now add 384 LUTs for the capture registers (assume
all captures are to be independent).

If we then give each architecture a 20% capacity margin to ensure
routing, then we get the following devices:

Altera 10K	1024 LUT's => 1280 LUT's => 10K30.
Altera 8K		1024 LUT's => 1280 LUT's => 81500.
Xilinx XC5200	1184 LUT's => 1480 LUT's => 5215.
Xilinx XC4000x	816 LUT's => 1020 LUT's => 4013E
Lucent ORCA	800 LUT's => 1000 LUT's => 2C10A

_Your_ mileage may vary.

I went to www.marshall.com and www.arrowschweber.com to get latest
one-of and 100-ofpricings for the cheapest devices of each and came up
with the following in ascending 100up order:

			1+	100+
Altera EPF81500AQC2404	$55.50	$39.50
Lucent OR2C10A2M84D	$46.90	$42.50
Altera EPF10K30RC2084	$98.00	$70.00
Xilinx XC5215-6PQ160C	$104.00	$75.80
Xilinx XC4013E-4PQ160C	$102.00	$87.80

Go figure. These are snapshot prices today and take no account of the
"we'll be paying you to use them next year" promises you may be made
with respect to forward pricing, or how desperate your respective
rep/disti is on the month you call.

They also don't take into account the wildly different levels of
performance you may expect from each chip. However, as you said 2MHz,
all of these should not have any problems in running at that speed.

Nor do they take into account development tool costs either.

(With the distributed memory families (Lucent ORCA and Xilinx 4000x)
you could look at serial counters implemented in RAM with some
control. Fiddly, but possible with the low speed required, and would
probably fit most of the smallest devices. Also makes reading the
values to the cpu and internal capture a bit harder too.)

My suggestion would be to devise a rough implementation of the circuit
you want, and then give the requirement to all of the vendors. Give
them a week or so to complete the assignment and return with their
tools for a demonstration of simulation and place and route.

This means you see something "real" instead of canned designs designed
to flatter one architecture. You will also see the competence of the
tools and support you can expect from the vendor, or vendors
representative.

Welcome to FPGA's.

Choose right, you'll love them.
Choose wrong, you might become an axe wielding homicidal maniac.

Regards
Stuart
--
For Email remove "die.spammer." from the address
Article: 8453
Subject: metastability: full citation of Hohl, extracting TAU and T0
From: mjohnson@netcom13.netcom.com (Mark Johnson)
Date: Tue, 16 Dec 1997 15:35:27 GMT
Links: << >>  << T >>  << A >>
  >
  > The Ph.D. thesis by Portmann (cited earlier on
  > this group) shows how.  So does the IEEE J.SSC paper
  > by Hohl.  Sorry I forget the exact issue# and page #s,
  > you can look it up, there aren't too many papers by
  > authors of that name.
  >

Portmann, C.L. et al. "Supply noise and CMOS
synchronization errors" IEEE JOURNAL OF SOLID-
STATE CIRCUITS  Sept. 1995. vol.30, no.9,
pp. 1015-17


Hohl, J.H., Larsen, W.R., and Schooley, L.C.,
"Prediction of Error Probabilities for Integrated
Digital Synchronizers," IEEE JOURNAL OF SOLID-
STATE CIRCUITS, Vol. SC-19, No. 2, April 1984,
pp. 236-244.


The methodology for extracting TAU and T0 from
SPICE simulations of parasitics-extracted-from-
layout circuits, is found in Section III of the
paper, pages 238 and 239.

  -M.J.
Article: 8454
Subject: Problems with license server for Xilinx M1 and Workview
From: Alfredo Rosado <alfredo.rosado@uv.es>
Date: Tue, 16 Dec 1997 18:40:56 +0100
Links: << >>  << T >>  << A >>
I have been trying to install Xilinx M1 and Workview on a Windows NT4.0
server in order to be able to run the software from other computers and
haveing the license server on the NT machine, but it does not work. Has
anybody done it before?, please could you tell me how it must b edone,
because I am not able to cope with it by just following the instructions
from the manuals.

    Thank you very much indeed.

Article: 8455
Subject: Re: metastability: full citation of Hohl, extracting TAU and T0
From: gah@u.washington.edu (G. Herrmannsfeldt)
Date: 16 Dec 1997 20:17:53 GMT
Links: << >>  << T >>  << A >>
OK, too much metastability already.  Anyway, not long after I learned
about metastability I was at a campground with a shower that was designed
so you had to hold the know turned on to keep the water flowing.

Wit a little trying, I found the metastable point on the shower knob,
and got it to stay on for the rest of my shower.

It doesn't only happen in electronics.

-- glen
Article: 8456
Subject: Re: bus design in Altera 10K, how to increase speed -- Check out Xilinx
From: berryhill@hep.uchicago.edu (Jeff Berryhill)
Date: Tue, 16 Dec 1997 20:22:22 GMT
Links: << >>  << T >>  << A >>
In article <01bd09aa$ea5dad60$6d733509@iachetta>,
	"Richard Iachetta" <iachetta@us.ibm.com> writes:
>
>Ok.  My experience was this summer (June/July) and we were 
>using the fastest 10k100 vs. the fastest 4085 at the time.
>  Both companies have come out with new stuff since.  When
> you say you've been using FLEX10K's, which ones did you use? 
> The 10k100?  The smaller they are, the faster they run. 
>It would take a lot to convincing me that the "new" 10K100's
> can do 50MHz. If they can, that's great, but having been 
>burned, I'm a little skeptical.
>
>-- 
>Rich Iachetta
>IBM Corporation
>iachetta@us.ibm.com
>
>

Mostly 10K50 (356 pin BGA) but also 10K70 and 10K100, but yeah the 
bigger ones will be slower.  I started compiling with the -1
 architecture only about a week ago, and the faster speed solved
some ongoing design problems of mine basically overnight.  The
 "registered performance" of the 10K50 nearly doubled in speed
from 30 MHz to 60 MHz, for my application.  YMMV.  

I'm _a lot_ skeptical with any broad claims of speed and the
like by the chip manufacturers, since the performance of the 
chips is so application-dependent.  Get the timing models from
Altera and see for yourself.  Basically I'm just pointing out
that, if you're willing to spend an outrageous amount of money,
there exist some new options from Altera that _might_ meet your speed 
requirements.       

--Jeff Berryhill


Article: 8457
Subject: Re: metastability: full citation of Hohl, extracting TAU and T0
From: rbmccammon@mmm.com (Roy McCammon)
Date: Tue, 16 Dec 1997 17:37:41 -0600
Links: << >>  << T >>  << A >>
G. Herrmannsfeldt wrote:
> 
> OK, too much metastability already.  Anyway, not long after I learned
> about metastability I was at a campground with a shower that was designed
> so you had to hold the know turned on to keep the water flowing.
> 
> Wit a little trying, I found the metastable point on the shower knob,
> and got it to stay on for the rest of my shower.
> 
> It doesn't only happen in electronics.
> 
> -- glen

It happens in my toilet tank all the time.



Opinions expressed herein are my own and may not represent those of my employer.

Article: 8458
Subject: Adaptec SCSI AVA 1505 and DOS
From: "Marco" <marval@magic.fr>
Date: 16 Dec 1997 23:50:09 GMT
Links: << >>  << T >>  << A >>
Hello,

I have an Adaptec SCSI AVA 1505 card with a Philips CDD2600 CDRom writer.

I have no problem to make that work in windows95, but absolutely impossible
to make it work in DOS, after booting in DOS with following system files.

Config.sys
	DEVICE=C:\SCSI\ASPI2DOS.SYS /D /Z
	DEVICE=C:\SCSI\ASPICD.SYS /D:ASPICD0

Autoexec.bat
	MSCDEX.EXE /D:ASPICD0 /M:12

During boot, everything is nice and OK, but when I want to read the CDrom,
I get the message "Not ready lecture sur lecteur D".

Which SCSI specialist can help me ?

Thanks.



Article: 8459
Subject: Best way to get Started with FPGAs
From: Richard Schwarz <aps@associatedpro.com>
Date: Tue, 16 Dec 1997 20:47:24 -0500
Links: << >>  << T >>  << A >>
The APS-X84 kits are the most complete and easiest way to get started in

FPGA development. They offer complete solutions including routers entry
tools
FPGA Test boards, low cost logic analyzers as well as VHDL starter
kits for those just getting started in VHDL. And the kits are priced
extremely low!
The X84 kits can be seen at:

http://www.associatedpro.com/aps/x84.html

--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 8460
Subject: FPGA Prototyping on the ISA Bus
From: "jtwhite@hal-pc.org" <jtwhite@hal-pc.org>
Date: Wed, 17 Dec 1997 00:17:54 -0600
Links: << >>  << T >>  << A >>
Does anyone know of a good source for a FPGA prototyping board for the
ISA bus.  Features that I'd like to have are:

1) 16-bit ISA card in either a 3/4 or full length format.

2) Hardware prototyping area of approximately 3" X 3".

3) FPGA connected to the 16-bit ISA bus and to a .1" X .1" header for
   connection to the prototyping area.

4) A quick and simple means of downloading and programming the FPGA.

5) Entry level VHDL development tools would be nice.

Thanks.
Article: 8461
Subject: Re: FPGA Prototyping on the ISA Bus
From: fliptron@netcom.com (Philip Freidin)
Date: Wed, 17 Dec 1997 08:16:39 GMT
Links: << >>  << T >>  << A >>
Fliptronics makes a card which I think meets most of your requirements:

In article <34976E92.1912@hal-pc.org> jtwhite@hal-pc.org writes:
>Does anyone know of a good source for a FPGA prototyping board for the
>ISA bus.  Features that I'd like to have are:
>
>1) 16-bit ISA card in either a 3/4 or full length format.

The card has 16-bit connectors, but only has the 8-bit bus prewired on 
the board. the extra 8 bus lines can be added with wire wrap wire, and 
there are headers on the board to support this. The card is full length 
format, and Fliptronics is a "good source" :-)

>2) Hardware prototyping area of approximately 3" X 3".

4.5" X 7.25"
Plated through .1" grid holes, internal VCC and Ground layers, brought 
out to perimeter holes, every 10th hole, with surface mount decoupling 
capacitors.

>3) FPGA connected to the 16-bit ISA bus and to a .1" X .1" header for
>   connection to the prototyping area.

Yep got this too. 90 uncommitted signals from FPGA to wire wrap area, on a
0.1" X 0.1" header. The rest of the FPGA signals go to the ISA connector,
and onboard SRAM and DRAM. The FPGA can be any 240 pin, 5V part that 
Xilinx makes. The standard board ships with an XC4025EHQ240-4

>4) A quick and simple means of downloading and programming the FPGA.

Board is shipped with download software to load the FPGA, as well as 
example software to talk to a design, once it has been loaded.

>5) Entry level VHDL development tools would be nice.

Sorry, I don't sell this, but AAPS (aaps@erols.com) does, and they also 
resell the above described board.

You can see the board at:

http://www.geocities.com/SiliconValley/2256/products.htm

>Thanks.

Your welcome. Thanks for the opportunity to respond to your article, and 
place a shameless advertisement in this news group.
If you require additional info, please look at the above web page, or 
email me.

Philip Freidin.
Article: 8462
Subject: Re: FPGA Prototyping on the ISA Bus
From: "Raymond E. Rogers" <rrogers@voyager.net>
Date: Wed, 17 Dec 1997 09:18:47 -0500
Links: << >>  << T >>  << A >>
I am a customer of Philip and his board does what he says and he is very
supportive in getting you going.  The documentation, while not being a
tutorial, is complete.

Raymond E. Rogers
Chrsyler DEC
rrogers@ceddec.com

* I do not speak for Chrysler; just my own experience doing work for
them *


Philip Freidin wrote:
> 
> Fliptronics makes a card which I think meets most of your requirements:
... snip ....
Article: 8463
Subject: Re: bus design in Altera 10K, how to increase speed -- Check out Xilinx
From: John McDougall <"john_mcdougall[NO SPAM]"@geocities.com>
Date: Wed, 17 Dec 1997 15:29:28 -0500
Links: << >>  << T >>  << A >>
Jeff Berryhill wrote:

> In article <01bd09aa$ea5dad60$6d733509@iachetta>,
>         "Richard Iachetta" <iachetta@us.ibm.com> writes:
> >
> >Ok.  My experience was this summer (June/July) and we were
> >using the fastest 10k100 vs. the fastest 4085 at the time.
> >  Both companies have come out with new stuff since.  When
> > you say you've been using FLEX10K's, which ones did you use?
> > The 10k100?  The smaller they are, the faster they run.
> >It would take a lot to convincing me that the "new" 10K100's
> > can do 50MHz. If they can, that's great, but having been
> >burned, I'm a little skeptical.
> >
> >--
> >Rich Iachetta
> >IBM Corporation
> >iachetta@us.ibm.com
> >
> >
>
> Mostly 10K50 (356 pin BGA) but also 10K70 and 10K100, but yeah the
> bigger ones will be slower.  I started compiling with the -1
>  architecture only about a week ago, and the faster speed solved
> some ongoing design problems of mine basically overnight.  The
>  "registered performance" of the 10K50 nearly doubled in speed
> from 30 MHz to 60 MHz, for my application.  YMMV.
>
> I'm _a lot_ skeptical with any broad claims of speed and the
> like by the chip manufacturers, since the performance of the
> chips is so application-dependent.  Get the timing models from
> Altera and see for yourself.  Basically I'm just pointing out
> that, if you're willing to spend an outrageous amount of money,
> there exist some new options from Altera that _might_ meet your speed
> requirements.
>
> --Jeff Berryhill

Come on guys. We have 70-80% full, 10k50-4 devices running at 50Mhz.
With alot of design consideration and pipelining, you can do almost
anything.
In another week I will have a fully portable design that I can truly see
how
Xilinx, Orca, and Altera compare.

Article: 8464
Subject: Re: bus design in Altera 10K, how to increase speed -- Check out Xilinx
From: "Richard Iachetta" <iachetta@us.ibm.com>
Date: 17 Dec 1997 21:26:18 GMT
Links: << >>  << T >>  << A >>
John McDougall <"john_mcdougall[NO SPAM]"@geocities.com> wrote in article
<34983628.3E76065E@geocities.com>...
> Jeff Berryhill wrote:
> 
> >
> > Mostly 10K50 (356 pin BGA) but also 10K70 and 10K100, but yeah the
> > bigger ones will be slower.  I started compiling with the -1
> >  architecture only about a week ago, and the faster speed solved
> > some ongoing design problems of mine basically overnight.  The
> >  "registered performance" of the 10K50 nearly doubled in speed
> > from 30 MHz to 60 MHz, for my application.  YMMV.
> >
> > I'm _a lot_ skeptical with any broad claims of speed and the
> > like by the chip manufacturers, since the performance of the
> > chips is so application-dependent.  Get the timing models from
> > Altera and see for yourself.  Basically I'm just pointing out
> > that, if you're willing to spend an outrageous amount of money,
> > there exist some new options from Altera that _might_ meet your speed
> > requirements.
> >
> > --Jeff Berryhill
> 
> Come on guys. We have 70-80% full, 10k50-4 devices running at 50Mhz.
> With alot of design consideration and pipelining, you can do almost
> anything.
> In another week I will have a fully portable design that I can truly see
> how
> Xilinx, Orca, and Altera compare.

John, the original poster of this thread (and I) were talking about the
10K100.  Jeff mentioned the 10K50 later.  I don't have direct experience
with the 10K50 but I can see from the data book that the routing timings of
the 10K100 are significantly slower than the 10K50 -- more than 5ns in one
case and several nanoseconds in most cases.  These add up very quickly on a
path.  Another point to consider is that super-pipelining your design to
run the clock faster may not be the best option if another vendor can
achieve the same clock rate less pipelined, thus decreasing your latency.

-- 
Rich Iachetta
IBM Corporation
iachetta@us.ibm.com


 
Article: 8465
Subject: Re: FPGA Prototyping on the ISA Bus
From: Richard Schwarz <aps@associatedpro.com>
Date: Wed, 17 Dec 1997 19:01:17 -0500
Links: << >>  << T >>  << A >>
Take a look at our site at http://www.associatedpro.com/aps

jtwhite@hal-pc.org wrote:

> Does anyone know of a good source for a FPGA prototyping board for the
> ISA bus.  Features that I'd like to have are:
>
> 1) 16-bit ISA card in either a 3/4 or full length format.
>
> 2) Hardware prototyping area of approximately 3" X 3".
>
> 3) FPGA connected to the 16-bit ISA bus and to a .1" X .1" header for
>    connection to the prototyping area.
>
> 4) A quick and simple means of downloading and programming the FPGA.
>
> 5) Entry level VHDL development tools would be nice.
>
> Thanks.



--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 8466
Subject: Example Problem (was Metastability)
From: Andreas Doering <doering@iti.mu-luebeck.de>
Date: Thu, 18 Dec 1997 08:49:51 +0100
Links: << >>  << T >>  << A >>
Koenraad Schelfhout VH14 8993 wrote:
> 
> Please stop the discussion on metastability here. 
OK, than lets turn to an actual example 
designed for FPGAs.
I have to cross a clock domain boundary. 
To make sure not to hurt any setup/hold-times I 
want to make an intermediate register that is 
loadedeither with the rising or falling 
edge of the clock where the data comes from. 
To decide this, I want to use the following 
phase comparator: 
-------------- VHDL (for SYNOPSYS FPGA-compiler synthesis -------
ENTITY EphaseComp IS
 PORT(clk1,clk2 : IN std_logic;
      phase : OUT std_logic);
END EphaseComp;

ARCHITECTURE syn1 OF EphaseComp IS

SIGNAL SposEdge,SnegEdge :std_logic;

BEGIN

PdriveSposEdge: PROCESS(clk1,clk2) 
BEGIN 
  IF clk1='1' THEN 
   SposEdge<='0';
  ELSE 
   IF clk2'EVENT AND clk2='1' THEN 
    SposEdge<='1';
   END IF;
  END IF;
END PROCESS PdriveSposEdge;

PdriveSnegEdge: PROCESS(clk1,clk2) 
BEGIN 
  IF clk1='1' THEN 
   SnegEdge<='0';
  ELSE 
   IF clk2'EVENT AND clk2='0' THEN 
    SnegEdge<='1';
   END IF;
  END IF;
END PROCESS PdriveSnegEdge;

PdrivePhase: PROCESS(SposEdge,SnegEdge) 
BEGIN 
  IF SposEdge='1' THEN 
   phase<='1';
  END IF;
  IF SnegEdge='1' THEN
   phase<='0';
  END IF;
END PROCESS PdrivePhase;
END syn1;
------------- END VHDL
The idea is quite simple: check wether the rising clock of 
clk2 appeared in the high or the low phase of clk1 
(clk1 is a little bit slower, than clk2)
Simulation of backannotated design, says everything 
is alright, I do not know, 
whether the libraries check all possible metastability 
problems. 
The critical point is, what happens, if the clk 
edge at the DFF appears very short after reset 
is deasserted. Setup- and hold times refer 
to the data input, which is constant, but
I assume, there is this topic, too (not mentioned
in the databooks?)
Andreas


-- 
---------------------------------------------------------------
                        Andreas Doering
                        Medizinische Universitaet zu Luebeck
                        Institut fuer Technische Informatik
		        Email: doering@iti.mu-luebeck.de
----------------------------------------------------------------
Article: 8467
Subject: Engineers Wanted
From: dmk1@valleytech.com (DM Kolesar)
Date: Thu, 18 Dec 1997 14:09:09 GMT
Links: << >>  << T >>  << A >>

	Immediate openings for hardware and software deisgn engineers
at a growing DSP product company. Valley Technologies is seeking  both
experienced and entry level engineers. If you desire to be part of
leading edge development company, please check out the following web
page:

http://www.valleytech.com/employment.htm




This article was posted from <A HREF="http://www.slurp.net/">Slurp Net</A>.
Article: 8468
Subject: Re: bus design in Altera 10K, how to increase speed
From: waynet@indirect.com (Wayne Turner)
Date: Thu, 18 Dec 97 16:10:57 GMT
Links: << >>  << T >>  << A >>
>On Fri, 12 Dec 1997 22:43:10 GMT, muzok@pacbell.net (muzo) wrote:
>I have a design which uses %55 of a 10K100 and within this design I have 12 8 bit
>registers which need to be selectively loaded into another register, IOW, I  have
>an 8 bit bus from which 12 8 bit registers hang. Because 10K doesn't have internal tristates, I have a big mux which selects the register. Currently
> this mux is the bottleneck in my design which limits my speed to  11 MHz in a -3
> part.
>
>Any ideas how to increase the speed in this design? The design is in Verilog.

Why not store the 12 8-bit registers in one of the EABs and 
selectively address which one you want to place into the target register?  No 
muxing required.  Use memory.  It will go plenty quick enough.

If you also need access to all 12 of the eight bit registers as well for 
internal use, then have these register values stored in logic cells with a 
mirror value in RAM that would be used to load the target register.  This way, 
you still have access to all of the 12 register values and you still don't 
need to mux anything to load one of them into the target register.  Internal 
use uses the logic cells, loading of the target register uses the mirror 
value from the RAM.

Wayne
 
Article: 8469
Subject: Re: bus design in Altera 10K, how to increase speed -- Check out Xilinx
From: berryhill@hep.uchicago.edu (Jeff Berryhill)
Date: Thu, 18 Dec 1997 19:11:47 GMT
Links: << >>  << T >>  << A >>
In article <34983628.3E76065E@geocities.com>,
	John McDougall <"john_mcdougall[NO SPAM]"@geocities.com> writes:
>Come on guys. We have 70-80% full, 10k50-4 devices running at 50Mhz.
>With alot of design consideration and pipelining, you can do almost
>anything.

This is almost certainly true, but there are many limiting factors:
very long pipelines 
very wide pipelines
very high I/O
limited device count on board
limited latency requirements
limited manpower
limited design schedule

A combination of such requirements will ultimately push one
to go to a higher speed chip if necessary, because $1000
for a chip beats spending a man-month pushing registers around.

I threw out the 30-40 MHz number as a baseline for designers
who will not spend a lot of time optimizing the design of a 10K50.
Sure you can almost always do better but who has the time? 
I'm haven't even started my Christmas shopping yet.


--Jeff Berryhill







Article: 8470
Subject: md5 in a FPGA?
From: Magnus Homann <d0asta@palver.dtek.chalmers.se>
Date: 18 Dec 1997 20:56:15 +0100
Links: << >>  << T >>  << A >>

Hi,

Just for fun we tried implementing MD5 in a FPGA. MD5 is a
authentication algoritm which uses a lot of 32-bit adds. It's targeted
for doing in software.

When using the largest Xilinx, we found that it got half the speed of
a pentium Pro at 200MHz and running NT4.0.

For this run, we used Synplifier and just modified the C-code into
VHDL. Do you think there will be any gains when optimizing the code
for Xilinx manually?

Homann
-- 
   Magnus Homann  Email: d0asta@dtek.chalmers.se
                  URL  : http://www.dtek.chalmers.se/DCIG/d0asta.html
  The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html
Article: 8471
Subject: xc4000e tms/tck/tdi/tdo pins
From: jhallen@world.std.com (Joseph H Allen)
Date: Thu, 18 Dec 1997 21:07:52 GMT
Links: << >>  << T >>  << A >>

Can the slew rate be controlled on the boundary scan pins when they're being
used as general I/O?  To use these I insert special symbols in place of the
normal ipad or opad in the schematic (orcad).  But it gives an error if I
set the slew rate option (FAST) on these symbols.

What is the default slew rate for these pins?  I would guess slow, but I'd
like to know for sure.


-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 8472
Subject: VME Interface on 10k family
From: paul@mrad.com.au (Paul Teagle)
Date: 18 Dec 1997 23:38:39 GMT
Links: << >>  << T >>  << A >>
Has anyone done a VME interface using the Altera 10k family? We are looking for A32:D32 slave, with interrupt generation capability, and block read/write capability. Speed isn't a big issue, and we are willing to use external bus interface chips if required.

As we wish to use other parts of the PLD for other logic, we don't want to use a dedicated VME interface chip (which we would still need to interface to.....)

Oh yes, we usually use AHDL, but can cope with VHDL or schematic.

Any references to library parts, designs people have used before, standard modules, etc, all gratefully received.

Thanks.

Paul Teagle
Systems Engineer
CAE MRad Pty Ltd




Article: 8473
Subject: Re: md5 in a FPGA?
From: "John L. Smith" <jsmith@uni_spamaway_vision.com>
Date: Thu, 18 Dec 1997 18:54:56 -0500
Links: << >>  << T >>  << A >>
99% probability you can get better performance by
optimizing for the part,
 BUT
It really depends on the nature of the MD5 algorithm.
How much data does it suck in vs. how much addition to
be performed, and can the additions be done in parallel,
or does each addition require a new word of data?

Further info on the algorithm would be helpful.



Magnus Homann wrote:
> 
> Hi,
> 
> Just for fun we tried implementing MD5 in a FPGA. MD5 is a
> authentication algoritm which uses a lot of 32-bit adds. It's targeted
> for doing in software.
> 
> When using the largest Xilinx, we found that it got half the speed of
> a pentium Pro at 200MHz and running NT4.0.
> 
> For this run, we used Synplifier and just modified the C-code into
> VHDL. Do you think there will be any gains when optimizing the code
> for Xilinx manually?
> 
> Homann
> --
>    Magnus Homann  Email: d0asta@dtek.chalmers.se
>                   URL  : http://www.dtek.chalmers.se/DCIG/d0asta.html
>   The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html
Article: 8474
Subject: FPGA Speeds ???
From: darkcyde <bazaillion@primary.net>
Date: Fri, 19 Dec 1997 09:53:06 -0600
Links: << >>  << T >>  << A >>
Hello,

I have a few questions about FPGA's

If a person was going to design some 2d/3d graphics circuitry lets say a
3dfx type 3d graphics accelerator or 2d chipset that is of the sorts in
a SEGA/PLAYSTATION/NINTENDO could a prototype be done with FPGA?
 
Would it be fast enough? or would the performance be degraded until
placed in a custom ASIC?

What is typical estimated costs for FPGA circuitry?

Thanks,
Michael Bazaillion
bazaillion@primary.net


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