Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 7925

Article: 7925
Subject: Part checksum calculate program?
From: Dan <no_spam@hp.com>
Date: Thu, 30 Oct 1997 14:52:02 -0800
Links: << >>  << T >>  << A >>
Does anyone know of a program that will calculate the checksum of a part 
from the programmer load file (binary and/or EXO format)? 

Thanks,

Dan
-- 
d@l.h.c | If you are a person you can read the vertical
a s p o | email address to the left. No spam please.
n i   m | 
c d     |
Article: 7926
Subject: Re: Help about ALTERA FPGA!!
From: Dongho Chung <actel@chollian.net>
Date: Fri, 31 Oct 1997 10:28:51 +0900
Links: << >>  << T >>  << A >>
After back-annotate the design, you can change pin, logic cells in
floorplan editor. The reason why you cannot modify this is you are in
the view of last compilation. If you change it to current assignment(you
can find this at layout menu in floorplan editor), you can modify it.

Thanks
D.H. Chung
Songsong wrote:

> Hi, everyone:
>
> I need your help.
>
> I use ALTERA's FPGA to design a controller. The first time, I assign
> the
> time for some pins, and fit successfully. But the pins are not
> distributed as I wanted. When I assign the pins location, I found it
> cann't fit or cann't get the specified time.
>
> I want to compile a design at first, when it success, back_annonate
> the
> design, but I find if I back_annonate the disign, I cann't modify the
> pins and logic cells in Floorpan editor. I think it can work, I don't
> know the answer, who can tell me.
>
> If you have used ALTERA's FPGA, please give me some advices.
>
> Thanx
>
> Songsong.



Article: 7927
Subject: Help about ALTERA FPGA!!
From: derrick <derrick@masca.demon.co.uk>
Date: Thu, 30 Oct 1997 19:00:25
Links: << >>  << T >>  << A >>
Songsong wrote
> 
> Hi, everyone:
> 
> I need your help.
> 
> I use ALTERA's FPGA to design a controller. The first time, I assign 
the
> time for some pins, and fit successfully. But the pins are not
> distributed as I wanted. When I assign the pins location, I found it
> cann't fit or cann't get the specified time.
> 
> I want to compile a design at first, when it success, back_annonate 
the
> design, but I find if I back_annonate the disign, I cann't modify the
> pins and logic cells in Floorpan editor. I think it can work, I don't 
> know the answer, who can tell me.
> 
Modifying the pin assignments in the floor plan editor make sure you are 
in the current assignments mode. Click on the icon which looks like a 
pencil pointing at the middle of a column of three squares. You cannot 
edit in the last compilation window.

To try and fit a design, first clear your pin and logic cell assignments 
and then assign the signals whose placement is critical. Let Maxplus do 
all the work. If this doesn't work you might have look at your design to 
see if changes will make it fit better into the device. 
 -- 
Derrick


Article: 7928
Subject: Slew Rate in ALTERA devices
From: Andreas Doering <doering@iti.mu-luebeck.de>
Date: Fri, 31 Oct 1997 08:56:13 +0100
Links: << >>  << T >>  << A >>
Hi all, 
after some days of RTFM and help files, ATLAs etc. I dare to ask the
public:
Is it possible to assign high slew rate mode to only some 
outputs in a design for a MAX9xxx (or FLEX). 
I only found the global style option for slow/high slew-rate,
but in one application it is recommended (as I expected) to 
assign high slew rate only to some speed critical signals.
But I found nowhere how to do so!
Thank you,
Andreas
---------------------------------------------------------------
                        Andreas Doering
                        Medizinische Universitaet zu Luebeck
                        Institut fuer Technische Informatik
		        Email: doering@iti.mu-luebeck.de
----------------------------------------------------------------
Article: 7929
Subject: Re: Slew Rate in ALTERA devices
From: Rune Baeverrud <r@acte.no>
Date: Fri, 31 Oct 1997 10:51:01 +0100
Links: << >>  << T >>  << A >>
Andreas Doering wrote:

> Is it possible to assign high slew rate mode to only some
> outputs in a design for a MAX9xxx (or FLEX).
> I only found the global style option for slow/high slew-rate,
> but in one application it is recommended (as I expected) to
> assign high slew rate only to some speed critical signals.
> But I found nowhere how to do so!

1) Go to Assign->Logic Options
2) Enter your node's name, or name of the I/O pin.
3) Click Individual Logic Options
4) Select Turbo bit, or deselect Slow Slew Rate.

Hope this helps.

Regards,
Rune Baeverrud
Article: 7930
Subject: Complex Multiplier
From: robert@ece.concordia.ca (Robert Morawski)
Date: 31 Oct 1997 17:37:40 GMT
Links: << >>  << T >>  << A >>
Hi, I used SPW (signal processing worksystem) from Alta Group, Synopsys, and
Xact software to design an 8bit input and 8bit output complex multiplier
(4 multipliers and two adders).  The final count of CLBS (using high mapping
effort) was 416 CLBs on XC4013-4 part.  Is there a better way (less CLBS) to
design an 8 bit input complex multiplier ?

Thanks,
Robert Morawski 


--
Robert Morawski
Department of Electrical and Computer Engineering 
Concordia University - 1455 de Maisonneuve West - Montreal, Que  H3G 1M8
Phone: (514) 848-8784    e-mail:robert@ece.concordia.ca
Article: 7931
Subject: Re: Complex Multiplier
From: Tom Burgess <tburgess@drao.nrc.ca>
Date: Fri, 31 Oct 1997 10:46:50 -0800
Links: << >>  << T >>  << A >>
A quick search turned up the following report which might
be of some interest:
http://infopad.eecs.berkeley.edu/~ian/ee241/proposal.html

a quote:
> For each complex multiply, for example (A + jB)*(C + jD), we must compute the result (R + jI) where R=AC - BD and I=AD + BC which,
> brute force, requires four multiplies, an addition, and a subtraction. Some cleverness may be employed to reduce the number of multiplies
> by one by noting that if we define M0=(A + B)*(C + D), M1=AC, and M2=BD, then we may calculate R=M1 - M2 and I=M0 - M1 - M2
> [Wei95][Oklobdzija94]. However, this still requires a fair amount of computation: three multiplies, two additions, and three
> subtractions. 

If you can tolerate some truncation error from only computing the
upper 8 product bits and doing only 8-bit adds and subs, this might
also save some CLBs. Another recent paper:

"Design of low-error fixed-width multiplier for DSP applications"
Jou & Kuang, IEE Electronics Letters - 11 Sept./97 V33 #19
This looks at multiplier designs that minimize errors due to only
computing uppermost product bits.

	regards, tom

Robert Morawski wrote:
> 
> Hi, I used SPW (signal processing worksystem) from Alta Group, Synopsys, and
> Xact software to design an 8bit input and 8bit output complex multiplier
> (4 multipliers and two adders).  The final count of CLBS (using high mapping
> effort) was 416 CLBs on XC4013-4 part.  Is there a better way (less CLBS) to
> design an 8 bit input complex multiplier ?
> 
> Thanks,
> Robert Morawski
> 
> --
> Robert Morawski
> Department of Electrical and Computer Engineering
> Concordia University - 1455 de Maisonneuve West - Montreal, Que  H3G 1M8
> Phone: (514) 848-8784    e-mail:robert@ece.concordia.ca
Article: 7932
Subject: Division & Multiplication (unsigned/signed) - Need HELP
From: Nestor Caouras <nestor@ece.concordia.ca>
Date: Fri, 31 Oct 1997 13:48:07 -0500
Links: << >>  << T >>  << A >>
Hi.

	In my efforts to build an efficient divider (unsigned for the time
being), I have used a method which separates the "y/x" quotient into a
product of "1/x" and "y". The "1/x" part is implemented in a ROM (in and
FPGA). So the input "x" addresses the ROM and the "1/x" value is
outputed and then multiplied with the "y" factor. Neither "x" nor "y"
are constants which makes implemtation a little more difficult (and less
efficient).

	My synthesis procedure of the method I used is the following and yields
less than acceptable results:
1. Block diagram design in SPW (Alta Group's (Cadence) Signal Processing
Worksystem)
2. VHDL code generation from SPW
3. Synthesis using Synopsys 3.4b
4. Place and route using Xilinx Alliance M1.3 and a -1 speed grade part.

	Any kind of input about this method or another better method for
implemeting division (or its sub-operations) would be greatly
appreciated. VHDL algorithms for signed or unsigned division can also be
useful to my project.

	Also, any info on where to obtain a good multiplication algorithm would
be very time saving.

Thanks in advance.

-- 
Nestor Caouras
nestor@ece.concordia.ca
http://www.ece.concordia.ca/~nestor/addr.html 
|-------------------------------------------|
| Dept. of Electrical and Computer Eng.     |
| Concordia University                      |
| 1455 de Maisonneuve Blvd (West)           |
| Montreal, Quebec, Canada H3G 1M8.         |
| Tel: (514)848-8784    Fax: (514)848-2802  |
|-------------------------------------------|
Article: 7933
Subject: Anyone using Protel Schematic 3 for XILINX?
From: z80@ds.com (Peter)
Date: Fri, 31 Oct 1997 19:59:25 GMT
Links: << >>  << T >>  << A >>
Just wonder how well this works. Xilinx sales reps don't know much
about it.

Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiXYZserve.com but
remove the XYZ.
Article: 7934
Subject: Re: [Reposted due to Enlow UCE cancel]: PROM for FLEX10K
From: Steve@s-dewey.demon.co.uk (Steve Dewey)
Date: Fri, 31 Oct 97 20:47:32 GMT
Links: << >>  << T >>  << A >>
Doug

Any chance of posting the code for that 7000 part that you use to load
the FLEX 10K ? 

Regards

Steve


In article <3458D8BB.6925@innocon.com> gibson@innocon.com  writes:

> > 
> > Hi Andrea,
> > 
> > For FLEX 10k, the EPROM is called EPC1 (Altera reference).
> > There are no EEPROMS. If you need a re-programmable solution for testing,
> > you can use a Bitblaster download cable, that you can deconnect after the
> > data has been transfered. This is what I'm using.
> > 
> > Andy Negoi
> > 
> We used one of the smaller 7000 series Altera parts in a socket that
> controlled an EEPROM. New code is easily put into the EEPROM and a reset
> to the 7000 part would reset the FLEX 10K and load it with the code.
> Doug
> 

-- 
Steve Dewey
Steve@s-dewey.demon.co.uk
Too boring to have an interesting or witty .sig file.


Article: 7935
Subject: Questions about FPGA hardware design
From: Cotton Seed <cottons@lcs.mit.edu>
Date: 31 Oct 1997 18:00:31 -0500
Links: << >>  << T >>  << A >>
Partially inspired by Jan Gray's site on Homebrew RISCs in FPGAs, I'd
like to start doing FPGA-based hardware design.  But I'm not sure
where to start.

I'm interested in learning about FPGA hardware design, and then
exploring processor architecture and micro-architecture.

As I see it, I need:

1. Software design tools.  I understand the software design tools the
least.  These tools take my design, in a standard HDL like VHDL or
Verilog, or a proprietary HDL (?) and turn them into a bitstream for
my FPGA device.  I assume these tools also do HDL simulation.

I've read parts of Peter Ashenden's _The Desginer's Guide to VHDL_.
In general, I understand RTL-level description in VHDL.

When programming a FPGA, do I also need to do layout in my design
(ie., map components of my design to logical structures within the
FPGA)?  Are these mappings also specified in VHDL?

What proprietary HDLs are out there?  What are thier comparative
advantages/disadvantages to VHDL/Verilog?  Jan Gray mentioned using
CNets HDL C++ class library for Xilinx FPGAs.  Are there others?

It seems most FPGA vendors have design tools.  In addition, a number
of 3rd party tool vendors exist.  How do specific vendor's offerings
(say, Xilinx and Altera) compare to 3rd party companies (like Exemplar
and Mentor Graphics)?

2. A FPGA programmer

After I've developed, simulated and verified a design, I need to
download it to an FPGA and run it.

It sounds like for testing purposes I can use a hardware programmer
driven by my desktop computer to program and debug the actual
hardware.  The Xilinx XChecker programmer sounds like a good option
here, since it can examine the running state of an FPGA.  Are there
other 3rd party programmers that support XChecker-like features?

FPGAs must be configured on power-up (usually by a boostrap ROM),
right?  Or are most FPGAs configured with non-volatile memory?

3. An FPGA

Choosing a device supported by the tools I want to use with the
capabilities required by my application seems simple enough.  Xilinx
4k series, Altera Flex10k, and Lucent Orca FPGAs seem particularly
attractive.

There are two things I'm confused about.

1. What do the speed ratings mean?  -1, -4, etc?

2. What do the various package types mean?  I'll probably wire wrap
any larger hardware design I use an FPGA in.

Any advice or experiences which could help me get started would be
most appreciated.

        - Cotton
Article: 7936
Subject: Re: Questions about FPGA hardware design
From: "Austin Franklin" <dark9room@ix.netcom.com>
Date: 31 Oct 1997 23:43:26 GMT
Links: << >>  << T >>  << A >>
Go to the Xilinx web site (www.xilinx.com) and get some of their data
sheets.  Same for Altera and Lucent if you're so inclined.  This will give
you your best starting point, understanding the architecture.  You might
want to just get an entire Xilinx data book, it explains all the available
parts, packaging, tools etc.

Austin Franklin
darkroom@ix.netcom.com

Article: 7937
Subject: 'compatible' fpgas
From: "Richard B. Katz" <stellare_nospam@erols.com>
Date: 1 Nov 1997 03:15:01 GMT
Links: << >>  << T >>  << A >>
Peter Alfke <peter@xilinx.com> wrote in article
<34551D1A.B5DB5A29@xilinx.com>...

<snip>
 
> Nobody makes pin- and functional compatible substitutes, and it is
> unlikely that there will be much second-sourcing in the future. At most,
> there might be devices that happen to have their supply pins in the same
> location, whatever significance that has.
> 
> Peter Alfke, Xilinx Applications

hi pete,

i think there is some significance for getting pins to line up and i'll add
clock and other special pins to the supply pins.  i have had feedback from
customers that they like the flexibility to potentially expand capabilities
in the future w/out having to make new boards.  and it helps keep costs
down to the bare minimum since i don't have to select a device w/
reasonable spare resources for changes and i can push things closer to the
edge and keep unit costs low.  i did this within actel by selecting a
a3265dx with the fall back of going to the a1280xl series if i got in
trouble on logic resources.  or back to a larger dx model if i wanted to 
add some internal dual-port sram for new features, for example.

another approach was taken by sei (space electronics inc.) in san diego. 
they took some quick logic die and packaged them to fit into 1020 and
1280 foot prints and called them the 1020yp and 1280yp if my memory is
correct.  this gave users more choice without changing their
layout with the faster quick logic devices.

lastly, i think this was the motivation by atmel; quickly going through
their recent announcements shows that they appear to have made their new
fpga family xilinx compatible and not atmel compatible.  here's what they
say
on their www site:

	The AT40K FPGAs are pin-compatible with Xilinx's XC4000 and XC5200 
	family, allowing users to upgrade their existing designs to higher 
	speed, lower cost and power, without having to relayout their boards.

it might be interesting to see just how compatible these devices are from
the pin-compatible perspective.  now i do not intend to be in a flame war
over this, these are just some observations.

-------------------------------------------------------------
rk

"there's nothing like real data to screw up a great theory" 
- me (modified from original, slightly more colorful version)
-------------------------------------------------------------

Article: 7938
Subject: Re: Complex Multiplier
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Sat, 01 Nov 1997 01:01:19 -0500
Links: << >>  << T >>  << A >>
Robert Morawski wrote:
> 
> Hi, I used SPW (signal processing worksystem) from Alta Group, Synopsys, and
> Xact software to design an 8bit input and 8bit output complex multiplier
> (4 multipliers and two adders).  The final count of CLBS (using high mapping
> effort) was 416 CLBs on XC4013-4 part.  Is there a better way (less CLBS) to
> design an 8 bit input complex multiplier ?
> 
> Thanks,
> Robert Morawski
> 
> --
> Robert Morawski
> Department of Electrical and Computer Engineering
> Concordia University - 1455 de Maisonneuve West - Montreal, Que  H3G 1M8
> Phone: (514) 848-8784    e-mail:robert@ece.concordia.ca


What is the data rate?  If the data rate low enough, you can use a 4x
clock and do all 4 multiplies using a single multiplier and adder.

Also, depending on what the multiplicands are, there may be some short
cuts that can be taken there.  For instance, if one multiplicand is a
unit vector with some arbitrary phase angle, A cordic rotator will run
faster and take less logic than using multipliers.  If a multiplicand is
a limited set of complex constants, then a modified LUT approach may be
the best.   

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka
Article: 7939
Subject: Re: Questions about FPGA hardware design
From: APS <APS@associatedpro.com>
Date: Sat, 01 Nov 1997 08:41:19 -0500
Links: << >>  << T >>  << A >>
Cotton Seed wrote:

> Partially inspired by Jan Gray's site on Homebrew RISCs in FPGAs, I'd
> like to start doing FPGA-based hardware design.  But I'm not sure
> where to start.

check our website at http://www.associatedpro.com/aps look at the VHDL
tutorialpages. They use the XILINX FOUNDATION software and the APS X84
FPGA board
and step you through VHDL code,  synthesis, routing, downloading
designs, and even in circuit testing.


>
>
> I'm interested in learning about FPGA hardware design, and then
> exploring processor architecture and micro-architecture.
>
> As I see it, I need:
>
> 1. Software design tools.  I understand the software design tools the
> least.  These tools take my design, in a standard HDL like VHDL or
> Verilog, or a proprietary HDL (?) and turn them into a bitstream for
> my FPGA device.  I assume these tools also do HDL simulation.

Some do some don't. We offer a stand alone Windows VHDL simulatorwhich
sells for around 700.00. (That's very low). We also offer synthesis and
router options for various FPGA vendors, as well as various levels of
debug
boards.

>
>
> I've read parts of Peter Ashenden's _The Desginer's Guide to VHDL_.
> In general, I understand RTL-level description in VHDL.
>
> When programming a FPGA, do I also need to do layout in my design
> (ie., map components of my design to logical structures within the
> FPGA)?  Are these mappings also specified in VHDL?

No, you don't have to, since the PLACE and ROUTE tools do this for you.
Theytake the synthesized netlist (XNF, EDIF etc) and first place and
then route your
design in the target FPGA. It is always best however to understand the
FPGA
hardware that you are using. This means that you will have to analyze
the basic
building blocks (CLBs,PLCs,LUTs,IOBs..etc) which the target technology.
You
actually don't have to know this, but the appropriate use of that
knowledge leads
to optimized designs.


>
>
> What proprietary HDLs are out there?  What are thier comparative
> advantages/disadvantages to VHDL/Verilog?  Jan Gray mentioned using
> CNets HDL C++ class library for Xilinx FPGAs.  Are there others?

I haven't tried any C++ stuff, but highly reccomend VHDL. It is more
andmore becoming the standard. XILINX Foundation Series for example
ships
with a VHDL compiler, not a Verilog compiler. Also the new PeakLucent
Kits
ship with VHDL as does the Altera suite I believe.

>
>
> It seems most FPGA vendors have design tools.  In addition, a number
> of 3rd party tool vendors exist.  How do specific vendor's offerings
> (say, Xilinx and Altera) compare to 3rd party companies (like Exemplar
>
> and Mentor Graphics)?

My experiences with all of the above have been pretty positive. I have
used Exemplar, Synplicity, Accolade, XILINX Foundation (Metamor), and
will soon be receiving SYNOPSIS FPGA Express (as part of my FOUNDATION
upgrade). Each has advantages. Exemplar and Synplicity are comporably
priced. Exemplar allows for hierarchial synthesis (many seperate
synthisized blocks resolved at router), while Synplicity does not.
Synplicity, has an advanced diagraming tool which lets you view all the
way down into the FPGA architecture components. Other tools like
Accolade's have an integrated VHDL Synthesis and VHDL Simulator at lower
costs than the EXEMPLAR/SYNPLICITY tools. We sell the Accolade tools
under our Synth-All brand and under the PeakLucent kits, as well as
XILINX Foundation tools which use the ALDEC tools.

>
>
> 2. A FPGA programmer
>
> After I've developed, simulated and verified a design, I need to
> download it to an FPGA and run it.
>
> It sounds like for testing purposes I can use a hardware programmer
> driven by my desktop computer to program and debug the actual
> hardware.  The Xilinx XChecker programmer sounds like a good option
> here, since it can examine the running state of an FPGA.  Are there
> other 3rd party programmers that support XChecker-like features?
>

If you buy our FPGA harware cards (APS-X84 for example) you can
downloadthe bit stream right from the PC ISA BUS into the card, and can
control the design
right in the circuit using the boards facilities to stimulate and read
back pins right through the PC IO bus. This allows you write test and
control code in C/C++ DELPHI/Visual BASIC etc. and do in circuit tests
or develop real time aplication code. We also sell a PC instrument for
use with our card which is basically a 100 Mhz POD LOGIC ANALYZER which
connects to the PC serial port and runs a logic analysis window on your
PC, to allow for debugging right down to the pin.

BTW- the PC FPGA cards alos have the capability to use PROMS or XCHECKER
CABLES also if desired. But after using the ISA BUS as a downloader I
think that you
will stay with that option.



> FPGAs must be configured on power-up (usually by a boostrap ROM),
> right?  Or are most FPGAs configured with non-volatile memory?

SRAM FPGAs (the most popular) use ROMs or are downloaded from a
microcontrolleror PC interface.


>
>
> 3. An FPGA
>
> Choosing a device supported by the tools I want to use with the
> capabilities required by my application seems simple enough.  Xilinx
> 4k series, Altera Flex10k, and Lucent Orca FPGAs seem particularly
> attractive.
>

I like the XILINX and Lucent parts in particular because of the on
boardtristates.


> There are two things I'm confused about.
>
> 1. What do the speed ratings mean?  -1, -4, etc?

Your guess are as good as ours. The vendors don't stick to any real
standard.In XILINX parts for example I always interpreted the -4 to be
4ns combinatorial delay
thorough one level of logic. A -1 would be faster at 1ns. But all
vendors don't use the same scheme and some are actually slower as the
numbers get smaller.


>
>
> 2. What do the various package types mean?  I'll probably wire wrap
> any larger hardware design I use an FPGA in.

THere are various packages from PLCC sockets to surface mount QFP (Quad
Flat packs) and now Ball Grid Arrays (MONSTERS)

>
>
> Any advice or experiences which could help me get started would be
> most appreciated.
>
>         - Cotton

  For your first design I would try using the APS-X84 board kits with a
VHDL synthesi system. Depending on cost and features the prices can go
from 800.00 for our APS-X84-FBV (BASE VHDL) which limits the size of the
FPGA to 8K gates to our
APS-X84-FSV which goes into the thousands. Or our Peak Lucent kits come
with a board which has some extra features (SRAM, 30 Mhz Dual DtoA and
Direct Digital Syntheized programmbale clock) plus a VHDL Simulator and
Synthesis package. Both systems come with everything you need to get
started and are expandable to allow other FPGA vendors to be added on.
Let me know more about you specific needs and I'll be happy to help you
out in selecting the best system for you.

--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 7940
Subject: Re: Polynomial division tool for LFSR/MISR simulation
From: NgOsSmPiAtMh@passport.ca (Gregory Smith)
Date: Sat, 01 Nov 1997 16:38:46 GMT
Links: << >>  << T >>  << A >>
In article <34577319.DB6@verdon.imag.fr>, Theodor Calin <calin@verdon.imag.fr> wrote:
I need to implement some polynomial division algorithms for test
>patterns generated 
>for ISCAS benckmarks. Could anybody suggest me some useful hints and
>references for the
>case I must do it myself ?

#define POLY 0x20400021  /* for instance, x^32+x^29+x^22+x^5+1 */
  unsigned crc,k;  /* assuming 32-bit machine here... */

        k = 32;
        crc = [[init-value]];
        for([[each word]]){
                crc ^= [[next-input-word]];       
                do{ 
                        /* one shift of a CRC register */
                        if( crc & 0x80000000 ){
                                crc = (crc<<1)^POLY;
                        }else{
                                crc = (crc<<1);
                        }
                }while(--k);
        }

Is that any help? You can do it faster with lookup tables.

Article: 7941
Subject: Re: Division & Multiplication (unsigned/signed) - Need HELP
From: NgOsSmPiAtMh@passport.ca (Gregory Smith)
Date: Sat, 01 Nov 1997 17:07:29 GMT
Links: << >>  << T >>  << A >>
In article <345A27E7.3FB6@ece.concordia.ca>, Nestor Caouras <nestor@ece.concordia.ca> wrote:
>Hi.
>
>        In my efforts to build an efficient divider (unsigned for the time
>being), I have used a method which separates the "y/x" quotient into a
...
>        Any kind of input about this method or another better method for
>implemeting division (or its sub-operations) would be greatly
>appreciated. VHDL algorithms for signed or unsigned division can also be
>useful to my project.
>
I assume your application can't tolerate the time required for a 'bit-by-bit' 
long division? can you put several of these in skew-parallel to reduce
the effective time?

Nestor, it makes a huge difference what kinds of errors you
can tolerate. Your 1/x table, unless x is always close to some
center value, will become very inaccurate for large x.
Have you considered a 'log' approach? use tables to approximate log2(x) and
log2(y), and then another table for 2^(y-x). The choice of 2 is important; for
instance, 2^z can be done by looking-up the fractional part of z and then
barrel shifting by the integer part. With this method the errors are uniform
relative to the magnitude of x and y.

For log x: rewrite x=2^k*(1+d), where k is an integer such that

(sqrt(0.5)-1)   < d < (sqrt(2)-1)      about -0.293 .. 0.414

'k'  can be found by a 'normalize' function which finds the MSB; then compare
the normalized result to sqrt(2) and shift again if larger. Now d is in the
range above, and 'k' is the integer part of your log. The fractional part
(which may be negative) is log2(1+d); Since 1+d is close to 1,
this can be approximated efficiently by 

     log2(1+d) =   (l/ln(2)) d + lookup[d]   

where the lookup table doesn't have to be very big (i.e. only use the first
few MSB's of d).
You may not have to go to such lengths, but this will reduce the table size 
at the expense of additional logic. The result above (log2(1+d)) will
always fall in the range [-0.5,0.5].

Of course you can just normalize so 'd' is in [0..0.999] and lookup the 
fractional log from there. log2(1+d) will also be in [0..0.9999].



>        Also, any info on where to obtain a good multiplication algorithm would
>be very time saving.

Many VLSI texts cover this. Look for 'Booth Coding' or 'Booth Multiplier';
that will at least bring you to the right place.
Article: 7942
Subject: REMEMBER THE WATKINS MAN??
From: cauleys@aol.com (Cauleys)
Date: 1 Nov 1997 17:42:38 GMT
Links: << >>  << T >>  << A >>
WATKINS BIZ-OPP!

     **Since 1868, Watkins Products have stood
        for quality, from generation-to-generation!

     **The Watkins Product Line features 375+
        items. Gourmet Food Items, Medicinal,
        Health & Nutrition, Household, Personal
        Care, Dietary Supplements, Gift Items 
        and MORE!

     **Founder J.R. WATKINS, introduced the
        first ever SATISFACTION GUARANTEE!

     **WATKINS REPRESENTATIVES can save/
        earn 28-61% discounts/profits on the sug-
        gested retail prices.

     **WATKINS REPRESENTATIVES have NO
        monthly sales quotas or required purchase
        amounts.

      **WATKINS REPRESENTATIVES are not
         required to maintain inventories, attend
         meetings of hype or folklore, deliver
         product or make collections.

      **THE WATKINS HOME OFFICE is now
         set up to process and ship all retail 
         customer and/or representative orders.

      **YOUR RETAIL CUSTOMERS can order
         direct via Watkins by calling Toll Free,
         by Direct Mail and/or via the Internet.
         Watkins will accept personal checks,
         money orders, Visa, Discover or Master-
         Cards.

       **THE WATKINS BUSINESS OPPORTUNITY
          was chosen as one of the top eight by
          MLM INSIDER MAGAZINE!

        **THE WATKINS BUSINESS OPPORTUNITY
           was chosen as one of the top ten by
           SUCCESS MAGAZINE!

         **THE WATKINS BUSINESS OPPORTUNITY
            was chosen as the NUMBER ONE BUSI-
            NESS OPPORTUNITY in the USA and
            CANADA by WAVE 3.

          **WATKINS will soon be expanding abroad
             by opening distribution centers in NEW
             ZEALAND and AUSTRALIA.

           **A PRESENT DAY WATKINS BUSINESS
              is no longer a horse & buggy, door-to-
              door solicitation mode. You can build an
              extremely successful WATKINS BUSI-
              NESS via mailorder or the internet.

GET YOUR FREE
NO OBLIGATION
WATKINS PROSPECT PACK
& CATALOG! JUST
SEND YOUR USPS
SNAIL MAIL ADDR-
ESS TO: cauleys@aol.com
CAULEY MARKETING GROUP
P.O. BOX 10
PANACEA, FLORIDA 32346-0010

Tel No: (850)926-9350 or (850)926-9330
E-mail: cauleys@aol.com  cauleys@freeyellow.com
VISIT OUR WEBSITE FOR ADDITIONAL INFO!
http://MasterNetworker.com/watkins/cauley.html







Article: 7943
Subject: Re: REMEMBER THE WATKINS MAN??
From: pfraser@dnai.com (Pete Fraser)
Date: Sat, 01 Nov 1997 10:02:42 -0800
Links: << >>  << T >>  << A >>
In article <19971101174200.MAA23866@ladder01.news.aol.com>,
cauleys@aol.com (Cauleys) wrote:

[nothing of consequence]


Oh, piss off.

-- 
Pete Fraser
Article: 7944
Subject: Re: Complex Multiplier
From: fliptron@netcom.com (Philip Freidin)
Date: Sat, 1 Nov 1997 20:49:42 GMT
Links: << >>  << T >>  << A >>

I think your example application (and its results) are an excelent example
of why I am still an old stick-in-the-mud schematics-type-of-guy. Synthesis
design promotes architecture neutral design, which unfortunately 
decouples you from the ability of taking advantage of facilities and 
advantages of a specific target architecture.

With probably little more effort than you need to do your synthesis 
design, I would have drawn a schematic withe the following symbols from 
my data path libraries:

4 copies of an 8 by 8 multiplier
2 copies of a 16 bit in, 17 bit out adder.

Because the libraries I am using are XC4000 specific (and also work for 
XC4000E and XC4000EX and XC4000XL and XC4000A and XC4000H and XC4000D (so 
not too specific)) ther is no ambiguity about how this will compile and 
the resources it will take.

The multipliers are 54 CLBs each, are 4 pipe stage deep, run at 80MHz in the
-1 speed grade of the XC4000E ( so probably more like 25 to 30 MHz in the 
4013-4 parts you are using) , and are floor planned for minimal area.

The adders will be 18 CLBs each, including an output pipeline stage.

Total is 252 CLBs. 
5 Pipe stages.
25 to 30 MHz clock rate.

This actually gives two 17 bit numbers R+I. If you only want 8 bit 
results, throw away the low order result bits. You may also be able to 
throw away the low order logic of the adders, depending on your 
tollerance to errors in the LSB of your remaining results.

A good demonstration that design re-use with schematics is easy to do if 
the libraries are designed correctly.

You asked for a better way. I think the above is close to optimal. 
You could use even less CLBs by time sharing fewer multipliers (minimum 
of one, time sgared 4 ways), and similarly with the adders. There are 
diminishing returns down this path, as the extra muxes and registers 
required for timesharing start to approach the logic they are replacing.
 
The multipliers are a derivative of the Xilinx LogiCore DSP libraries 
(available from their web site I believe), and the adders come from
a library that Fliptronics (my company) will soon be making available.
Similar adders are available in the standard Xilinx libraries.



Philip Freidin.



In article <63d514$r9v$1@newsflash.concordia.ca> robert@ece.concordia.ca (Robert Morawski) writes:
>Hi, I used SPW (signal processing worksystem) from Alta Group, Synopsys, and
>Xact software to design an 8bit input and 8bit output complex multiplier
>(4 multipliers and two adders).  The final count of CLBS (using high mapping
>effort) was 416 CLBs on XC4013-4 part.  Is there a better way (less CLBS) to
>design an 8 bit input complex multiplier ?
>
>Thanks,
>Robert Morawski 
>
>
>--
>Robert Morawski
>Department of Electrical and Computer Engineering 
>Concordia University - 1455 de Maisonneuve West - Montreal, Que  H3G 1M8
>Phone: (514) 848-8784    e-mail:robert@ece.concordia.ca


Article: 7945
Subject: Re: Complex Multiplier
From: "Martin Mason" <mtmason@ix.netcom.com>
Date: Sat, 1 Nov 1997 13:40:29 -0800
Links: << >>  << T >>  << A >>


Philip Freidin wrote in article ...

...snip..

>
>With probably little more effort than you need to do your synthesis
>design, I would have drawn a schematic withe the following symbols from
>my data path libraries:
>
>4 copies of an 8 by 8 multiplier
>2 copies of a 16 bit in, 17 bit out adder.
>
>Because the libraries I am using are XC4000 specific (and also work for
>XC4000E and XC4000EX and XC4000XL and XC4000A and XC4000H and XC4000D (so
>not too specific)) ther is no ambiguity about how this will compile and
>the resources it will take.
>
>The multipliers are 54 CLBs each, are 4 pipe stage deep, run at 80MHz in
the
>-1 speed grade of the XC4000E ( so probably more like 25 to 30 MHz in the
>4013-4 parts you are using) , and are floor planned for minimal area.
>

Using Atmel's AT40K FPGA architecture which is optimised for array
multiplier problems such as this, each pipelined 8x8 multiplier will take 72
Atmel AT40K core cells (each half the size of a Xilinx CLB) and will achieve
70MHz+ operation with only one stage of pipelining (-1 worst case
commercial).   The non-pipelined 8x8 multiplier is 64 cells and 40MHz (-1
w.c. commercial). The AT40K Macro Generators, which ship as standard with
our IDS 5.0 s/w, will allow you to generate the multiplier in less than 5
mins (including symbol and schematic) and it will be architecture optimised
(hard macro).  If you would like more info.  check out http://www.atmel.com
and follow the AT40K FPGA link on the home page splash.

>The adders will be 18 CLBs each, including an output pipeline stage.
>
>Total is 252 CLBs.
>5 Pipe stages.
>25 to 30 MHz clock rate.
>
>This actually gives two 17 bit numbers R+I. If you only want 8 bit
>results, throw away the low order result bits. You may also be able to
>throw away the low order logic of the adders, depending on your
>tollerance to errors in the LSB of your remaining results.
>
>You asked for a better way. I think the above is close to optimal.
>You could use even less CLBs by time sharing fewer multipliers (minimum
>of one, time sgared 4 ways), and similarly with the adders. There are
>diminishing returns down this path, as the extra muxes and registers
>required for timesharing start to approach the logic they are replacing.
>

We achieve similar results for our adders too....

Martin Mason.
(Atmel Corp.)

...snip..



Article: 7946
Subject: Re: 'compatible' fpgas
From: APS <APS@associatedpro.com>
Date: Sat, 01 Nov 1997 16:52:09 -0500
Links: << >>  << T >>  << A >>
I too am very interested in how these new ATMEL parts will pan out. I
have seen the structure in the data sheets. The architecture seems  to
be smaller than XILINXs CLB with only one FF in the CLB. They do have
diagonal routing capabilities between their CLBs which they claim will
allow for better utilization in a samller area. They also calim to be
coming out with an XNF netlist translater which will translate XNF
designs into the new ATMEL designs.(not the easiest of jobs after
looking at the two architecure differences) They also have distributed
RAM throughout the chip which do not take up LUTs which is a nice
feature. I am convinced that the key for ATMEL will be getting low cost
tools out and getting the parts accessible. They will have a 900.00
development system and will of course cater to the well financed
campanies and probably give away those tools. But I am convinced that
getting low cost tools out to the masses is the way for this FPGA family
to take off. We are looking closely at the parts and will be looking to
see what kind of support ATMEL is going to give to facilitate the
acceptance of their parts. I would be interested to hear XILINX's
evaluations on the ATMEL parts and architecture. Perhaps Peter will
enlighten us as to his thoughts on the parts. I always enjoy reading his
informative posts.


Richard B. Katz wrote:

> Peter Alfke <peter@xilinx.com> wrote in article
> <34551D1A.B5DB5A29@xilinx.com>...
>
> <snip>
>
> > Nobody makes pin- and functional compatible substitutes, and it is
> > unlikely that there will be much second-sourcing in the future. At
> most,
> > there might be devices that happen to have their supply pins in the
> same
> > location, whatever significance that has.
> >
> > Peter Alfke, Xilinx Applications
>
> hi pete,
>
> i think there is some significance for getting pins to line up and
> i'll add
> clock and other special pins to the supply pins.  i have had feedback
> from
> customers that they like the flexibility to potentially expand
> capabilities
> in the future w/out having to make new boards.  and it helps keep
> costs
> down to the bare minimum since i don't have to select a device w/
> reasonable spare resources for changes and i can push things closer to
> the
> edge and keep unit costs low.  i did this within actel by selecting a
> a3265dx with the fall back of going to the a1280xl series if i got in
> trouble on logic resources.  or back to a larger dx model if i wanted
> to
> add some internal dual-port sram for new features, for example.
>
> another approach was taken by sei (space electronics inc.) in san
> diego.
> they took some quick logic die and packaged them to fit into 1020 and
> 1280 foot prints and called them the 1020yp and 1280yp if my memory is
>
> correct.  this gave users more choice without changing their
> layout with the faster quick logic devices.
>
> lastly, i think this was the motivation by atmel; quickly going
> through
> their recent announcements shows that they appear to have made their
> new
> fpga family xilinx compatible and not atmel compatible.  here's what
> they
> say
> on their www site:
>
>         The AT40K FPGAs are pin-compatible with Xilinx's XC4000 and
> XC5200
>         family, allowing users to upgrade their existing designs to
> higher
>         speed, lower cost and power, without having to relayout their
> boards.
>
> it might be interesting to see just how compatible these devices are
> from
> the pin-compatible perspective.  now i do not intend to be in a flame
> war
> over this, these are just some observations.
>
> -------------------------------------------------------------
> rk
>
> "there's nothing like real data to screw up a great theory"
> - me (modified from original, slightly more colorful version)
> -------------------------------------------------------------



--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 7947
Subject: Re: Division & Multiplication (unsigned/signed) - Need HELP
From: "Prof. Vitit Kantabutra" <vkantabu@computer.org>
Date: Sat, 01 Nov 1997 15:00:41 -0700
Links: << >>  << T >>  << A >>
Gregory Smith wrote:
> 
> In article <345A27E7.3FB6@ece.concordia.ca>, Nestor Caouras <nestor@ece.concordia.ca> wrote:
> >Hi.
> >
> >        In my efforts to build an efficient divider ...

I have some new algorithms for high-radix division that don't use
complicated table look-up.  The most recent paper is available at
http://math.isu.edu/~vkantabu/radix8.pdf, and can be viewed with Adobe
Acrobat Reader 3.0 or later.
Article: 7948
Subject: Re: Pin compatible
From: APS <APS@associatedpro.com>
Date: Sat, 01 Nov 1997 17:01:08 -0500
Links: << >>  << T >>  << A >>
Ray Andraka wrote:

> Mr Barry Tso wrote:
> >
> > May be the best substitute is the E part from Xilinx :>
> > They deliver better performance and lower cost.
> >
> > Although Atmel claims they have pin compatible part, they
> > can't have all the architecture feature from Xilinx.
>
> The Atmel AT40K is pin compatible in that it can be used in a Xilinx
> socket (dedicated pin assignments are the same, xilinx configuration
> modes and protocol are supported).  The internal architecture is quite
>
> different however.  Which part is the better one really depends on the
>
> application.  Atmel's pricing is very aggressive (I think it is about
> $40 for a 20K gate part in small quantities) so it is worth a look,
> especially in cost sensitive projects.
>
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka

  The concern I have is the flip flop count of the ATMEL FPGAs when
compared
to the flip flop count of the XILINX 20Kish range is not as high. It
does appear that using the FFs in the XILINX CLB, that at least one
require the use of an LUT, while all the ATMEL FFs are available without
using LUTs. One big plus which ATMEL has is that their distributed RAM
is not using their on board LUTs as XILINX does. Also the diagonal
routing resources look interesting. How all these facts will pan out in
actual implementation will be interesting to see.As it stands now, ATMEL
is just sending out the 20K parts. They have tweaked my interest, but
lets see what else they do now.

--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 7949
Subject: Synopsys FPGA Express and Altera 10K design
From: muzok@pacbell.net (muzo)
Date: Sat, 01 Nov 1997 22:22:31 GMT
Links: << >>  << T >>  << A >>
hi,
I am having trouble instantiating IO cells (INBUF, OUTBUF and BUFT) in a verilog
design with fpga express. FE doesn't seem to know about these 10K IO cells. It
doesn't put any  of them into the  EDIF file and maxplus2 complains about
unconnected ports etc. Any ideas how I can convince FE to use these cells ?

thanks

muzo

WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>


Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search