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Messages from 7625

Article: 7625
Subject: Advantages of VHDL vs. Verilog?
From: Creed Huddleston <creedh@worldnet.att.net>
Date: Mon, 29 Sep 1997 11:15:21 -0400
Links: << >>  << T >>  << A >>
Our company is just getting into FPGA design and I'm looking at the
various synthesis packages available.  Can someone please enlighten
me on the strengths and weaknesses of VHDL and Verilog and the types
of applications for which each is best suited?

TIA,
Creed
Article: 7626
Subject: Re: Still for sale OrCAD SDT & Xilinx XACT
From: Steve Goodwin <steve@p2cl_DSPM.demon.co.uk>
Date: Mon, 29 Sep 1997 16:18:26 +0100
Links: << >>  << T >>  << A >>
In article <60o8b2$lqv$1@newshost.cyberramp.net>, timolmst@cyberramp.net
writes
>
>>You got M1 for $100 bucks?  Who sells it for that price?  Last time I
>>checked, the foundation base package was $1000 and the foundation standard
>>package was $3000.  I assume the new M1 stuff is similarly priced.
>
>THat price is actualy fairly repeatable. Just go to a Xilinx seminar.
>Even the "regular everyday" price is down to about $495 now.
>

Could these comments be qualified by max gate counts and exactly what
you get in the package. My  full Step 6 and now M1 systems do not have a
limit on gate counts. The low cost Foundation I am buying for the front
end is limited to 8K gates (whatever that equates to in clb's) and would
not seem to be M1 as it supports chip types not yet supported by M1 (I
think)

-- 
Steve Goodwin...  De-spamming active, remove any _DSPM from address
Article: 7627
Subject: Re: AMD TAXI
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 29 Sep 1997 10:14:44 -0700
Links: << >>  << T >>  << A >>
If I remember right ( I wrote part of the AMD TAXI data sheet 13 years
ago ), there is an analog phase-locked loop acting as a clock frequency
multiplier. That means an on-chip 125 MHz ( ? ) Voltage Controlled
Oscillator which is not that easy to implement inside any FPGA.
If you are willing to bring in the >100 MHz clock from the outside, the
design should not be too difficult, provided you pick the fastest
available FPGA or CPLD.

Peter Alfke, Xilinx Applications

Article: 7628
Subject: Job Opportunities With A Hot California Company
From: "Tim McManamon" <tim@mcmanamon.com>
Date: 29 Sep 1997 18:27:24 GMT
Links: << >>  << T >>  << A >>
Los Angeles, California

We need ASIC Design Engineers to develop ASICs for one of our
next-generation products, a Layer 3, IP/IPX Ethernet Switch (one of the
hottest markets going at the moment). 

We're not Cisco, and we're not 3Com.  We're a small company who almost
overnight became the #3 market leader (based on Ethernet ports shipped). 
In fact, we're the second-fastest growing company in California; and this
is probably the ideal time to come on board.  We offer a very competitive
compensation package, including stock options that are actually worth
something today and can realistically be expected to be worth more in the
future.

Ideally, your background should be like this:  7+ years experience with all
aspects of ASIC design flow using VHDL and Verilog coding, including
simulation, synthesis, scan insertion, I/O and test benches.  You should be
familiar with Local Area Networking.  You should understand the
architecture/implementation of Ethernet switching products in ASIC.

We would like you to have the following education:  BSEE or similar;  MSEE
preferred.

We have retained an Executive Search firm, and you should contact them if
you are interested, using the information below.

Tim McManamon
Rogers-McManamon Executive Search
714-496-1614 voice
714-496-2305 fax
tim@mcmanamon.com
Article: 7629
Subject: FS Advin Pilot U84 Universal Programmer
From: Jim Chase <Jim.Chase@LucasControls.Com>
Date: Mon, 29 Sep 1997 15:59:23 -0500
Links: << >>  << T >>  << A >>
Advin Systems

PILOT-U84 --- Universal programmer with 84 pin-drivers, supports devices
up to 208 pins. 

$2895 New

Sell for $1,750 Mint Condition barely used

Price includes 
PX-20: For 20-pin PLCC devices, including PLDs, serial PROMs $99 new 
PX-32: For 32-pin PLCC EPROMs and Flash, including 2764 to 8-MEG 27080
	$139 new 
AM-XC100Q Supports Xilinx XC7372 and 73108 100-pin QFP. $329 new

Jim.Chase@LucasControls.Com
   or
Jim.Chase@MindSpring.Com
Article: 7630
Subject: FS Corelis PCI Probe Card
From: Jim Chase <Jim.Chase@LucasControls.Com>
Date: Mon, 29 Sep 1997 16:14:40 -0500
Links: << >>  << T >>  << A >>
Corelis PCI Probe Card for HP logic analyzers.

$750.00 Mint Condition - includes software, manual and
					nice case!

Jim.Chase@LucasControls.Com
    or
Jim.Chase@MindSpring.Com
Article: 7631
Subject: -Hot Young Girls -hhhot.jpg
From: asdlfjsadl@0w9fasfusd.com
Date: 29 Sep 97 21:17:35 GMT
Links: << >>  << T >>  << A >>

Check out the Hottest New Teen Sex Site on the Internet !!!


There are Girls doing things that will "Blow" your mind.



Visit:


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Article: 7632
Subject: circuitonline.com
From: deepka <deepka@best.com>
Date: Mon, 29 Sep 1997 14:29:56 -0700
Links: << >>  << T >>  << A >>
Check out CircuitOnline..Searchable directory of services designed for
the electronics/semiconductor design and manufacturing:
http://www.circuitonline.com
CAD Tools, IC Design Services, VLSI Research, FPGA, Maegacells
Article: 7633
Subject: book
From: shahrier@ccrl.nj.nec.com (Sharif M. Shahrier)
Date: 29 Sep 1997 23:38:49 GMT
Links: << >>  << T >>  << A >>
Is there a good book explaining how to code data structures such as circular buffers,
linked lists, LIFO stacks etc. in VHDL? I was interested if there were any books that
explains how to code efficiently. Please send me e-mail if you can help.

-- 
Sharif M. Shahrier				Tel:    1-609-951-2976
C&C Research Laboratories			Fax:    1-609-951-2499
4 Independence Way
Princeton, NJ 08540, U.S.A.			E-mail: shahrier@ccrl.nj.nec.com
Article: 7634
Subject: Re: vme vs compact pci
From: Ido Kleinman <kleinn@erez.cc.biu.ac.il>
Date: Tue, 30 Sep 1997 01:43:41 +0200
Links: << >>  << T >>  << A >>
Oh In Hee wrote:

> Hi,
> I'm looking for a Compact PCI interface spec. & vme vs compact pci
> perfomance comparison.
> Any hints are welcome. ( web-sites, vendor..)

Can't help you about VME specs. I am currently working on PCI card - and
after some searchs about general PCI standard I discovered that there's
one organization named the PCI Special Interest Group which holds all of
the up-to-date information about any variation of the PCI bus.

Check www.pcisig.com for details, I think most of the complete specs
cost something like 20 bucks.

--
--==  Ido Kleinman  ==--
kleinn@erez.cc.biu.ac.il


Article: 7635
Subject: Synthesis and module generation for FPGAs.
From: pryan@atnf.rp.csiro.au (Philip Ryan)
Date: Tue, 30 Sep 1997 04:15:51 GMT
Links: << >>  << T >>  << A >>
Once some new memory turns up for my PC I will be evaluating a couple
of packages for synthesizing HDL (Verilog) to FPGAs (Xilinx).

The packages I'm looking at are FPGA Express from Synopsys, and Leonardo
from Exemplar. I'm particularly looking for a tool which has the capability
for low level hacking -- eg for datapaths where I want to say exactly how a
block should be implemented. Ideally I'd like to have as much control as you
get with a CAD like Digital's PamDC, with synthesis of all the bits I don't
care about.

So far (based on a _real_ quick scan of the documentation) it seems that
FPGA Express doesn't have this, and that Leonardo does. However, ...
flicking through the documentation for another (earlier) Exemplar FPGA
synthesis product (Galileo) I notice a disclaimer re Xilinx -- module
generation only for XC7000(?), not for the XC4000XL parts I'm interested in.
Hmm.

After that long winded introduction, in the week while I'm waiting for
memory and evaluation licenses to turn up, has anyone used these tools
or similar? Does module generation exist for XC4000XL parts in Leonardo?

Replies eagerly awaited.

Philip Ryan.   

==============================================================================
                                     CSIRO
				     Telecommunications and Industrial Physics
				     Radiophysics Laboratory
                                     PO Box 76, Epping NSW 2121,
        Philip  Ryan.                Australia.
        pryan@tip.csiro.au
                                     Ph:  +61 2 9372-4424
                                     Fax: +61 2 9372-4490
==============================================================================
Article: 7636
Subject: Implementation of partial orders
From: Andreas Doering <doering@iti.mu-luebeck.de>
Date: Tue, 30 Sep 1997 08:29:09 +0200
Links: << >>  << T >>  << A >>
Hi,
I am interested in the computation in finite partial orders, 
esp. one with supremum and infimum for every subset. 
(I think the right term is lattice for that, but I nood not to 
use a Lattice device, though :-))

I am intersted in the maximum function. 
It has a lot of intersting properties.
I think there should be an efficient implementation 
for computing in these structures, because
- the booleans form a lattice
- lattices are monotonic in some sense

The task is as follows:
Given is a directed acyclic graph with exactly one source 
node (in-degree=0) and one sink node (out-degree = 0). 
From this a configuration is computed (together with an encoding scheme)
, and  afterwards if 2 values are given at the inputs, the output shows 
the earliest successor in graph of the two input nodes. 

I have already one idea how this could be done, but I have to 
work out the details before I come up with this.
I guess there might be some publications on this topic.
Andreas

-- 
---------------------------------------------------------------
                        Andreas Doering
                        Medizinische Universitaet zu Luebeck
                        Institut fuer Technische Informatik
                        Ratzeburger Allee 160
                 
                        D-23538 Luebeck
                        Germany

		        Tel.: +49 451 500-3741
		        Fax:  +49 451 500-3687
		        Email: doering@iti.mu-luebeck.de
----------------------------------------------------------------
Article: 7637
Subject: How to instantiate LPMs in Verilog (is there an equivalent for th
From: Martin Vorbach <Martin.Vorbach@SCRAP.de>
Date: Tue, 30 Sep 1997 09:27:53 +0200
Links: << >>  << T >>  << A >>
Hi!

can somebody explain me how LPMs are instantiated in Verilog?


Below is a code which instantiates Altera´s CSFIFO LPM in VHDL. How does
this code looks like in Verilog??

COMPONENT csfifo
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_NUMWORDS: STRING := UNUSED);
   PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
      wreq, rreq, clock, clockx2, clr: IN STD_LOGIC;
      empty, full: OUT STD_LOGIC;
      q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
      );
END COMPONENT;


Thank You

Article: 7638
Subject: Xilinx 5200 I/O Performance
From: nickg@hpqt0653.sqf.hp.com (Nick Gent)
Date: 30 Sep 1997 10:39:07 GMT
Links: << >>  << T >>  << A >>
I am looking for information regarding the Xilinx 5200-series.

Specifically:

 - How do you specify the NO DELAY option for a 5200 IOB?
   The 9/96 data book clearly indicates that it is available, but
   my local Xilinx support tell me that the NODELAY attribute is
   not supported for 5200.

 - How do you then make sure that the DFFs are placed in the optimum
   location to achieve the input set-up and hold times given in the data
   book?

   Surely the correct way is by setting a 'PADS:to:FFS:' timespec and 
   letting the place/route tool handle it. However, what spec do you
   put on? Do you have to assume a certain clock delay, and work 
   backwards from the set-up/hold specs??

   One answer I am not contemplating is placing LOC properties on
   all the I/O DFFs! We have a VHDL design flow and many tens of
   designs to do for several package-types, and this is *not* an option!

Thanks,
Nick
============================================================================
Nick Gent

Telecommunications Network Test Division         Email:     nickg@sqf.hp.com
Hewlett-Packard                                  Telephone: +44 131 331 7644
South Queensferry EH30 9TG                       Fax:       +44 131 331 7488
Scotland 
============================================================================

Article: 7639
Subject: Re: Advantages of VHDL vs. Verilog?
From: Charles Sweeney <CharlesSweeney@compuserve.com>
Date: Tue, 30 Sep 1997 12:08:36 +0100
Links: << >>  << T >>  << A >>
Creed Huddleston wrote:
> 
> Our company is just getting into FPGA design and I'm looking at the
> various synthesis packages available.  Can someone please enlighten
> me on the strengths and weaknesses of VHDL and Verilog and the types
> of applications for which each is best suited?
> 
> TIA,
> Creed

There's also Handel-C from ESL! This is a compiler with syntax based on
the C programming language, ideal for applications such as DSP, image
processing and pre- and post-processing of data in data acquisition
systems. See our web site below. It enables the implementation of
software algorithms directly in hardware for greatly increased
performance and, compared to hardware description languages such as VHDL
and Verilog, increased designer productivity and shorter learning times.

Charles
-- 


Charles Sweeney, Engineering Director, Embedded Solutions Ltd
Tel/fax +44 1235 510456   <http://www.embedded-solutions.ltd.uk/>
Email CharlesSweeney@compuserve.com or
csweeney@embedded-solutions.ltd.uk
6 Main Road, East Hagbourne, Didcot, Oxfordshire. OX11 9LJ.
Article: 7640
Subject: Re: Still for sale OrCAD SDT & Xilinx XACT
From: timolmst@cyberramp.net
Date: Tue, 30 Sep 1997 12:27:03 GMT
Links: << >>  << T >>  << A >>

>Could these comments be qualified by max gate counts and exactly what
>you get in the package. My  full Step 6 and now M1 systems do not have a
>limit on gate counts. The low cost Foundation I am buying for the front
>end is limited to 8K gates (whatever that equates to in clb's) and would
>not seem to be M1 as it supports chip types not yet supported by M1 (I
>think)

Yes, it is the 8K gate version. My point was that the price being
asked for old software was much too high. Even if you bought the $495
version it would be a much better deal than paying a bundle for old
software.


Tim Olmstead
webmaster of the CP/M Unofficial web page
http://cdl.uta.edu/cpm


Article: 7641
Subject: Problem using FAST config mode with X4kE part?
From: "Austin Franklin" <dark4room@ix.netcom.com>
Date: 30 Sep 1997 12:29:36 GMT
Links: << >>  << T >>  << A >>
I have a design using a 4013EPQ208-3, in master serial mode (M0, M1 and M2
tied low), and an XC17256 Xilinx PROM.  When the bit stream is generated
with the CONFIGRATE:SLOW option, it works fine.  When it is generated using
CONFIGRATE:FAST, it doesn't work.

I can't quantify what 'doesn't work' means, except to tell you, the chip
does not work....I don't know if that means 'at all' or 'certain parts of
it don't work'.  My guess, is not at all.  Sorry....but I'll have more info
on that at a later date.

What the question is, has anyone else had trouble with FAST mode with an
X4kE part?

The PROM is hooked to the FPGA as follows:

PROM pin	FPGA pin
DATA		DIN
/RES		/INIT
CCLK		CCLK
/CE		DONE

There are 4.7k external pullups on the FPGA pins PROG, DONE and INIT.  The
PROM is configured for an active low reset.

Thank you,

Austin Franklin
darkroom@ix.netcom.com

to reply to this post, remove the number from the reply address


Article: 7642
Subject: Re: Problem using FAST config mode with X4kE part?
From: jhallen@world.std.com (Joseph H Allen)
Date: Tue, 30 Sep 1997 15:07:26 GMT
Links: << >>  << T >>  << A >>
In article <01bccd9c$3f7118a0$55c220cc@drt1>,
Austin Franklin <dark4room@ix.netcom.com> wrote:
>I have a design using a 4013EPQ208-3, in master serial mode (M0, M1 and M2
>tied low), and an XC17256 Xilinx PROM.  When the bit stream is generated
>with the CONFIGRATE:SLOW option, it works fine.  When it is generated using
>CONFIGRATE:FAST, it doesn't work.

I haven't tried fast mode, but maybe the cclk slew rate is faster too?  If
so try a series damping resistor on cclk near the fpga.

-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 7643
Subject: Re: fifos design for fpga
From: Frank Gilbert <gilbert@informatik.uni-kl.de>
Date: Tue, 30 Sep 1997 16:39:00 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

--------------5EDC765C38CA
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

david.surphlis@gecm.com wrote:
> 
> Does any-one have a model for a fifo 16X4, which can be used in an fpga
> design 4000e series, if so i would be gald to here from any-one who has such
> a model or who could direct me to somewere, were i may obtain one.
> 
>                         Thanks  Davey

Dear Davey,

You should look at Xilinx Application Note XAPP051 "Implementing FIFOs
in XC4000 Series RAM" (http://www.xilinx.com/xapp/xapp051.pdf). There
you find all you need to know about fifos in XC4000e series.

I also attached a VHDL-code of a fifo I wrote some time ago (before I
read XAPP051). My example uses a component "ram16x4dp", use LogiBlox or
MemGen to generate a netlist for it (BTW: LogiBlox can also generate a
VHDL functional description).

Hope that helps.

Best regards 

Frank
____________________________________________________________________

    LOOK AT OUR WEB SERVER:  http://xputers.informatik.uni-kl.de

Frank Gilbert                       | University of Kaiserslautern
mailto:gilbert@informatik.uni-kl.de | Dept. of Computer Science 
   fax: ++49/0 631 205 2640         | Germany 

..._/  _/  _/_/_/  _/  _/ _/_/_/ _/_/_/  _/_/_/   _/_/ ....._/
..._/_/   _/   _/ _/  _/   _/   _/      _/   _/ _/  ......._/_/
..._/    _/_/_/  _/  _/   _/   _/_/_/  _/_/_/   _/_/ ._/_/_/_/_/
._/_/   _/      _/  _/   _/   _/      _/   _/     _/ ...._/_/
_/  _/  _/       _/_/    _/   _/_/_/  _/    _/ _/_/ ....._/

--------------5EDC765C38CA
Content-Type: text/plain; charset=us-ascii; name="fifo16x4_sync.vhd"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline; filename="fifo16x4_sync.vhd"

-- =====================================================================
-- Modulname:	FIFO16X4
-- Date: 	29.09.1997
-- Autor: 	Frank Gilbert (University of Kaiserslautern, Germany)
-- E-Mail:	gilbert@informatik.uni-kl.de
-- =====================================================================

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_arith.ALL ;
USE IEEE.std_logic_unsigned.ALL ;


ENTITY fifo16x4 IS
	PORT (
		reset :	IN	STD_LOGIC;
		clk :	IN	STD_LOGIC;		

		-- Input Port
		din :	IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
		we :	IN	STD_LOGIC;	

		-- Output Port
		dout :	OUT	STD_LOGIC_VECTOR(3 DOWNTO 0);
		re :	IN	STD_LOGIC;	

		-- Flags
		ef : 	OUT	STD_LOGIC; 	-- Empty Flag
		ff :	OUT	STD_LOGIC;	-- Full Flag
		ae :	OUT	STD_LOGIC;	-- Almost Empty Flag
		af :	OUT	STD_LOGIC	-- Almost Full Flag
	) ;
END fifo16x4 ;


ARCHITECTURE behav OF fifo16x4 IS

	COMPONENT ram16x4dp
	PORT(
		A: 	IN 	std_logic_vector(3 DOWNTO 0);
		DI: 	IN 	std_logic_vector(3 DOWNTO 0);
		WR_EN: 	IN 	std_logic;
		WR_CLK: IN 	std_logic;
		DPRA: 	IN 	std_logic_vector(3 DOWNTO 0);
		SPO: 	OUT 	std_logic_vector(3 DOWNTO 0);
		DPO: 	OUT 	std_logic_vector(3 DOWNTO 0)
	);
	END COMPONENT;

	SIGNAL read_adr, write_adr : 	STD_LOGIC_VECTOR(3 DOWNTO 0);
	SIGNAL dummy :			STD_LOGIC_VECTOR(3 DOWNTO 0);
	SIGNAL counter :		INTEGER RANGE 0 TO 16;

BEGIN
	dpram : ram16x4dp PORT MAP(
		a 	=> write_adr,
		dpra 	=> read_adr,
		di 	=> din,
		wr_en 	=> we,
		wr_clk 	=> clk,
		spo 	=> dummy,
		dpo 	=> dout
	);


	ff <= 	'1' WHEN counter = 16 ELSE '0';

	ef <=	'1' WHEN counter = 0 ELSE '0';

	af <= 	'1' WHEN counter >= 15 ELSE '0';

	ae <=	'1' WHEN counter <= 1 ELSE '0';


	fifo : PROCESS( reset, clk )
	BEGIN
		IF( reset = '1' ) THEN
			read_adr 	<= "1111";
			write_adr 	<= "0000";
			counter		<= 0;
		ELSIF( clk'EVENT AND clk = '1' AND clk'LAST_VALUE = '0' ) THEN
			IF( we = '1' ) THEN
				write_adr 	<= write_adr + "1";
			END IF;
			IF( re = '1' ) THEN
				read_adr 	<= read_adr + "1";
			END IF;
			IF( we = '1' AND re = '0' ) THEN
				counter <= counter + 1;
			ELSIF( we = '0' AND re = '1' ) THEN
				counter <= counter - 1;
			END IF;
		END IF;
	END PROCESS fifo;

END behav;

--------------5EDC765C38CA--

Article: 7644
Subject: Re: Problem using FAST config mode with X4kE part?
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 30 Sep 1997 10:18:09 -0700
Links: << >>  << T >>  << A >>
I suggest checking the CCLK-to-DATA  output delay of the SPROM. It
should be less than 50 ns if it is the current XC17256D from Xilinx. If
you use older or other SPROMs, make sure they are fast enough. I suspect
that's your problem.
Then I would check the CCLK period. It should be longer than 100 ns in
FAST , and eight times longer in SLOW.  That would leavemore than the
required 20 ns of DIN set-up time.

Call or e-mail me if the problem persists.
Peter Alfke, Xilinx Applications
tel 408 879-5091,  peter@xilinx.com
 
 

Article: 7645
Subject: Re: vme vs compact pci
From: bowtie@mclean.mcd.mot.com (Bill Dennen)
Date: Tue, 30 Sep 1997 17:36:26 GMT
Links: << >>  << T >>  << A >>
In article <34303D2C.CE245C9F@erez.cc.biu.ac.il>, Ido Kleinman <
kleinn@erez.cc.biu.ac.il> writes:
> Oh In Hee wrote: 
>  
> > Hi, 
> > I'm looking for a Compact PCI interface spec. & vme vs compact 
> > pci perfomance comparison. 
> > Any hints are welcome. ( web-sites, vendor..) 
>  
> Can't help you about VME specs. I am currently working on PCI card - 
> and after some searchs about general PCI standard I discovered 
> that there's one organization named the PCI Special Interest Group 
> which holds all of the up-to-date information about any variation of 
> the PCI bus. 
>  
For VME specs check http://www.vita.com

Regards


{>@<}
Bill Dennen                bill_dennen@mcg.mot.com   | we has met the enemy,
Technical Sales Support    (703) 714-0707            |    and they is us ...
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Article: 7646
Subject: Circuit Board & FPGA Designers
From: "Dave" <cleaner@starnetinc.com>
Date: 30 Sep 97 18:24:29 GMT
Links: << >>  << T >>  << A >>
Hi,

We have an opportunity for an individual who has done some complex Circuit
Board/FPGA design to work at a place where cutting edge technology is the
norm, and one of the very best design staffs in the country awaits.

This position is for someone who has between 3-10 years of high performance
custom circuit design under his/her belt.  You will be working on some of
the "neatest" projects you've ever seen, and will become a stellar hardware
designer for your efforts.

Some of the "buzz":  We are looking for High Speed Digital Designers,
having some experience with PLD's, FPGA's (ASICS), complex designs (nothing
simple at this place), understands timings, etc...  Not a person who still
needs a lot of instruction, we are hoping to find an individual who can
stand alone and bring a project in from scratch to production.

This is a great company!  Our guarantee is this:  If you go in and chat
with these people, you WILL want to work there, especially if you can do
this type of work.

They are located on the North side of Chicago, near Skokie or Evanston,
just off the Kennedy.  Salary will be very nice, they're not cheap, as
they're looking for the best we can bring in.

Please E-mail or Fax us at:

Hunter International
E-mail: cleaner@starnetinc.com
Fax: (815)356-9225

Thanks,

Dave... 
Article: 7647
Subject: Xilinx license idiocy
From: jhallen@world.std.com (Joseph H Allen)
Date: Tue, 30 Sep 1997 19:45:18 GMT
Links: << >>  << T >>  << A >>
Here I am twiddling my thumbs, waiting for Xilinx customer support to call
me.

I got the new M1 product update to XACT step for PCs, and I would love to
try it but the licensing system is seriously braindead.  It uses flexlm and
a parallel port dongle for copy protection.  This would be fine (PADS PCB
uses this method also, and it works fine), but it also requires a matching
hard drive partition serial number.  Now I don't understand how this
improves security either, but there it is.  They require it.  In fact their
flexlm license file is generated to match it, and their web-based license
file generator gives you only one shot to create this file, and gives you no
opportunity to change your mind about what hard drive you're going to
install the program on.

So they expect:
 - you to run their software on one machine only: no switching dongles to
   my lap-top anymore

 - your hard drive to never break

 - you to never upgrade the hard drive in your machine

 - hmm... maybe they don't require the dongle any more and the security
   is based entirely on the partition serial number.  This is great news!
   I'll install it on all my machines and edit the volume name entry of
   each of them to match!

What a vast improvement this is over xact step 6.0!  I'm really impressed!

Nope, customer support still has not returned my call.  I suppose they are
overwhelmed by calls from other M1 customers.

-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 7648
Subject: ISPD98: Call for Papers
From: ispd98@ee.iastate.edu (Symposium 98 Acct)
Date: 30 Sep 1997 20:56:18 GMT
Links: << >>  << T >>  << A >>
                            CALL FOR PAPERS
          1998 International Symposium on Physical Design (ISPD-98)
            April 6-8, 1998, Embassy Suites Hotel, Monterey, CA

                Sponsored by ACM SIGDA in cooperation with
         IEEE Circuits and Systems Society and IEEE Computer Society

The International Symposium on Physical Design provides a forum to exchange 
ideas and promote research on critical areas related to the physical design 
of VLSI systems. All aspects of physical design, from interactions with 
behavior- and logic-level synthesis, to back-end performance analysis and 
verification, are within the scope of the Symposium. Target domains include 
semi-custom and full-custom IC, MCM and FPGA based systems. The ACM/SIGDA 
Physical Design Workshop evolved into this Symposium last year and was very 
well-attended. Following its six predecessors, the 1998 symposium will 
highlight key new directions and leading-edge theoretical and experimental 
contributions to the field. Accepted papers will be published by the ACM Press 
in the Symposium proceedings. Topics of interest include but are not limited to:

     Management of design data and constraints
     Interactions with behavior-level synthesis flows 
     Interactions with logic-level (re-)synthesis flows
     Analysis and management of power dissipation 
     Techniques for high-performance design
     Floorplanning and building-block assembly 
     Estimation and point-tool modeling
     Partitioning, placement and routing 
     Special structures for clock, power, or test
     Compaction and layout verification
     Performance analysis and physical verification
     Physical design for manufacturability and yield
     Mixed-signal and system-level issues
     Physical design in parallel, distributed and Web environments

IMPORTANT DATES:        Submission deadline             December 5, 1997
                        Acceptance notification         January 26, 1998
                        Camera-ready paper due          February 23, 1998

SUBMISSION OF PAPERS:
Authors should submit full-length, original, unpublished papers (maximum 20 
pages double spaced) along with an abstract of at most 200 words and contact 
author information (name, street/mailing address, telephone/fax, e-mail). 
Previously published papers or papers submitted for publication to other 
conferences/journals will not be considered. Electronic submission via 
uuencoded e-mail is encouraged and is the preferred submission mode. Please 
email a single postscript file, formatted for 8 1/2" x 11" paper, compressed 
with Unix "compress" or "gzip" to
                         ispd98@cs.utexas.edu
Alternatively, you may send ten (10) hardcopies of the paper to:

        Prof. D.F. Wong, Technical Program Chair, ISPD-98
        University of Texas at Austin, Department of Computer Sciences,
        Austin, TX 78712, USA

SYMPOSIUM INFORMATION:
To obtain information regarding the Symposium or to be added to the Symposium 
mailing list, please send e-mail to ispd98@ee.iastate.edu. The ISPD web page 
is at http://www.ee.iastate.edu/~ispd98

SYMPOSIUM ORGANIZATION:
General Chair:          M. Sarrafzadeh (Northwestern)
Past Chair:             A. Kahng (UCLA)
Steering Committee:     J. Cohoon (Virginia), S. DasGupta (IBM),
                        M. Marek-Sadowska (UCSB), B. Preas (Xerox),
                        E. Yoffa (IBM)
Program Committee:      M. Alexander (WA State)     C.-K. Cheng (UCSD)
                        J. Cong (UCLA)              W. Dai (UC Santa Cruz)
                        J. Fishburn (Lucent)        D. D. Hill (Synopsys)
                        J. A. G. Jess (Eindhoven)   L. Jones (Motorola)
                        S. Kang (Illinois)          Y.-L. Lin (Tsing Hua)
                        M. Pedram (USC)		    R. Rutenbar (CMU)
                        C. Sechen (Washington)      M. Wiesel (Intel)
                        D. F. Wong (Texas), Chair   T. Yoshimura (NEC)
Publication Chair:      D. D. Hill (Synopsys)
Panel Chair:            N. Sherwani (Intel)
Local Chair:            R.-S. Tsay (Axis Systems)
Publicity Chair:        S. Sapatnekar (Minnesota)
Treasurer:              S. Souvannavong
Article: 7649
Subject: Re: Xilinx license idiocy
From: jhallen@world.std.com (Joseph H Allen)
Date: Tue, 30 Sep 1997 21:19:45 GMT
Links: << >>  << T >>  << A >>
In article <EHC6vI.6GJ@world.std.com>,
Joseph H Allen <jhallen@world.std.com> wrote:
>Here I am twiddling my thumbs, waiting for Xilinx customer support to call
>me.
>
>I got the new M1 product update to XACT step for PCs, and I would love to
>try it but the licensing system is seriously braindead.  It uses flexlm and
>a parallel port dongle for copy protection.  This would be fine (PADS PCB
>uses this method also, and it works fine), but it also requires a matching
>hard drive partition serial number.  Now I don't understand how this
>improves security either, but there it is.  They require it.  In fact their
>flexlm license file is generated to match it, and their web-based license
>file generator gives you only one shot to create this file, and gives you no
>opportunity to change your mind about what hard drive you're going to
>install the program on.
>
>So they expect:
> - you to run their software on one machine only: no switching dongles to
>   my lap-top anymore
>
> - your hard drive to never break
>
> - you to never upgrade the hard drive in your machine
>
> - hmm... maybe they don't require the dongle any more and the security
>   is based entirely on the partition serial number.  This is great news!
>   I'll install it on all my machines and edit the volume name entry of
>   each of them to match!

It's true!  The key is no longer needed and the security is entirely based
on the partition serial number.  This is vastly more conventient than that
silly hardware key thing.  I won't have to lug that key around when I use
my laptop anymore.

Now suppose you have linux installed on your hard (as I do) and the
Windows-95 vfat partition is /dev/hda2 and you want the serial number to be
(hex) AABB-CCDD:

log into root,

type: joe /dev/hda2,39,4     	# edits bytes 39-42 of drive C boot sector
type: ^T T                       	# put joe into overtype mode
type: ` x D D ` x C C ` x B B ` x A A	# Enters new serial number
type: ^K X                              # saves data back to disk

You could also do this from Windows-95 but you would have to write a C
program.  Remember it's bytes 39-42 of the first sector of the C: partition.
Be sure to make backups before messing with your boot sector.

-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}


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