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sourabh.dhir@gmail.com (SD) wrote in message news:<cb01307e.0410051430.7ab8037e@posting.google.com>... > Hi, > I am trying to implement a DSP algorithm in a FPGA. My algorithm has > sine and cosine functions in it. Can somebody help me in implementing > sine and cosine functions in MATLAB fixed point (using fixed point > toolbox) or VHDL. > Thanks, > SD In the past I used sin(x) == sin(x[msb]+x[lsb]) and the expansion gives me 3 or 4 multiplies and small table lookups with a final PLA to correct a few odd cases. The table lookups for a course sin,cos (x[msb]) can be very small. Also visit Ray Andraka's site, I'm sure there's something there on sin/cos with some interesting cordic functions. You could also stuff a blockram with a pretty good size table too. regards johnjakson_usa_comArticle: 74201
I'm currently using webpack 6.2i sp3 for some virtex II designs. Does Webpack 6.3sp1 have improvements in it that would improve my design implementaion? Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:<cjtjgd$al2$1@lnx107.hrz.tu-darmstadt.de>... > Antti Lukats <antti@case2000.com> wrote: > : Quote from Xilinx Website (the best support web as many seem to claim!): > > : "Support for 3S1000 and 3S1500 devices is available in ISE WebPACK 6.3i only > : when the product is downloaded and installed from the Web at > : www.xilinx.com/ise/webpack6" > > : if you go to the link to download 6.3 you get what ? > > : guess: you land to 6.2 download pages!! > > 6.3 webpack is out nowArticle: 74202
Hi Zohar, It's a single 32 bit Micron MT48LC4M32B2 just like the Cyclone devkit board. Ken "zg" <zohargolan@hotmail.com> wrote in message news:e24ecb44.0410040846.5eb0f5ad@posting.google.com... > Hi Kemmeth, > > Thank you again for your help. > What is the part number of the SDRAM chip you are using. Maybe the > difference is that I am simulating a different (Maybe slower) chip. > > Zohar > > "Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message news:<10lqi8vegegit29@news.supernews.com>... > > Hi Zohar, > > > > My system is running at 75 MHz right now. My fmax is 90+ so I may try a > > little higher too. > > I didn't simulate, but I used SignalTapII to verify that I was indeed > > dma'ing the contents of an external fifo into sdram at a rate of 1 clock per > > 32bit word. (480 words in ~485 cpu clocks) > > This was while my system was running out of the same sdram and operating on > > other sdram data simultaneously - so very good results! > > > > I'd like to add that I got these perfect results with the help of the Altera > > Nios team. I'll be posting this setup on the IP section of the Nios Forum. > > > > This was *writing* to sdram, and I haven't really looked at reads yet. > > Hopefully I'll be just as pleased with those results. In my case reads are > > not quite as critical as writes, as the data streaming in is real time and > > waits for no one. > > > > Ken > > > > > > "zg" <zohargolan@hotmail.com> wrote in message > > news:e24ecb44.0409301615.7b8bccaf@posting.google.com... > > > Hi Ken, > > > > > > Thank you for your response. > > > What frequncy are you running the NIOS? I tried simulating at 72MHz > > > and I got only 2 words bursts. > > > Are you using NIOS II? > > > > > > Regards, > > > Zohar > > > > > > "Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message > > news:<10lg0aca67jseaa@news.supernews.com>... > > > > "zg" <zohargolan@hotmail.com> wrote in message > > > > news:e24ecb44.0409241455.340ba130@posting.google.com... > > > > > Hi All, > > > > > > > > > > I am trying to use the SDR SDRAM controller that is comming with the > > > > > NIOS II development package. In the simulation it looks like this core > > > > > supports only 2 words bursts. I couldn't find anything in the > > > > > documentations. > > > > > Am I correct? > > > > > If this core supports bigger bursts then 2 words, any ideas what am I > > > > > doing wrong? > > > > > > > > > > Thank you all > > > > > Zohar > > > > > > > > Zohar, > > > > > > > > I'm working on a design that uses one 16MB sdram chip for most of its > > > > instruction and data memory. I rely heavily on dma and other burst > > reads > > > > and writes (ie cache) to get the performance I need. > > > > > > > > The sdram controller you're talking about is good enough to burst 480 32 > > bit > > > > words in under 485 cpu clocks. It's a beautiful thing to watch in > > Signal > > > > Tap as I get this performance. (Haven't explored the lenght limits > > above > > > > 480 - my external fifo's AlmostFull level) > > > > > > > > I'm hammering that sdram (through the Altera sdram controller) nines > > ways to > > > > Sunday and it performs flawlessly. > > > > > > > > I have some serious issues with the whole NiosI/II chain, but the sdram > > > > controller has been a champ. > > > > > > > > KenArticle: 74203
Hi Pino, It has been a long hard battle getting my ADC data streamed into my Nios for processing. I've been at it since May of this year and I've just now achieved success. I've gone through streaming dma, master port, and several interrupt driven input fifo setups. Our problem was 99% correct data on day one, but still 99% correct data month(s) later. (only 100% is acceptable) It was not until Altera found mercy on me and assisted me with this last 1%. I got them involved, because I thought I had found an actual bug in the dma controller. To their credit they took my evidence seriously. I've had a couple local HW engineers along the way have to give up. Altera demonstrated that it can work. I'd like to see more sample implementations, so that everyone can get the performance they need out of their designs quickly. SOPC and Nios are so incredible in power and ease of use, but it needs continuous improvement to "can" more and more cababilities. Ken "Pino" <pinod01@sympatico.ca> wrote in message news:b7ed9648.0410051125.7f5f54cc@posting.google.com... > "Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message news:<10lrfijae32bme9@news.supernews.com>... > > Hi, > > > > No config that I'm aware of other than in the SOPC builder wizard. I looked > > in the .ptf file and didn't see any additional settings that looked > > interesting. > > > > Ken > > > > "Markus Meng" <meng.engineering@bluewin.ch> wrote in message > > news:aaaee51b.0410010914.3916acce@posting.google.com... > > > Hi, > > > > > > I expected that you can initialize the burst > > > lenght after SDRAM startup. I just wonder what happens > > > in case you have a nios-II cache miss. > > > However I will have to spend some time simulating the whole bunch ... > > > > > > Configuration of SDRAM burst length is a normal step in > > > using SDRAM's, isn't it? > > > > > > Best Regards > > > Markus > > > > > > zohargolan@hotmail.com (zg) wrote in message > > news:<e24ecb44.0409301615.7b8bccaf@posting.google.com>... > > > > Hi Ken, > > > > > > > > Thank you for your response. > > > > What frequncy are you running the NIOS? I tried simulating at 72MHz > > > > and I got only 2 words bursts. > > > > Are you using NIOS II? > > > > > > > > Regards, > > > > Zohar > > > > > > > > "Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message > > news:<10lg0aca67jseaa@news.supernews.com>... > > > > > "zg" <zohargolan@hotmail.com> wrote in message > > > > > news:e24ecb44.0409241455.340ba130@posting.google.com... > > > > > > Hi All, > > > > > > > > > > > > I am trying to use the SDR SDRAM controller that is comming with the > > > > > > NIOS II development package. In the simulation it looks like this > > core > > > > > > supports only 2 words bursts. I couldn't find anything in the > > > > > > documentations. > > > > > > Am I correct? > > > > > > If this core supports bigger bursts then 2 words, any ideas what am > > I > > > > > > doing wrong? > > > > > > > > > > > > Thank you all > > > > > > Zohar > > > > > > > > > > Zohar, > > > > > > > > > > I'm working on a design that uses one 16MB sdram chip for most of its > > > > > instruction and data memory. I rely heavily on dma and other burst > > reads > > > > > and writes (ie cache) to get the performance I need. > > > > > > > > > > The sdram controller you're talking about is good enough to burst 480 > > 32 bit > > > > > words in under 485 cpu clocks. It's a beautiful thing to watch in > > Signal > > > > > Tap as I get this performance. (Haven't explored the lenght limits > > above > > > > > 480 - my external fifo's AlmostFull level) > > > > > > > > > > I'm hammering that sdram (through the Altera sdram controller) nines > > ways to > > > > > Sunday and it performs flawlessly. > > > > > > > > > > I have some serious issues with the whole NiosI/II chain, but the > > sdram > > > > > controller has been a champ. > > > > > > > > > > Ken > > It is nice to hear of some progress using the Altera SDRAM controller. > However, I must say I have not been so fortunate. I have been > trying for some time to develop my own Master peripheral in SOPC > builder to allow reads and writes to the SDRAM on my evaluation board. > However, there isn't any proper documentation on how to do so. The > NIOS makes a perfect master, but I do not want the overhead cost of a > processor in my application. Just can't afford it. If anyone has an > example of using SignalTap and more specifically viewing the interface > of the Avalon Bus, that would help me tremendously in debugging the > interface. > > PinoArticle: 74204
Brian Davis wrote: > > John H wrote: > > > > > > That is right. Did you make the same comment to Austin? > > > > Honestly, no. To me, you appear to be the one predisposed to > > being argumentative in the posts back and forth. > > > > I'd have to side with Rick on this one - Austin's 'bad hair day' > comment is what prompted Rick's response. > > Personally, I can easily ignore Austin's marketing spiels. > > My real beef with Austin is when he flames up an accurate technical > post with an insult-and-opinion laden response, for no apparent reason > other than to spread FUD when someone has taken the time and effort > to document tool or device problems about which Xilinx has been less > than forthcoming. > > He makes lots of noise when you point out the flaws in his reasoning, > yet when you pin him down by asking a detailed technical question, he > becomes strangely silent. I appreciate your comments. I am sure I would do better by not making noise about these things and normally I let it slide. But sometimes Austin gets under my skin. So I would like to apologize to all and I promise to restrain myself in the future. I have had enough "conversations" with Austin to realize that he is not going to change his "style" of posting here, so I would do better just to leave it all alone. Besides, this is just the internet... pretty silly to do much arguing here. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 74205
Hi Jingzhao, ouj wrote: > I am working on the Xilinx ML300 prototying board. I have a Linux image > that needs to be uploaded to the DDR memroy. > > I tried for a few days and was unable to figure out how this can be done. > Can any one kindly give me some hints? http://www.klingauf.de/v2p/index.phtml Have a look at section 5 "Booting the kernel via JTAG" on this page, it talks about exactly this problem. Regards, JohnArticle: 74206
john jakson wrote: > sourabh.dhir@gmail.com (SD) wrote in message news:<cb01307e.0410051430.7ab8037e@posting.google.com>... >>I am trying to implement a DSP algorithm in a FPGA. My algorithm has >>sine and cosine functions in it. Can somebody help me in implementing >>sine and cosine functions in MATLAB fixed point (using fixed point >>toolbox) or VHDL. > In the past I used sin(x) == sin(x[msb]+x[lsb]) and the expansion > gives me 3 or 4 multiplies and small table lookups with a final PLA to > correct a few odd cases. The table lookups for a course sin,cos > (x[msb]) can be very small. I have a National data book from the days when ROMs needed +12 volts with a SIN lookup rom set. There is the course ROM, and then more ROMs and an adder. I believe the fine ROMs are linear interpolation, such that only an adder is needed. As for the original problem, it would be easier to say with more description of what the real problem is. The best solution might depend on details not yet given. -- glenArticle: 74207
Hi, I have a question concerning my multi-clock design. A PLL is fed with a 30MHz external clock. There are three different clocks generated by the PLL: c0 : 48MHz (for internal use) c1 : 90MHz (for internal use) e0 : 90MHz (for external use) Apart from that I have a clock divider which generates an 12MHz clock out of c0 and an inverted 90MHz clock out of c1. When I compile the whole design I get the following warnings: 1.Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew Info: Detected ripple clock CLOCK_DIVIDER Do I have to make some assignment for that? How? I would appreciate your help. Rgds AndréArticle: 74208
"Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message
news:10m6j0ko352cb9b@news.supernews.com...
>
> Hi David,
>
> Sorry for the delay I've been out of town with no access.
>
> I'm using the standared included dma peripheral to empty a standard single
> clock fifo. I did not modify any of the master priorities.vr
>
So you have a DMA device set up to read from a fifo as a slave. Did you
make a class.ptf file for the fifo slave, that you could post here? Am I
right in thinking you used a standard fifo (i.e., readReq triggers a new
read) rather than a read-ahead fifo (i.e., readReq works as an acknowledge)
? I think the read-ahead version would eliminate your need of a read
latency. Also, were you feeding data into the fifo at full speed? In my
application, the other end of the fifo is much slower (roughly 1/6 of the
system speed), so I'd like to let the fifo build up a bit before starting a
burst - perhaps triggering a burst start when it is half-full, and stopping
again when it is empty. I expect to write my own slave, wrapping the fifo
and providing such control signals (I have much of the code for that from my
original version using my own master). Would I be correct in thinking that
the way to handle this is for the DMA to be set up to transfer a given
number of words, and have the slave assert waitRequest to pause the DMA
reads until the fifo was half-full?
David
> I can post a test project to the Nios Forum that runs on the Cyclone
devkit
> board, but I don't have time to document it very well.
>
> If anyone is in a bind they can contact me through the forum and I will
> email them a .zip of the project. (~4MB)
>
> The credit for this perfect performance goes mostly to an Engineer at
Altera
> who worked with me for over a week until we had it perfect.
>
> One thing was that Read_Latency="1" had to be added to the Interface to
User
> Logic settings. (see below for the entire settings list)
>
> Ken
>
> SYSTEM_BUILDER_INFO
> {
> Bus_Type = "avalon";
> Address_Alignment = "dynamic";
> Address_Width = "2";
> Data_Width = "32";
> Has_IRQ = "1";
> Base_Address = "0x010019A0";
> Has_Base_Address = "1";
> Read_Latency = "1";
> Read_Wait_States = "0.0cycles";
> Write_Wait_States = "0.0cycles";
> Setup_Time = "0.0cycles";
> Hold_Time = "0.0cycles";
> Is_Memory_Device = "1";
> Uses_Tri_State_Data_Bus = "0";
> Is_Enabled = "1";
> MASTERED_BY SCAN_IN_DMA/read_master
> {
> priority = "1";
> }
> IRQ_MASTER cpu/data_master
> {
> IRQ_Number = "0";
> }
> MASTERED_BY cpu/data_master
> {
> priority = "1";
> }
> }
>
>
> "David Brown" <david@no.westcontrol.spam.com> wrote in message
> news:cjrh8o$ck5$1@news.netpower.no...
> >
> > "Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message
> > news:10lnrtjlg7sff75@news.supernews.com...
> > >
> > > "Markus Meng" <meng.engineering@bluewin.ch> wrote in message
> > > news:aaaee51b.0409290819.a6020e5@posting.google.com...
> > > > Hi all [SOPC users],
> > > >
> > > > is there a way a can configure the read burst length of the
> > > > standard SDRAM controller within SOPC 4.1?
> > > >
> > > > Best Regards
> > > > Markus
> > >
> > > Hi Markus,
> > >
> > > You might try asking this over on the Nios Forum (www.niosforum.com).
> I'd
> > > like to know the answer as well. I looked through the controller's
> > > class.ptf file and even the verilog source and don't see anything.
> > >
> > > On writes however, I'm getting bursts of at least 480 long words at
one
> > > clock per word. (my system is running at 75MHz)
> > >
> >
> > Did you have to do anything special to achieve that? I have a custom
> > peripheral that is writing as fast as it can to the sdram, but I'm
getting
> > one 32-bit write every 3 clocks. With the prototype system I have at
the
> > moment, that's good enough, but I'd like to improve on it when we start
> > making the real thing. When reading, I'm getting one read every 2
> clocks -
> > again, it's not ideal but it works. I'd expect one read/write per clock
> for
> > most of the burst, with some waits while changing banks or refreshing.
> >
> > Also, my reader and writer peripherals are independant, so sometimes
they
> > coincide. The Avalone bus arbitration apparently cannot take bursting
> into
> > account, and swaps between the two accesses. Is there any way this can
be
> > improved upon, or do I have to implement my own mini-arbitrator to
control
> > the two peripherals?
> >
> >
> >
>
>
Article: 74209The concept of wasted power is not relevant... unless its a walkman strapped to your arm... I don't see many joggers with heatsinks strapped to their backs :-) But I did read a thesis on a 'self-timed' gate array design where everything is done by handshakes and local clocks. This would be imposable in a FPGA with its 4 clocks and no support for handshaking with variable delays. I've seen quotes of 30% smaller die and 30% lower power.. but you have to take marketers at their word don't you? Imaging a MP3 player where only the gates being used are being clocked and even then... only at the rate they are being used! You are talking an increase in play time and the saving of those batteries ... its even good for the environment. I wouldn't be surprised if things like MP3 and small consumer goods before the main stay of gate arrays.. they are one of the few things where this kind of benefit can be justified. but in a society of waste and consumerism ... power isn't worried about ... (unless you live in California). And this is not fantasy.. google knows all about it :-) Simon "Nicholas Weaver" <nweaver@soda.csua.berkeley.edu> wrote in message news:cjubvu$ngb$1@agate.berkeley.edu... > In article <ccd4e670.0410050203.1989f076@posting.google.com>, > Ian Dedic <ian.dedic@fme.fujitsu.com> wrote: > >The inescapable fact is that an FPGA solution will always consume a > >lot more power than an ASIC solution in a similar technology, > >typically 10x higher. For applications where this matters an FPGA > >solution is often just not viable; examples include portable equipment > >where 5-10W for an FPGA rules it out compared to 0.5-1W for an ASIC, > >or high-complexity system application where we're comparing 5-10W for > >a single big ASIC with 50-100W for 5-10 big FPGAs. > > For the huge system applications, however, there are cooling solutions > (eg, IA64 heatsinks which are rated for 140W of power) which work, so > the cooling cost can get just added onto one more side for the asic > and against the FPGA, to balance out that $1M mask set. > > But portable will never be a strong suite of conventional SRAM-based > FPGAs: programmable interconnect is simply too much capacitence > compared with wires, and thats an ugly fact of life for dynamic power > (let alone the static power of all those SRAMs). > -- > Nicholas C. Weaver. to reply email to "nweaver" at the domain > icsi.berkeley.eduArticle: 74210
I would like to implement Cache memory in to FPGA / CPLD. I would like to use LRU replacement policy for that. SO could any one suggest me whiich cache placement policy is best suited for that, whether the fully associative or 2- way set assosiative. Is it possible to implement LRU fully assosiative cache in to any FPGA or CPLD device family.Article: 74211
PLease helpm me in this regardArticle: 74212
Hello, I was doing a project with Actel FPGA ex128 with Libero Platinum Eval version software. in my project I had to use some counters,Multiplexers etc. which I wrote myself. Now as I was a beginner I didnt use the ActGen. Is it worth the effort to write the code partly by using ActGen macros for counter and muxes and etc. Thanks NaimeshArticle: 74213
"Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message n
> BTW, nice job on the Java processor! Very cool.
^^^
You mean nice jop ;-)
This thread turns out into a contest to build the fastest JOP version.
Choose an FPGA vendor of your choice and optimize HDL and tool
settings.
Maybe Martin should donate one of his boards to the winner ;-)
I allready submitted patches to martin to scrap 300 LUTs from the MUL
and ALU.
Paul removed another 200 by improved synthesis settings. At that rate
the processor will be very small very soon ;-)
Kolja Sulimma
Article: 74214
Hi,
It is understood that, HDL functional simulation will not bring out
any Metastability issue with the crossing clock domain paths.
|-----| |------|
---| FF1 |----------| FF2 |---
| | | |
Clk1--|> | Clk2--|> |
|-----| |------|
But, is there any tricky way to Fail the Fucntional simulation for
Crossing clock domain issues.
--
Regards,
Muthu
Article: 74215nweaver@soda.csua.berkeley.edu (Nicholas Weaver) wrote in message news:<cjubvu$ngb$1@agate.berkeley.edu>... > >or high-complexity system application where we're comparing 5-10W for > >a single big ASIC with 50-100W for 5-10 big FPGAs. > > For the huge system applications, however, there are cooling solutions > (eg, IA64 heatsinks which are rated for 140W of power) which work, so > the cooling cost can get just added onto one more side for the asic > and against the FPGA, to balance out that $1M mask set. Agreed for systems where forced-air cooling (or enormous heatsinks!) are OK. If your system is one PCB is a sealed box you're in big trouble :-) > > But portable will never be a strong suite of conventional SRAM-based > FPGAs: programmable interconnect is simply too much capacitence > compared with wires, and thats an ugly fact of life for dynamic power > (let alone the static power of all those SRAMs). Exactly what I was saying as a counterpoint to the Xilinx "FPGAs will take over the world" point of view! In the functions-per-mW game ASICs will always win. IanArticle: 74216
Anyone know how to instantiate ( in Viewdraw ) a bus with a fixed value? I try to explain better: if for example I have to add the constant decimal value 7 to an incrementer every time I have a rising clock event, I suppose I have to enter in the incrementer with a 4-bit wide bus which holds the value 7 every time. How can I do it?? As you see I'm very new with fpga programming, any help is very appreciated. Thanks in advance, Teo.Article: 74217
> > BTW, nice job on the Java processor! Very cool.
> ^^^
> You mean nice jop ;-)
>
> This thread turns out into a contest to build the fastest JOP version.
> Choose an FPGA vendor of your choice and optimize HDL and tool
> settings.
> Maybe Martin should donate one of his boards to the winner ;-)
OK, that's a good idea!
Here's the contest in two categories:
The smallest JOP in LC/LE count.
The fastest JOP in turn of fmax.
Both versions must run the embedded benchmark to show that the processor
is still working (I can verify this for the Cyclone and Spartan-3. Target
devices are the low-cost FPGAs Cyclone and Spartan.
You can change the pipeline to achieve a higher famx, but the benchmaks
must still run AND be faster than with the original pipeline. However, I
would avoid the pipeline change.
The prices: An ACEX 1K50 board
>
> I allready submitted patches to martin to scrap 300 LUTs from the MUL
> and ALU.
Yes, thanks. I think now it's the time to incorporate your changes :-)
> Paul removed another 200 by improved synthesis settings. At that rate
> the processor will be very small very soon ;-)
>
Martin
Article: 74218
Hi,
following question:
I have a signal in an 48MHz clock domain, it is high for exactly one clock
cycle.
Now I want to pass it to an 90MHz clock domain where the synchronized signal
should also be high for one 90MHz clock cycle.
Is the following approach reasonable?
signal l_valid_48 : std_logic; -- high for one 48MHz clock cycle
signal l_valid_h1 : std_logic;
signal l_valid_h2 : std_logic;
signal l_valid_h3 : std_logic;
signal l_valid_90 : std_logic; -- should be high for one 90MHz clock cycle
process(Reset, Clk_90)
begin
if Reset='1' then
l_valid_h1 <= '0';
l_valid_h2 <= '0';
l_valid_h3 <= '0';
elsif rising_edge(Clk_90) then
l_valid_h1 <= l_valid_48;
l_valid_h2 <= l_valid_h1;
l_valid_h3 <= l_valid_h2;
end if;
end process;
process(l_valid_h2, l_valid_h3)
begin
l_valid_90 <= '0';
if ((l_valid_h2='1') and (l_valid_h3='0')) then
l_valid_90 <= '1';
end if;
end process;
I would appreciate your opinion.
Rgds
Article: 74219ALuPin wrote: > process(Reset, Clk_90) > begin > if Reset='1' then > l_valid_h1 <= '0'; > l_valid_h2 <= '0'; > l_valid_h3 <= '0'; > > elsif rising_edge(Clk_90) then > l_valid_h1 <= l_valid_48; > l_valid_h2 <= l_valid_h1; > l_valid_h3 <= l_valid_h2; > end if; > end process; > > process(l_valid_h2, l_valid_h3) > begin > l_valid_90 <= '0'; > > if ((l_valid_h2='1') and (l_valid_h3='0')) then > l_valid_90 <= '1'; > end if; > end process; The 3 FF approach is a good one, but you should create the i_valid_90 on the clock as well. Just put the combinatorial statements within your clocked process, and I think it should work just fine. Regards, Pieter HulshoffArticle: 74220
"Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message
news:10m6j0ko352cb9b@news.supernews.com...
>
> Hi David,
>
> Sorry for the delay I've been out of town with no access.
>
> I'm using the standared included dma peripheral to empty a standard single
> clock fifo. I did not modify any of the master priorities.vr
>
I have just thought of another possibility for my non-optimal bursts. I
have been running the cpu at 60 MHz rather than the default 50 MHz for the
development board. There is no problem running at that speed (and it could
probably go a fair amount faster), as long as I'm lucky with the sdram clock
synchronisation (the clock setup on the Cyclone Nios development card is
daft, IMHO).
However, I notice that some of the timing parameters for the Micro sdram
chip are at 20 ns. The sdram controller will round these up to integer
clock cycles - at 50 MHz clock, that's one clock, while at 60 MHz they would
be two clocks. As far as I can see, the two timings in question ("Active to
read or write delay trcd" and "duration of precharge trp") should cause an
extra cycle during bank activation, but not during bursts - the sdram
supports full speed bursts up to 143 MHz. I'm also wondering if there is a
particular reason for having the default CAS Latency at 3 - the sdram chip
supports CAS 2 up to 100 MHz.
Article: 74221
You've got it. I generate a IRQ based on the fifo level and then in the ISR
I setup the dma to dump the fifo to an sdram buffer. The fifo is being
filled at about one word every 700ns and when the fifo level reaches 480 the
IRQ dump process is triggered. The interrupt latency is about 8uS and the
dma itself takes approximately 485 system clocks. (other code is hammering
the sdram in parallel + sdram refresh etc.)
Here is the fifo instantiation:
NFIFO : scfifo WITH (
INTENDED_DEVICE_FAMILY = "Cyclone",
LPM_WIDTH = 36,
LPM_NUMWORDS = 512,
LPM_WIDTHU = 9,
LPM_TYPE = "scfifo",
LPM_SHOWAHEAD = "ON",
OVERFLOW_CHECKING = "OFF",
UNDERFLOW_CHECKING = "OFF",
USE_EAB = "ON",
ADD_RAM_OUTPUT_REGISTER = "ON"
);
Then I hook the chipselect (CS) and read signals from the IUL port thusly:
RD_DN.d = SCAN_IN_CS & SCAN_IN_RE;
RD_DN.clk = CLK100M;
NFIFO.rdreq = RD_DN;
NF_OUT[35..0] = NFIFO.q[35..0];
NF_OUT[31..0] is connected directly to the data in port of IUL.
CLK100M is actually the sysclk which is 75 MHz right now. Timing analysis
says I'm good to 97MHz, but I haven't pushed it yet.
I'm pretty sure this info with the system builder IUL port settings I posted
earlier are all you need. Hope this helps.
Ken
"David Brown" <david@no.westcontrol.spam.com> wrote in message
news:ck05od$t7e$1@news.netpower.no...
>
> "Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message
> news:10m6j0ko352cb9b@news.supernews.com...
> >
> > Hi David,
> >
> > Sorry for the delay I've been out of town with no access.
> >
> > I'm using the standared included dma peripheral to empty a standard
single
> > clock fifo. I did not modify any of the master priorities.vr
> >
>
> So you have a DMA device set up to read from a fifo as a slave. Did you
> make a class.ptf file for the fifo slave, that you could post here? Am I
> right in thinking you used a standard fifo (i.e., readReq triggers a new
> read) rather than a read-ahead fifo (i.e., readReq works as an
acknowledge)
> ? I think the read-ahead version would eliminate your need of a read
> latency. Also, were you feeding data into the fifo at full speed? In my
> application, the other end of the fifo is much slower (roughly 1/6 of the
> system speed), so I'd like to let the fifo build up a bit before starting
a
> burst - perhaps triggering a burst start when it is half-full, and
stopping
> again when it is empty. I expect to write my own slave, wrapping the fifo
> and providing such control signals (I have much of the code for that from
my
> original version using my own master). Would I be correct in thinking
that
> the way to handle this is for the DMA to be set up to transfer a given
> number of words, and have the slave assert waitRequest to pause the DMA
> reads until the fifo was half-full?
>
> David
>
>
>
> > I can post a test project to the Nios Forum that runs on the Cyclone
> devkit
> > board, but I don't have time to document it very well.
> >
> > If anyone is in a bind they can contact me through the forum and I will
> > email them a .zip of the project. (~4MB)
> >
> > The credit for this perfect performance goes mostly to an Engineer at
> Altera
> > who worked with me for over a week until we had it perfect.
> >
> > One thing was that Read_Latency="1" had to be added to the Interface to
> User
> > Logic settings. (see below for the entire settings list)
> >
> > Ken
> >
> > SYSTEM_BUILDER_INFO
> > {
> > Bus_Type = "avalon";
> > Address_Alignment = "dynamic";
> > Address_Width = "2";
> > Data_Width = "32";
> > Has_IRQ = "1";
> > Base_Address = "0x010019A0";
> > Has_Base_Address = "1";
> > Read_Latency = "1";
> > Read_Wait_States = "0.0cycles";
> > Write_Wait_States = "0.0cycles";
> > Setup_Time = "0.0cycles";
> > Hold_Time = "0.0cycles";
> > Is_Memory_Device = "1";
> > Uses_Tri_State_Data_Bus = "0";
> > Is_Enabled = "1";
> > MASTERED_BY SCAN_IN_DMA/read_master
> > {
> > priority = "1";
> > }
> > IRQ_MASTER cpu/data_master
> > {
> > IRQ_Number = "0";
> > }
> > MASTERED_BY cpu/data_master
> > {
> > priority = "1";
> > }
> > }
> >
> >
> > "David Brown" <david@no.westcontrol.spam.com> wrote in message
> > news:cjrh8o$ck5$1@news.netpower.no...
> > >
> > > "Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message
> > > news:10lnrtjlg7sff75@news.supernews.com...
> > > >
> > > > "Markus Meng" <meng.engineering@bluewin.ch> wrote in message
> > > > news:aaaee51b.0409290819.a6020e5@posting.google.com...
> > > > > Hi all [SOPC users],
> > > > >
> > > > > is there a way a can configure the read burst length of the
> > > > > standard SDRAM controller within SOPC 4.1?
> > > > >
> > > > > Best Regards
> > > > > Markus
> > > >
> > > > Hi Markus,
> > > >
> > > > You might try asking this over on the Nios Forum
(www.niosforum.com).
> > I'd
> > > > like to know the answer as well. I looked through the controller's
> > > > class.ptf file and even the verilog source and don't see anything.
> > > >
> > > > On writes however, I'm getting bursts of at least 480 long words at
> one
> > > > clock per word. (my system is running at 75MHz)
> > > >
> > >
> > > Did you have to do anything special to achieve that? I have a custom
> > > peripheral that is writing as fast as it can to the sdram, but I'm
> getting
> > > one 32-bit write every 3 clocks. With the prototype system I have at
> the
> > > moment, that's good enough, but I'd like to improve on it when we
start
> > > making the real thing. When reading, I'm getting one read every 2
> > clocks -
> > > again, it's not ideal but it works. I'd expect one read/write per
clock
> > for
> > > most of the burst, with some waits while changing banks or refreshing.
> > >
> > > Also, my reader and writer peripherals are independant, so sometimes
> they
> > > coincide. The Avalone bus arbitration apparently cannot take bursting
> > into
> > > account, and swaps between the two accesses. Is there any way this
can
> be
> > > improved upon, or do I have to implement my own mini-arbitrator to
> control
> > > the two peripherals?
> > >
> > >
> > >
> >
> >
>
>
Article: 74222I have never used Xilinx's product before.In some articles are said the Xilinx's silicon is better than Altera.Is it realy?I'm only a university student and not have enough money to validate it.Can give some advice to me?Article: 74223
> I have never used Xilinx's product before.In some articles are said > the Xilinx's silicon is better than Altera.Is it realy?I'm only a > university student and not have enough money to validate it.Can give > some advice to me? IMHO, that vastly depends on : - What families you're looking for ( more like high-end FPGA with embedded procesors, lots of LE/CE, ... ) - What you want to do with it ... FWIW, I'm personnaly working at this time at a 'low-cost' design but that must do lots of multiplications, so the embedded multipliers of spartan 3 were a plus. Now, look at the JOP thread : If I wanted to implement it in a real app, the current results of altera synthesis would be a plus ... SylvainArticle: 74224
Bruce Sam wrote: > I have never used Xilinx's product before.In some articles are said > the Xilinx's silicon is better than Altera.Is it realy?I'm only a > university student and not have enough money to validate it.Can give > some advice to me? > There is the chip, the development system, the support, and the pricing. Since the support is the hardest part, choose the manufacturer which a colleague can introduce you to. You need at least a one hour introduction into everything. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
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