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Messages from 17500

Article: 17500
Subject: Re: nuneric_std package in Foundation 1.5
From: David Dye <davidd@xilinx.com>
Date: Mon, 02 Aug 1999 10:18:41 -0600
Links: << >>  << T >>  << A >>
Andy Peters wrote:

> Bret Eddinger wrote in message <37A1E7B1.555DC755@bah.com>...
> >Does anybod have any idea of how to enable the numeric_std library in
> >Foundation 1.5???  I've dried the download from xilinx giving me the
> >numeric_std.vhd file but when I try to add it to the project library it
> >gives me a ton of errors.  Any help would be appreciated.  Thanks in
> >advance.
>
> There's a Xilinx Answer about this at:
> http://www.xilinx.com/techdocs/5432.htm
>
> The problem is that it's not yet built into FPGA Express; you have to add it
> as a user library.  So, instead of:
>
> library ieee;
> use ieee.numeric_std.all;
>
> you have to create a new library and compile numeric_std into the new
> library.  As the Xilinx note indicates, you'll have to include the library
> like this:
>
> library myieee;
> use myieee.numeric_std.all;
>
> The note says to ignore warnings about assert and initial values.
>
> It's obvious what problems you'll have when trying to simulate.  You have to
> create a simulation library called myieee and compile numeric_std in that
> too.
>
> Supposedly they're going to put numeric_std in the ieee library (where it
> belongs) whenever Foundation 2.1 comes out.  Might as well wait.  We've
> waited *this* long already.

Andy and everyone, just to confirm:

Synopsys has included the numeric_std package in the IEEE library in their
3.2 release, which has been out since June.  This version of FPGA Express
is included in Foundation F2.1i, which began shipping Friday.

David Dye
Xilinx Product Applications

>
> --
> ----------------------------------------------------------------------------
> --
> Andy Peters
> Sr Electrical Engineer
> National Optical Astronomy Observatories
> apeters (at) noao.edu
>
> "I'm not judging you, I'm judging me."
> -- Mission of Burma, "Academy Fight Song"

great tune.

Article: 17501
Subject: Re: Xilinx Readback Problems
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 02 Aug 1999 09:25:07 -0700
Links: << >>  << T >>  << A >>


Gordon Hollingworth wrote:

> I'm trying to implement a Boundary Scan interface to a Xilinx 4010XL device
> to do Configuration and Readback.  The configuration works OK, but I've got
> some trouble with the Readback,  Could anybody tell me what length the
> bitstream should be for Readback, from the xilinx datasheets it should be
> 178,136 bit's (Including header and all!) but I'm receiving (and
> configuring) 283424 bits!
>

The XC4010E has ~178k configuration bits.
The XC4010XL has twice as much routing etc., which causes it to have ~283k
configuration bits.
See page 6-49 of the 1999 Xilinx Data Book.

Peter Alfke, Xilinx Aplications


Article: 17502
Subject: Re: Warning! The eclipse approaches... {5.3a}
From: bob@nospam.thanks (Bob Perlman)
Date: Mon, 02 Aug 1999 21:59:45 GMT
Links: << >>  << T >>  << A >>
On 2 Aug 1999 20:20:01 -0000, Anonymous
<Use-Author-Address-Header@[127.1]> wrote:

>
>That "monstriferous" Comet Lee will be seen during the
>solar eclipse this August 11th, followed by WWIII, the
>1300-meter "King of Terror" meteoroid impact before 10
>October 1999, and *many* catastrophic events, including
>the >20 degree shifting of the polar axis before 2002!
>The Tribulation prophesied even by our Lord and Savior
>Jesus Christ is begun. ANSWER THIS: Are you prepared?
>
>Godspeed,
>Daniel

Just tell me this: should I install M1 v2.1 now, or wait until after
the Apocalypse?

Thanks,
Bob Perlman
-----------------------------------------------------
Bob Perlman
Cambrian Design Works
Digital Design, Signal Integrity
http://www.best.com/~bobperl/cdw.htm
Send e-mail replies to best<dot>com, username bobperl
-----------------------------------------------------
Article: 17503
Subject: Re: Warning! The eclipse approaches... {5.3a}
From: thor@sm.luth.se (Jonas Thor)
Date: Mon, 02 Aug 1999 23:51:28 GMT
Links: << >>  << T >>  << A >>
On 2 Aug 1999 20:20:01 -0000, Anonymous
<Use-Author-Address-Header@[127.1]> wrote:

>
>That "monstriferous" Comet Lee will be seen during the
>solar eclipse this August 11th, followed by WWIII, the
>1300-meter "King of Terror" meteoroid impact before 10
>October 1999, and *many* catastrophic events, including
>the >20 degree shifting of the polar axis before 2002!
>The Tribulation prophesied even by our Lord and Savior
>Jesus Christ is begun. ANSWER THIS: Are you prepared?
>
>Godspeed,
>Daniel

Doh! I'm not as prepared as I would have wished. I don't think my
thesis will be accepted before the ">20 degree shifting of the polar
axis". Sorry!

/ Jonas Thor
Article: 17504
Subject: help about PCI bridge
From: "wqg" <srdwqg@sbell.com.cn>
Date: Tue, 3 Aug 1999 16:49:56 +0800
Links: << >>  << T >>  << A >>
Hello all,
I am sorry to trouble you,I want to use 9080 in the modle as follow:

                         CPU
                           |
                           |
                     Host bridge

                           |
         ------------------------------  PCI Bus
                           |
                           |
                       PLX9080
                           |
                           |
                     I/O device

I want to know if the I/O device will use DMA transfer mode,and it has 4
signal:DMARead,DMAReadAck,DMAWrite,DMAWriteAck for DMA transfer.
Can 9080 transfer the DMA request of I/O device to PCI bus and DMA
acknowledge to I/O device? That is to say ,can 9080 work in this structure?

Thanks in advance!




Article: 17505
Subject: Xilinx Virtex configuration in chunks
From: Hendrik De Vloed <hendrik.despam@barco.com>
Date: Tue, 3 Aug 1999 12:41:32 +0200
Links: << >>  << T >>  << A >>
Hello, all,


We want to configure a Xilinx Virtex XCV300-4 using the SelectMAP method. 
However, the data-sheet seems somewhat ambiguous:
Is it valid to deassert the Chip Select (nCS) once configuration has started?

The application notes all seem to use one continuous chip select signal, 
asserted at the start, and deasserted once all data has been loaded. The flow 
chart on page 3-20 of the databook also inhibits a temporary deassertion of nCS 
during the transmission of configuration data. On the other hand, p. 3-19 
states "The packet does not have to complete within one assertion of CS, ..."

As we want to use the nCS linked to a processor's address decoder, the nCS 
would assert once per byte written.

Is this valid?

Greetings,

-- 
Hendrik De Vloed --  A4000/40 -- Aminet:hard/hack/lcdaemon.lha
-- Barco Silex FPGA/ASIC design   --   http://www.barco.com --
***   #include<these_are_my_opinions_legal_mumbo_jumbo.h>  ***
     <To reply by E-mail, remove the "_hates_spam_" parts>


Article: 17506
Subject: Re: Digital modulator? Synthesisable Sin(x) funct.
From: Ray Andraka <randraka@ids.net>
Date: Tue, 03 Aug 1999 09:18:23 -0400
Links: << >>  << T >>  << A >>
Try calling Hamilton Avnet.  They might be able to sell in single quantity for a
small premium.  If not, they may be able to direct you to a reseller that will sell
in single quantities.

If you don't have any luck with the distributers, Try Digi-key (www.digikey.com).
They don't list spartan or virtex in their catalog, but they can usually get
parts.  They will probably be more expensive than other distributors.  Other places
you might try (also with substantial mark-ups) are Newark and Allied Electronics.

Glad I could help.

Luis Yanes wrote:

> On Wed, 28 Jul 1999 18:00:14 -0400 Ray Andraka <randraka@ids.net>
> wrote:
>
> > You should be able to get the spartan parts in small
> >quantities from a reseller such as hamilton avnet.  Try http://www.avnet.com .
>
> Their online purchasing tool only allow to buy from 15 units each
> minimun. Yes, its less than the 26 that the Xilinx local distribuitor
> here want to sell me, but excesive also.
>
> 73's de Luis
>
> mail: melus@esi.us.es
> Ampr: eb7gwl.ampr.org
> http://www.esi.us.es/~melus/   <- Homebrewed Hardware Projects with PCBs



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 17507
Subject: Re: Xilinx Virtex configuration in chunks
From: randy.robinson@xilinx.com (Randy Robinson)
Date: Tue, 03 Aug 1999 14:40:36 GMT
Links: << >>  << T >>  << A >>
On page 10 of XAPP138 (Virtex Configuration and Readback)

In applications where multiple clock cycles may be required
to access the configuration data, before each byte can be
loaded into the SelectMAP interface, data may not be ready
for each consecutive CCLK edge. In such a case the CS
signal may be de-asserted until the next data byte is valid
on the DATA[0:7] pins. This is demonstrated in Figure 7.
While CS is High, the SelectMAP interface will not expect
any data and will ignore all CCLK transitions. However,
WRITE must continue to be asserted while CS is asserted.
If WRITE is High during a positive CCLK transition while
CS is asserted, the FPGA will abort the operation. For
applications that need to de-assert the WRITE signal with-out
de-asserting CS... blah blah

The key sentence is

In such a case the CS
signal may be de-asserted until the next data byte is valid
on the DATA[0:7] pins.

So, yes, CS can be deasserted.  

Go the the Xilinx website, hit the Products button to get to Virtex,
and grab this apnote.  It explains a lot.

Randy


On Tue, 3 Aug 1999 12:41:32 +0200 , Hendrik De Vloed
<hendrik.despam@barco.com> wrote:

>Hello, all,
>
>
>We want to configure a Xilinx Virtex XCV300-4 using the SelectMAP method. 
>However, the data-sheet seems somewhat ambiguous:
>Is it valid to deassert the Chip Select (nCS) once configuration has started?
>
>The application notes all seem to use one continuous chip select signal, 
>asserted at the start, and deasserted once all data has been loaded. The flow 
>chart on page 3-20 of the databook also inhibits a temporary deassertion of nCS 
>during the transmission of configuration data. On the other hand, p. 3-19 
>states "The packet does not have to complete within one assertion of CS, ..."
>
>As we want to use the nCS linked to a processor's address decoder, the nCS 
>would assert once per byte written.
>
>Is this valid?
>
>Greetings,
>
>-- 
>Hendrik De Vloed --  A4000/40 -- Aminet:hard/hack/lcdaemon.lha
>-- Barco Silex FPGA/ASIC design   --   http://www.barco.com --
>***   #include<these_are_my_opinions_legal_mumbo_jumbo.h>  ***
>     <To reply by E-mail, remove the "_hates_spam_" parts>
>
>

Article: 17508
Subject: looking for software
From: z0rbaf@newsguy.com
Date: 3 Aug 1999 10:34:28 -0700
Links: << >>  << T >>  << A >>
Hi
   Please excuse me if this is out-of-line
in this group, but I am looking for some 
software to use on a intel type platform
( '486 machine ).  There are programs for
developing logic for parts such as "82S153"
or "22V10" and I notice that PALAZM & CUPL
are expencive programs that do a lot for the
professional user of this kind of logic but
is there anything that does the job for the
hobbist?  I would like to find a program to
do at least some of the function, & I really
can't pay the bucks for the commercal versions,
Any help here?
                 & thanks
                           Z0rba~the~Geek

Article: 17509
Subject: Re: Partial Reconfiguration?
From: M.Vasilko@computer.org
Date: Tue, 03 Aug 1999 21:23:46 GMT
Links: << >>  << T >>  << A >>
Jim
You might want to check out our WWW DR Hardware Library for relevant
info (includes a technology section with list of past & present
partially reconfigurable devices). Feedback much appreciated.

URL: http://dec.bournemouth.ac.uk/drhw_lib/

Best,
--Milan

In article <7nnne7$42c$1@newshound.csrv.uidaho.edu>,
  jff@mrc.uidaho.edu (Jim Frenzel) wrote:
> I've fallen a bit behind on the latest developments.
>
> Which FPGAs support partial reconfiguration?
>
> I see that the Xilinx Virtex parts do to some degree
> and I assume the XC6200 series is no more (or did some
> company pick that up?) ...
>
> --
> Jim Frenzel, Assoc. Professor      phone:            (208) 885-7532
> Electrical Engineering, BEL 213    fax:              (208) 885-7579
> University of Idaho, MS 1023       email:       jfrenzel@uidaho.edu
> Moscow, ID 83844-1023 USA          www:    www.uidaho.edu/~jfrenzel
>


Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.

Article: 17510
Subject: Re: nuneric_std package in Foundation 1.5
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Tue, 3 Aug 1999 16:21:34 -0700
Links: << >>  << T >>  << A >>
David Dye wrote in message <37A5C4E1.65370B0B@xilinx.com>...
>Andy and everyone, just to confirm:
>
>Synopsys has included the numeric_std package in the IEEE library in their
>3.2 release, which has been out since June.  This version of FPGA Express
>is included in Foundation F2.1i, which began shipping Friday.


Ah!  I was wondering when we'd be able to get Foundation 2.1i.  the Alliance
2.1 has been out for a while.

-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao.edu

"You want partial credit?  You build bridge, bridge falls down - no partial
credit."
-- Dr A. Chang, professor of Mechanical Engineering at Stevens Institute of
Technology



Article: 17511
Subject: Re: Xilinx/Synopsys License Problem
From: Nicholas Brown <nbrownNOT@gulfaccess.com>
Date: Tue, 03 Aug 1999 19:23:11 -0400
Links: << >>  << T >>  << A >>
First of all, Thanks for the help everyone.
The problem was that the file generator must be given the Drive ID that the system boots up on (typicaly C:) as opposed to the drive that the Foundation Series is on. The down side to this is that I only have one more use of the file generator, so I can't reformat my drive (this can change the ID and disable the software) unless I "use up" the last license. Also there is a required patch (an 11.2MB download.) The service pack can be found at:
Ftp://ftp.xilinx.com/pub/swhelp/M1.5_updates/15_service_pack1_nt.zip
and
ftp://ftp.xilinx.com/pub/swhelp/M1.5_updates/15_sp1_ftp1_nt.zip .
Thanks for the help.
-Nick

Dave Vanden Bout wrote:

> Nicholas:
>
> Did you get your Foundation to work?  I don't think you can key off of the D: drive.  You must use the C: drive or your ethernet id #.  You can't change your license file manually.  You will have to go to the xilinx web site and generate a new license with the appropriate C: or ethernet id key.  You can generate up to three licenses at the xilinx site before you get locked out.  Let me know if you run into this problem and I will try to get you another xilinx serial number.
>
> Email us at xess.com or send questions to the xsboard-users mailing list if you have problems like this in the future.  We don't have xilinx's godly power to generate license files but sometimes we can point you in the right direction.
>
> Nicholas Brown wrote:
>
> > Hello,
> >     I have just purchased the Xilinx Foundation Series 1.5 Student
> > Edition, a XS40 and a XS95 board  from Xess Corp. Unfortunately, the
> > license software dosnít seem to work and Xilinx now claims that they
> > donít support the student edition. I was hoping that someone here knows
> > a solution to the problem.
> >     Everything seems to work except the VHDL synthesis. When attempting
> > to synthesize a VHDL entry I get:
> >
> > Pcm :Synopsys server initialization
> > Dpm :Invalid Host(-9,57)
> > Pcm :Cannot find a valid license for Synopsys synthesis
> >
> >     I have spent several hours attempting to get this to work. Initially
> > I
> > used Drive number 0B87-7DBF with the Xilinx license generator which is
> > the id for the D drive where the Foundation Series software resides (as
> > reported by Vol C: in DOS.)
> > This did not work, so I manually changed the license.dat file so the id
> > was 1878-08CD which is the id the master drive, C:. This did not work.
> > Then I downloaded Hostid.exe from Synopsys which gave the host id as
> > f8d709c10000. This also did not work. The Autoexec.bat dose contain:
> > C:\flexlm\license.dat. Any insight to the problem would be appreciated.
> > Thanks in advance
> > -Nick
>
>   ------------------------------------------------------------------------
>
>   Dave Vanden Bout <devb@xess.com>
>   FPGA Product Manager
>   XESS Corp.
>
>   Dave Vanden Bout
>   FPGA Product Manager  <devb@xess.com>
>   XESS Corp.
>   2608 Sweetgum Drive   Fax: (919) 387-1302
>   Apex                  Work: (919) 387-0076
>   NC                    Netscape Conference Address
>   27502
>   USA
>   Additional Information:
>   Last Name  Vanden Bout
>   First Name David
>   Version    2.1



Article: 17512
Subject: Re: looking for software
From: Edwin Naroska <edwin@mira.e-technik.uni-dortmund.de>
Date: Wed, 04 Aug 1999 10:39:26 +0200
Links: << >>  << T >>  << A >>
Hi,

take a look at the "Free and Low-Cost Software" page of  the
Programmable Logic Jump Station:

    http://www.optimagic.com/lowcost.shtml

--
Edwin


z0rbaf@newsguy.com wrote:

> Hi
>    Please excuse me if this is out-of-line
> in this group, but I am looking for some
> software to use on a intel type platform
> ( '486 machine ).  There are programs for
> developing logic for parts such as "82S153"
> or "22V10" and I notice that PALAZM & CUPL
> are expencive programs that do a lot for the
> professional user of this kind of logic but
> is there anything that does the job for the
> hobbist?  I would like to find a program to
> do at least some of the function, & I really
> can't pay the bucks for the commercal versions,
> Any help here?
>                  & thanks
>                            Z0rba~the~Geek

Article: 17513
Subject: Re: Xilinx/Synopsys License Problem
From: Arve Ronning <arve.ronning@thomson-csf.no>
Date: Wed, 04 Aug 1999 12:14:22 +0200
Links: << >>  << T >>  << A >>
Nicholas Brown wrote:
> 
> First of all, Thanks for the help everyone.
> The problem was that the file generator must be given the Drive ID that the 
> system boots up on (typicaly C:) as opposed to the drive that the Foundation 
> Series is on. The down side to this is that I only have one more use of the 
> file generator, so I can't reformat my drive (this can change the ID and 
> disable the software) unless I "use up" the last license. Also there is a 
[snip]

As implied by 'Rickman' in another message, changing a disk's serial number
isn't difficult. It may be hazardous though !!! in case you make a mistake.

**Warning**, potentially destructive procedure ahead. Practice on diskette !

See sample session below, changing the D: serial number from 3028-16AA to
3028-16EE. Note that the second number in the L and W commands is the disk,
0 = A:, 1 = B:, 2 = C:, 3 = D: etc.

----------------------------------------------------------------------------
D:\>vol d:

 Volume in drive D has no label
 Volume Serial Number is 3028-16AA

D:\>debug
-L 100 3 0 1
-D 100
27CC:0100  EB 3E 90 4D 53 57 49 4E-34 2E 31 00 02 20 01 00   .>.MSWIN4.1.. ..
27CC:0110  02 00 02 00 00 F8 C5 00-3F 00 40 00 3F 00 00 00   ........?.@.?...
27CC:0120  01 8C 18 00 80 00 29 AA-16 28 30 20 20 20 20 20   ......)..(0
27CC:0130  20 20 20 20 20 20 46 41-54 31 36 20 20 20 F1 7D         FAT16   .}
27CC:0140  FA 33 C9 8E D1 BC FC 7B-16 07 BD 78 00 C5 76 00   .3.....{...x..v.
27CC:0150  1E 56 16 55 BF 22 05 89-7E 00 89 4E 02 B1 0B FC   .V.U."..~..N....
27CC:0160  F3 A4 06 1F BD 00 7C C6-45 FE 0F 8B 46 18 88 45   ......|.E...F..E
27CC:0170  F9 FB 38 66 24 7C 04 CD-13 72 3C 8A 46 10 98 F7   ..8f$|...r<.F...
-E 127
27CC:0127  AA.EE
27CC:0128  16.     28.     30.
-W 100 3 0 1
-q

D:\>vol

 Volume in drive D has no label
 Volume Serial Number is 3028-16EE

D:\>
----------------------------------------------------------------------------

Article: 17514
Subject: RLOC constraint not interpreted correctly?
From: takehiro@rr.iij4u.or.jp
Date: Wed, 04 Aug 1999 20:33:33 +0900
Links: << >>  << T >>  << A >>
Dear all,

I try to place and route my design on XC4013XL with UCF constraint file
which includes RLOC=R0C0.FFX constraint description.
But the some RLOC constraints(not all!) may be ignored because the
instance attached the RLOC constraint is mapped on Y position of
flipflop in a CLB(same as FFY).
I have no error or warning messages about that UCF description during
translate and map process.
Is there some case that MAP ignores user specified RLOC property?
Please anyone give me advice.

note : I use foundation M1.5.

Thanks,

hiro


Article: 17515
Subject: Re: looking for software
From: dicar@aa.net (Don Matson)
Date: Wed, 04 Aug 1999 17:39:17 GMT
Links: << >>  << T >>  << A >>
Hello,
You will find the maxplusII software is free and will do all that a
hobbist should need.  You can design with either schmatics or text and
can simulate your design with this package.  Go to www.altera.com and
click on the free software icon.

Don Matson

On 3 Aug 1999 10:34:28 -0700, z0rbaf@newsguy.com wrote:

>Hi
>   Please excuse me if this is out-of-line
>in this group, but I am looking for some 
>software to use on a intel type platform
>( '486 machine ).  There are programs for
>developing logic for parts such as "82S153"
>or "22V10" and I notice that PALAZM & CUPL
>are expencive programs that do a lot for the
>professional user of this kind of logic but
>is there anything that does the job for the
>hobbist?  I would like to find a program to
>do at least some of the function, & I really
>can't pay the bucks for the commercal versions,
>Any help here?
>                 & thanks
>                           Z0rba~the~Geek
>

Article: 17516
Subject: ECL IO to Virtex or APEX ?
From: muzok@nospam.pacbell.net (muzo)
Date: 04 Aug 1999 17:59:32 PDT
Links: << >>  << T >>  << A >>
I would like to be able to connect an ECL output device to either of
these FPGAs. Although they offer numerous IO options, ECL is not one
of them. Has anyone done this ? My input signal is around 120 MHz so I
need a way which is not going to degrade it too much. Would using ECL
to TTL converters be prudent for this application ?

muzo

Verilog, ASIC/FPGA and NT Driver Development Consulting (remove nospam from email)
Article: 17517
Subject: Re: ECL IO to Virtex or APEX ?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Thu, 05 Aug 1999 00:47:49 -0400
Links: << >>  << T >>  << A >>
muzo wrote:
> 
> I would like to be able to connect an ECL output device to either of
> these FPGAs. Although they offer numerous IO options, ECL is not one
> of them. Has anyone done this ? My input signal is around 120 MHz so I
> need a way which is not going to degrade it too much. Would using ECL
> to TTL converters be prudent for this application ?
> 
> muzo
> 
> Verilog, ASIC/FPGA and NT Driver Development Consulting (remove nospam from email)

I assume that your signals are sync rather than async. In that case is
might be a little dicey with 8 ns clock rates. The logic delays in a
10H125 hex translator for example, add up to 2.6 ns of skew which might
be excessive for your app. Or you might be able to reclock through a
10H605 register which still adds 2.5 ns of skew, but may reduce the
total delay. You will have to look at your requirements. If you can pass
all of the inputs through a single chip the skew problems go way down. 

I understand that Dynachip makes ECL gate arrays. I have not looked at
them myself, but I have heard that they run fast and are not overly
difficult to work with. I am sure that they are not as large as the
Virtex or APEX parts, but they might get the job done.


-- 

Rick Collins

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Arius - A Signal Processing Solutions Company
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Internet URL http://www.arius.com
Article: 17518
Subject: serial multiplier with LogiCore scaled 1/2 accumulator
From: Ilia Oussorov <fliser6@fli.sh.bosch.de>
Date: Thu, 05 Aug 1999 09:55:10 +0200
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Hello,
Does somebody know, how one can build serial multiplier with LogiCore
scaled by 1/2 acc.
Xilinx writes, that this module is typical for bit serial multiplier but

I miss something as write_enable or shift  input for the accumulator
register (to add only if current factor bit ='1' or to only shift and
not add if current factor bit ='0' ).

Any usefull comments will be appreciated.



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n:              Oussorov;Ilia
org:            Robert Bosch GmbH, FV/FLI
adr:            P.O.Box 10 60 50;;;Stuttgart;;D-70049;Germany
email;internet: fliser6@fli.sh.bosch.de
tel;work:       +49-(0)-711-8117057
tel;fax:        +49-(0)-711-8117602
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--------------44A0079F03195D916024D54F--

Article: 17519
Subject: Re: Watch! [2.2di7.49n]
From: Sabri Berisha <sabri@selwerd.cx>
Date: Thu, 05 Aug 1999 10:29:01 +0000
Links: << >>  << T >>  << A >>
[flup set]

Nicolas Matringe wrote:
> 
> STOP YOUR CROSSPOSTING !!!
> (especially if it's not in english)

The language used was dutch. Some people do not verify their headers
while reading or posting. You however could also set a followup header
:)

-- 
Sabri Berisha	    | http://www.selwerd.cx        |
Check out HIT2000!! | http://www.hit2000.org       |
* My opinion only * | http://www.selwerd.cx/~sabri |
Article: 17520
Subject: [FRANCE] we need "help" with programming a FPGA
From: "B.Thierry" <benedicte.thierry@wanadoo.fr>
Date: Thu, 5 Aug 1999 14:23:59 +0200
Links: << >>  << T >>  << A >>
hello

for a one frame CCD driving, we need "help" with programming a FPGA, behind
a micro-controller

who is itrested ? please answer or send me curiculum vitae only to :
benedicte.thierry@wanadoo.fr


Article: 17521
Subject: Re: serial multiplier with LogiCore scaled 1/2 accumulator
From: Ray Andraka <randraka@ids.net>
Date: Thu, 05 Aug 1999 08:48:58 -0400
Links: << >>  << T >>  << A >>
Look at the multiplier page on my website (under the DSP page).  The first
multiplier discussed is a scaling accumulator multiplier.  There is a drawing
with it.  That example is unsigned.  To make it signed, you need to subtract
the partial product corresponding to the MSB of the serial input instead of
adding it.  You'll see that you really don't need the logicore piece, as all
it is is an accumulator (registered adder with output fed back to one input)
with the feedback path shifted by a bit.

Ilia Oussorov wrote:

> Hello,
> Does somebody know, how one can build serial multiplier with LogiCore
> scaled by 1/2 acc.
> Xilinx writes, that this module is typical for bit serial multiplier but
>
> I miss something as write_enable or shift  input for the accumulator
> register (to add only if current factor bit ='1' or to only shift and
> not add if current factor bit ='0' ).
>
> Any usefull comments will be appreciated.
>

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 17522
Subject: Support of XS40 in Jbits new version
From: "Josan Moreno" <jmorenoz@nexo.es>
Date: Thu, 5 Aug 1999 16:59:23 +0200
Links: << >>  << T >>  << A >>
Hi,
Does it exists a new version of Jbits that supports new cards like XS40 from
XESS?. The last version I know is the v.1.1 (beta).
Thanks.
______________________________

  Jose Antonio Moreno Zamora

  Universidad de Extremadura
    Dpto. de Informatica

   Avda. Universidad, s/n
   10071 - Caceres (SPAIN)
   Vox/Fax: +34-927-257267
   E-mail: joseanmo@unex.es
______________________________


Article: 17523
Subject: Re: Counters
From: "Timothy R. Sloper" <trs@mpinet.net>
Date: Thu, 5 Aug 1999 20:38:21 -0400
Links: << >>  << T >>  << A >>
Synplicity will have no problem synthesizing 64-bit counters. Last night I
was setting up my software and ran a 64-bit increment by 1 counter through
the tools. I was able to place and route the counter achieving a max clock
rate of 98 MHz in an Actel A54SX08-TQ144 (STD).

Tim

Peter SÝrensen <ps@emi.dtu.dk> wrote in message
news:37380535.14B9FFF0@emi.dtu.dk...
> What do you mean by large?
> In many FPGA's you can relative fast counters by using carry logic chains
up to
> say 32 bits. But you must enable the carry logic in both the synthesis and
> sometimes also the palce and route tool. If you need very big counters
like say 64
> bits you need special code as carry chains of this length is not alloved
by
> standard settings and may give too much trouble in routing.
> Make a small counter of 2-4 bits and use MSB Q output as enable for the
remaining
> bits. I have some old code somewhere if this is not enough send me a mail.
>
> Hi Peter
>
>
> "C. Michele Rogers" wrote:
>
> > Hi everyone,
> >
> > Can Synplicity and Leonardo automatically optimize large binary counters
to be
> > fast? Or do I have to recode them?
> >
> > Any help will be highly appreciated.
> >
> > Thanks
> > Michele
>


Article: 17524
Subject: Re: Intel Opportunity
From: hareshk@cadence.com (Haresh Kripalani)
Date: 6 Aug 1999 05:13:14 GMT
Links: << >>  << T >>  << A >>
markx.gregory@intel.com wrote:
: Intel Corp. is looking for hardware design engineers who are interested in
: making the transition into Technical Marketing.  If you're interested in
: hearing more about this opportunity, feel free to e-mail me at
: markx.gregory@intel.com.
: 
: -----------== Posted via Deja News, The Discussion Network ==----------
: http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    


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