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Messages from 15775

Article: 15775
Subject: Re: Placement constraints on LOGIBLOX instances
From: "Jamie Sanderson" <jamie@nortelnetworks.com>
Date: Tue, 13 Apr 1999 14:21:12 -0400
Links: << >>  << T >>  << A >>
Not sure if this suggestion will be useful, but here goes:

In the latest version of Logiblox I have (Version M1.5.25), there is an
attribute called "Use RPMs" in the module selector program. When I set that
to true for RAM blocks, they will then occupy adjacent CLB's in the device.
Looks very nice, and I think runs faster too...

Perhaps someone else will be able to tell you how could proceed without
using this version of Logiblox.

Good luck,
Jamie

Jo Depreitere wrote in message <3713624F.5894CC69@elis.rug.ac.be>...
>Hi,
>
>  is it possible to have more control over the placement of the
>LOGIBLOX instances using placement constraints  (LOC/RLOC) in the
>.UCF file? I've made a 256x8 RAM with LOGIBLOX and after P&R, the
>thing is all over the place.
>
>  I know that it is possible to put constraints on the MEMx_y
>portion of the RAM, but the rest of the logic consists of gates
>and you can't put constraints on gates.
>
>  After studying the structure of the RAM in the .xnf file, I tried
>to fiddle with the .xnf file and put some FMAP's in there. Unfortunately,
>this .xnf file is not used in the mapping phase since the tool does a
>"LogiBlox expansion" on the instance, completely skipping the .xnf
>file and, hence, my RLOC'ed FMAPs.
>
>  Any suggestions?



Article: 15776
Subject: Lowest power for DSP
From: Dave Decker <ddecker@diabloresearch.com>
Date: Tue, 13 Apr 1999 12:57:21 -0700
Links: << >>  << T >>  << A >>
Are there any devices that can do slow DSP (2MHz clock) with as little
power as a Xilinx XC3030L screened for 2.75V operation? This chip is not
really big enough for my application, but has 20uA static current and
the global clock uses about .61uA at 2MHz. at 2.8V) There are no
existing 2.75V screens for larger 3000L parts. (It's hard to get a new
screen on an old chip.)

2.75V allows operation directly off  Lithium/Manganese Dioxide, Li/MnO2
battery.

The application will go to ASIC so a programmable DSP is not a good
match. I wonder if it would work, though. Also, FPGA volume is only a
few tens of thousands while waiting for ASIC. This is why Xilinx doesn't
want to do a new 2.75V screen for a larger 3000L part.

So, should I be looking at some other FPGA family? Can any compete with
the 3030L on power at 2MHz clock rates, run at 2.75V, but hold more DSP
style logic, like decimators etc.? (3030 has 100 CLBs, each with 2 flops
and 2 4input muxes)

Thanks a bunch,

Dave Decker
Diablo Research Co. LLC
ddecker@diabloresearch.com


Article: 15777
Subject: Re: Using the temperature diode on the virtex...
From: tronsmith@my-dejanews.com
Date: Tue, 13 Apr 1999 23:11:29 GMT
Links: << >>  << T >>  << A >>
Go to the Xilinx Answer search page:
http://www.xilinx.com/support/searchtd.htm
Search on Diode, and the #1 answer is:
http://www.xilinx.com/techdocs/5738.htm
which recommends a Maxim part.

Or you could start from diode equation:

I = i0 * [ exp(e*V/k*T)-1 ]
where i0 is characteristic current, e is electron charge,
k is Boltzman's konstant, V in Volts and T in Kelvins.

Then add constant current source and check voltage,
or use constant voltage and check current.

The Maxim part is interesting, claims accuracy to
+/- 3C. It contains an A/D which can be read via
SMB (like IIC ) two wire interface.
Connect the temp sensor up to the Virtex, allow the
Virtex to control its internal clock based on the
temperature...don't know how many apps tolerate
temperature controlled performance though.
Suggested use is to turn on a fan rather than
shut down chip.

I could not find any characterization of the diode
in Xilinx pages.

- John


In article <7evs3e$2d2$1@agate.berkeley.edu>,
  nweaver@hiss.CS.Berkeley.EDU (Nicholas C. Weaver) wrote:
> Is there an application note or some other information about using the
> temperature sensing diode on the Virtex chip?  Specifically, we want
> to implement a failsafe cutoff if the temperature goes too high.
>
> --
> Nicholas C. Weaver                                 nweaver@cs.berkeley.edu
>

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Article: 15778
Subject: Re: bitstream
From: Tom Kean <tom@algotronix.com>
Date: Wed, 14 Apr 1999 00:12:03 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------EAEB47581DBC2C7F54C25ED4
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit



"J. Khatib" wrote:

> Is there any FPGA with documented bit stream?

The Xilinx XC6200 has a fully documented bitstream.


--------------EAEB47581DBC2C7F54C25ED4
Content-Type: text/x-vcard; charset=us-ascii;
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Content-Transfer-Encoding: 7bit
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Content-Disposition: attachment;
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begin:vcard 
n:Kean;Tom
tel;fax:UK +44 131 556 9247
tel;work:UK +44 131 556 9242
x-mozilla-html:TRUE
org:Algotronix Ltd.
adr:;;P.O. Box 23116;Edinburgh;;EH8 8YB;Scotland
version:2.1
email;internet:tom@algotronix.com
title:Director
note:Web Site: www.algotronix.com
x-mozilla-cpt:;4768
fn:Tom Kean
end:vcard

--------------EAEB47581DBC2C7F54C25ED4--

Article: 15779
Subject: Intel Opportunity
From: markx.gregory@intel.com
Date: Wed, 14 Apr 1999 00:11:57 GMT
Links: << >>  << T >>  << A >>
Intel Corp. is looking for hardware design engineers who are interested in
making the transition into Technical Marketing.  If you're interested in
hearing more about this opportunity, feel free to e-mail me at
markx.gregory@intel.com.

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Article: 15780
Subject: VCC Hotworks
From: leskowid@uwplatt.edu (David F. Leskowicz)
Date: 13 Apr 99 20:03:30 CDT
Links: << >>  << T >>  << A >>
Does anyone out there use VCC's Hotworks boards that would be able to answer
some basic questions, as I have been unable to get any response from VCC.
Thanks

-dave


Article: 15781
Subject: Re: VCC Hotworks
From: Steve Casselman <sc@vcc.com>
Date: Tue, 13 Apr 1999 19:19:25 -0700
Links: << >>  << T >>  << A >>
David F. Leskowicz wrote:

> Does anyone out there use VCC's Hotworks boards that would be able to answer
> some basic questions, as I have been unable to get any response from VCC.
> Thanks
>
> -dave

I'm sure there are lots of people that can help.  No one here can
locate your question. Let us hear what you need to know!


--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 15782
Subject: Re: Lowest power for DSP
From: "John Cain" <jjcain@goodnet.com>
Date: Tue, 13 Apr 1999 21:19:07 -0700
Links: << >>  << T >>  << A >>
The Philips coolpld family ( 3.0 - 3.6V - PZ3064 2kgates & PZ3032) may be an
alternate to the Xilinx 3032 Device. The spec sheet indicates a static IDD
of 40ua for the PZ3064 device  with a 2MHZ IDD of 1.3ma. The PZ3032 2MHZ IDD
is specified at 200ua.  For low current battery powered FPGA applications
there are limited choices.

John Cain, Power Processing, Inc.  Phoenix, AZ
jjcain@goodnet.com




Article: 15783
Subject: Re: Does any one want to talk about Dynamic Configuration?
From: Steve Casselman <sc@vcc.com>
Date: Tue, 13 Apr 1999 21:40:08 -0700
Links: << >>  << T >>  << A >>


> OK
> It seems that there are some people want to talk about it.
> What do you want to talk about?
>

If you look at the HOT2 system
http://www.vcc.com/Hotii.html
you will see that it has a configuration
cache that holds 3 configurations (2
for the 4062 board). There is also
a flash that can hold 3 configurations
(11 on the 4062). One these configurations
are load into cache you use the API to
reconfigure (RtrCache(2); will reconfigure
off the third configuration in the sram
cache).  Once the board reconfigures
since it contains the LogiCore PCI interface
we reload the pci base address registers and
off you go. This takes about 200ms for the
Spartan 40 and 600ms for the 4062.

The configuration cache manager (ccm) is
loaded with the flash or sram data address
and then the ccm serializes the data and
the FPGA. If the user trys to load a bad configuration
the ccm will panic and reboot from its base
(flash 0) configuration and the API will flag an
error.

Configuration cache is important. The one thing
that processors do very well that FPGA do really
badly at is that processor know intrinsically how
to get their next configuration( uh set of instructions).

FPGAs really only know how to fetch one set of instructions
(uh configration).

Check out my patent
http://www.patents.ibm.com/details?pn10=US05684980
(don't let the date fool you the real priority date is june 7, 1992
it is the oldest patent on reconfigurable computing)

You might also check out
http://www.vcc.com/hist1.html
Which shows a little history (where were you in '87?:-)


--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 15784
Subject: Re: FPGA vs CPLD? Any Experts out there?
From: Weri Kuolstad <winsome24@my-dejanews.com>
Date: Wed, 14 Apr 1999 05:25:46 GMT
Links: << >>  << T >>  << A >>
Both of your responses were effervescent with thorough professionalism at the
art of designing to an FPGA technology. Your advice would definitely count in
my work toward achieving a solution keeping in mind the two design goals that
I specified earlier. And also I would like to get back to you with results
from time to time. Would you mind?

The new Michael D. Ciletti book is called "Modelling, Synthesis, and Rapid
Prototyping with the Verilog HDL" - Prentice Hall. ISBN 0-13-977398-3
TK7885.7.C55 1999

It has some cool stuff on behavioral code synthesis.

The second note that you posted will be of especial help to me.
Thanks a lot.
WK.

In article <7eucdq$ngk$1@news-2.news.gte.net>,
  "Jan Gray" <jsgray@acm.org.nospam> wrote:
> Jan Gray wrote in message <7ettgk$ddr$1@news-2.news.gte.net>...
> >Only when you understand where (and how and how many of) your rams, adders,
> >registers, muxes, etc. should fall on the die, only then, should you write
> >your first line of Verilog or draw your first FDCE.
>
> I don't like my own advice here, so let me try again.
>
> Implementing a processor or other substantial design is an iterative process
> with subproblems which require analysis and experimentation.  The more
> expert you are with your tools and with the device architecture, the less
> experimentation you'll need.  If you're new to FPGA design, I think taking
> some time to try out different solutions to the subproblems will help to
> save time overall and achieve a better result.
>
> Some of the subproblems to investigate include:
> * how to implement a register file?  a 2 read / 1 write port register file?
> * how to source an operand from a register or an immediate field
> * how to implement an ALU? a shifter?
> * how to multiplex the many results (incl. ALU, shifts, loads, sign exts
> (lbs), jal's)
> * how to implement zero/negative/carry/overflow detect?
> * what is the external memory or on-chip bus interface like?
> * how to implement load/store byte lane alignment logic?
> * how to implement an instruction register? a program counter? incrementing
> it? branch displacements?
> * how to pipeline the design? how many stages are beneficial? how to stall
> pipe? how to annul insns?
> * how to deal with pipeline hazards? memory not ready? branch/jump shadows?
> data hazards?
> * where to implement the effective address adder?
> * should memory be 1- or 2- ported? how to mux eff. addr. with PC?
> * how to do interrupts and return from interrupt?
> * what is the clock discipline? rising or both edges? 1 or multiple clocks
> per insn?
> * what are the critical paths? what is the feasible cycle time? what is the
> required cycle time?
> * is any retiming needed?
>
> Some of these analyses will benefit from actually designing the subunit and
> observing what the tools produce, including layouts and delays (EPIC /
> static timing analysis). And trying some alternatives.
>
> Then you'll know approximately how much area and time it takes to do a
> register file writeback and read vs. an add vs. a wide-mux vs. a 32-bit zero
> detector and will be able to make intelligent tradeoffs.
>
> Have fun!
> Jan.
>
>

-----------== Posted via Deja News, The Discussion Network ==----------
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Article: 15785
Subject: Re: Lattice
From: Tim Forcer <tmf@ecs.soton.ac.uk.nojunk>
Date: Wed, 14 Apr 1999 09:19:12 +0100
Links: << >>  << T >>  << A >>
NO-SPAM damiano wrote:
> 
> What do you think about lattice?

Useful chips at reasonable prices. pDS software awful.  isp
documentation excellent.

-- 
Tim Forcer               tmf@ecs.soton.ac.uk
The University of Southampton, UK

The University is not responsible for my opinions
Article: 15786
Subject: Re: One hot comes up cold
From: "Bill" <bb@alphadata.co.uk>
Date: Wed, 14 Apr 1999 12:41:04 +0100
Links: << >>  << T >>  << A >>
Ask Xilinx about the reset delay across your device - that may be the
problem.

George E. Smith, Jr wrote in message <371243DE.97E881C7@bellsouth.net>...
>Hi
> Has anyone experienced problems with one hot FSM's not getting there
>initial state
>set? I'm useing Xilinx Alliance 1.5i and Synplicity. Seems that a reset
>ff is being selected
>instead of a preset.
>



Article: 15787
Subject: Obsolete Xilinx series - how to use them?
From: Gianni Comoretto <comore@arcetri.astro.it>
Date: Wed, 14 Apr 1999 13:44:53 +0200
Links: << >>  << T >>  << A >>
I have several Xilinx chips, series 4000 and 4000A
None of the current support tools are able to implement a design using 
these chips, the first supported family is 4000E.

It is possible to use a bitstream for a 40xxE in a 40XXA? Has anybody
tried this?

Thank you
[if possible, send answer by E-mail]
-- 
Gianni Comoretto      			Osservatorio Astrofisico di Arcetri 
gcomoretto@arcetri.astro.it		Largo E. Fermi 5 
http://www.arcetri.astro.it/~comore	50125 Firenze - ITALY
Article: 15788
Subject: SUBSCRIBE
From: "J. Khatib" <khatib@ieee.org>
Date: Wed, 14 Apr 1999 15:09:27 +0300
Links: << >>  << T >>  << A >>
SUBSCRIBE khatib@ieee.org
Article: 15789
Subject: Re: FIFO
From: Eli Keren <elik@dsi.co.il>
Date: Wed, 14 Apr 1999 15:19:47 +0300
Links: << >>  << T >>  << A >>
Hello All !

Yes you can use ALTERA devices from FPGA series ,like 10K10-X . If you
need more information contact with me.

regards


vanan wrote:

> Hi!
>
> Anyone know about 8bit x 1K FIFO can implemented in FPGA ?
>
> If yes , Pls give me the vendor and part number.
>
> Any application note ? will be great .
>
> Thanks
>
> Svana

Article: 15790
Subject: Re: SUBSCRIBE
From: julius kusuma <kusuma@ecn.purdue.edu>
Date: Wed, 14 Apr 1999 08:38:05 -0500
Links: << >>  << T >>  << A >>
Khatib,

these are all newsgroups, not mailing lists. you need to use a news
reader with
access to a news server (like what you did here), or use dejanews 
(http://www.dejanews.com). you and only you can subscribe and
unsubscribe
to newsgroups. there's no control message. 

for introduction on what newsgroups are all about, please read:

LEARN about newsgroups at the news.newusers.questions Web site: 
    http://www.geocities.com/ResearchTriangle/Lab/6882/

julius


J. Khatib wrote:
> 
> SUBSCRIBE khatib@ieee.org

-- 
julius kusuma
purdue university communication research lab
http://shay.ecn.purdue.edu/~kusuma
news.newusers.questions moderation board
Article: 15791
Subject: Re: Obsolete Xilinx series - how to use them?
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 14 Apr 1999 09:23:38 -0700
Links: << >>  << T >>  << A >>
Gianni Comoretto wrote:

> It is possible to use a bitstream for a 40xxE in a 40XXA? Has anybody
> tried this?

   No, do not even try! The XC4000A is a reduced-interconnect subset of the
XC4000. As you can see in its data sheet, it has fewer bits in the bitstream.
So, although you can implement the same functionality as in XC4000( accepting
the more limited interconnects ), the software is different. You have to use the
old software.

Peter Alfke, Xilinx Applications

Article: 15792
Subject: Re: bitstream
From: Jamie Lokier <spamfilter.apr1999@tantalophile.demon.co.uk>
Date: 14 Apr 1999 19:46:25 +0200
Links: << >>  << T >>  << A >>
> "J. Khatib" wrote:
>> Is there any FPGA with documented bit stream?

Tom Kean writes:
> The Xilinx XC6200 has a fully documented bitstream.

Are there any others?

-- Jamie
Article: 15793
Subject: What to see in New York?
From: ricso@ludd.luth.se (Rickard Norberg)
Date: Wed, 14 Apr 1999 18:00:33 GMT
Links: << >>  << T >>  << A >>
Hi everyone,

The subject is "What to see in New York" and the things that are on
the list of interest are Science and Electronics. The reason I am
asking you is that my class, 13 people, is planing a trip over the
Atlantic to visit New York at the end of your project in industrial
electronics. We are about to take your Master in Industrial
Electronics, at Luleň University of Technology, this fall so the
companies that we would like to visit should have a connection to our
field. We have looked at the Brookenhaven Laboratory and Locked Martin
which both are interesting to us. The reason why we are staying in New
York is purely a question of economics.

Has anybody any good suggestion of other companies/organisations that
might be of interest to us?

The project that we currently are working on is an instrument that
will be monitored over the Internet (IP-meter) via an Ethernet
connection. The companies that we are working with are Abelko
Innovation, Antenna, D-Flow, and Hans Fald Elektronik.

Sincerely yours,
Rickard Norberg, ElTek

Article: 15794
Subject: CHES CFP
From: Christof Paar <christof@ece.wpi.edu>
Date: Wed, 14 Apr 1999 14:17:24 -0400
Links: << >>  << T >>  << A >>
This the the last and final CFP for CHES. A registration form is at the
end of this mail.
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

           Workshop on Cryptographic Hardware and Embedded Systems
                                   (CHES)
                   http://ece.WPI.EDU/Research/crypt/ches

                       Worcester Polytechnic Institute
                       Worcester, Massachusetts, USA
                            August 12 & 13, 1999

                       Third and Final Call for Papers

General Information

The focus of this workshop is on all aspects of cryptographic hardware and
embedded system design. The workshop will be a forum of new results from
the research community as well as from the industry. Of special interest
are contributions that describe new methods for efficient hardware
implementations and high-speed software for embedded systems, e.g., smart
cards, microprocessors, DSPs, etc. We hope that the workshop will help to
fill the gap between the cryptography research community and the
application areas of cryptography. Consequently, we encourage submission
from academia, industry, and other organizations. All submitted papers
will be reviewed.

The topics of interest include but are not limited to:

   * Computer architectures for public-key cryptosystems
   * Computer architectures for secret-key cryptosystems
   * Reconfigurable computing and applications in cryptography
   * Cryptographic processors and co-processors
   * Modular and Galois field arithmetic architectures
   * Tamper resistance on the chip and board level
   * Architectures for smart cards
   * Tamper resistance for smart cards
   * Efficient algorithms for embedded processors
   * Special-purpose hardware for cryptanalysis
   * Fast network encryption
   * True and pseudo random number generators

Mailing List

If you want to receive emails with subsequent Call for Papers and
registration information, please send a brief mail to ches@ece.orst.edu.

Instructions for Authors

Authors are invited to submit original papers. The preferred submission
form is by electronic mail to ches@ece.orst.edu. Papers should be
formatted in 12pt type and not exceed 12 pages (not including the title
page and the bibliography). The title page should contain the author's
name, address (including email address and an indication of the
corresponding author), an abstract, and a small list of key words. Please
submit the paper in Postscript or PDF. We recommend that you generate the
PS or PDF file using LaTeX, however, MS Word is also acceptable. All
submissions will be refereed.

Only original research contributions will be considered. Submissions must
not substantially duplicate work that any of the authors have published
elsewhere or have submitted in parallel to any other conferences or
workshops that have proceedings.

Workshop Proceedings

The post-proceedings will be published in Springer-Verlag's Lecture Notes
in Computer Science (LNCS) series. Notice that in order to be included in
the proceedings, the authors of an accepted paper must guarantee to
present their contribution at the workshop.

Important Dates

 Submission Deadline:          April 30th, 1999.
 Acceptance Notification:      June 15th, 1999.
 Final Version due:            July 15th, 1999.
 Workshop:                     August 12th & 13th, 1999.
=20
NOTES: The CHES dates August 12 & 13 are the Thursday & Friday preceding
       CRYPTO '99 which starts on August 15.

Invited Speakers

Dale Hopkins, Compaq - Atalla, USA.
=09     "Design of Hardware Encryption Systems for e-Commerce Applications.=
"

David Naccache, Gemplus, France.
=09       "Significance Tests and Hardware Leakage."

Brian Snow, National Security Agency, USA.
=09    "We Need Assurance."

Eberhard von Faber, Debis IT Security Services, Germany.
=09            "Security Evaluation Schemes for the Public and Private=20
=09=09     Market with a Focus on Smart Card Systems."

Colin D. Walter, Computation Department - UMIST, U.K.
                 "An Overview of Montgomery's Multiplication Technique:=20
                  How to make it Smaller and Faster."

Program Chairs

All correspondence and/or questions should be directed to either of the
Program Chairs:

 Cetin Kaya Koc                       Christof Paar
 Dept. of Electrical & Computer       Dept. of Electrical & Computer
 Engineering                          Engineering
 Oregon State University              Worcester Polytechnic Institute
 Corvallis, Oregon 97331, USA         Worcester, MA 01609, USA
 Phone: +1 541 737 4853               Phone: +1 508 831 5061
 Fax: +1 541 737 1300                 Fax: +1 508 831 5491
 Email: Koc@ece.orst.edu              Email: christof@ece.wpi.edu

Program Committee

Gordon Agnew,  University of Waterloo, Canada
David Aucsmith,   Intel Corporation, USA
Ernie Brickell,  CertCo, USA
Wayne Burleson,   University of Massachusetts at Amherst, USA
Burt Kaliski,   RSA Laboratories, USA
Jean-Jacques Quisquater,   Universit=E9 Catholique de Louvain, Belgium
Christoph Ruland,   University of Siegen, Germany
Victor Shoup,   IBM Research, Switzerland
Michael Wiener,   Entrust Technologies, Canada

Location

WPI is in Worcester, the second largest city in New England. The city is
80 km (50 miles) West of Boston and 280 km (175 miles) North-East of New
York City.

Worcester is home to a wealth of cultural treasures, many of which are
just a short distance from WPI. These include the historic Higgins Armory
Museum, which houses one of the world's largest collections of armor; the
EcoTarium (formerly New England Science Center), one of the only museums
in the country dedicated to environmental education; and the beautifully
restored Mechanics Hall, one of America's finest concert halls. The
Worcester Art Museum, holding one of the nation's finest collections, and
the world-renowned American Antiquarian Society, with the largest
collection of items printed during the nation's colonial period, are
within two blocks of the WPI campus. Worcester is also well known for its
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August 12 & 13, 1999

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Article: 15795
Subject: Re: Anyone using FPGA Express 'Time Tracker' option?
From: Todd Kline <todd@wgate.com>
Date: Wed, 14 Apr 1999 18:21:20 GMT
Links: << >>  << T >>  << A >>
Well ... it's a mixed blessing.  What it identifies as a "critical path" or a
path exceeding the time-spec is not always correct.  It is easy to use and does
give you a good idea of POTENTIAL problems, but because the timing in the back
end tool varies so much, you could end up fixing problems which are not really
there.

The latest version of PAR plus a beefy PC have reduced my run times to less
then 2 hours.  I would rather work on some other task for 2 hours and then fix
only real problems identified by PAR.

That said, it does give you useful look inside of the design and the structures
generated by FPGA Express.  Get a demo copy and take it for a drive.

Todd

Austin Franklin wrote:

> Hi,
>
> Anyone using the FPGA Express 'Time Tracker' option?  If so, is it a useful
> option?  It's almost the same price as the base product!
>
> Opinions (on this subject ;-) greatly appreciated!
>
> Thanks,
>
> Austin Franklin
> austin@darkroom.com

Article: 15796
Subject: Re: simulator
From: Todd Kline <todd@wgate.com>
Date: Wed, 14 Apr 1999 18:28:34 GMT
Links: << >>  << T >>  << A >>
Do you want to do gate based or language based simulation?

1.) Gate based (i.e. schematic)
  Orcad
  VIEWlogic
  Xilinx Foundation (Aldec based) - Xilinx only
  MaxPlus - Altera Only

2.) Language Based
  Model Technology (VHDL/Verilog)
  VIEWlogic, SpeedWave/VCS (VHDL/Verilog)
  Xilinx Foundation (Aldec based) - Xilinx only
  MaxPlus - Altera only

wathelet wrote:

> hi,
>
> I'm getting interested in FPGA, particularly evolvable type. Is there a
> software package that can simulate an FPGA that I could use to do
> experiments on, instead of bying the hardware and connecting it to a PC
> (which is all I've got).
>
> R. Wathelet

Article: 15797
Subject: Re: bitstream
From: Steve Casselman <sc@vcc.com>
Date: Wed, 14 Apr 1999 12:43:35 -0700
Links: << >>  << T >>  << A >>
Jamie Lokier wrote:

> > "J. Khatib" wrote:
> >> Is there any FPGA with documented bit stream?
>
> Tom Kean writes:
> > The Xilinx XC6200 has a fully documented bitstream.
>
> Are there any others?
>
> -- Jamie

  From what I here the Virtex will soon have lots of documentation
on the bit stream.  Also you don't really need the fully documented
bitstream if you have and API that allows you to manipulate the bit
stream
(ie JBITS http://www.xilinx.com/products/software/sx/sxpresso.html#JBITS )




--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 15798
Subject: Re: Info about FPGA/PLD
From: Steve Casselman <sc@vcc.com>
Date: Wed, 14 Apr 1999 13:06:15 -0700
Links: << >>  << T >>  << A >>
Hernan wrote:

> Ray Andraka wrote:
>
> > Actually in that case, I would have preferred to have a SRAM based FPGA in
> > there, but not its PROM.  In the event of a incident where the equipment
> > might wind up in the wrong hands, simply removing power or hitting the
> > program pin would wipe out the SRAM and there would be no chance of the
> > enemy even getting one working copy to use or study.  In that case, the
> > FPGA would be programmed sometime before the mission, so that the only
> > copy of the program on board is the one in the FPGA.
>
> Can you imagine the technicians in the military base using byteblaster and
> xchecker cables
> while they are pumping gas into the fighers and bombers?
> It would be pretty amusing to see a critical mission aborted because DONE does
> not
> go high.
>
> Just a deep thought :)
>

They do this in the tomahawk cruise missile. They
load the fpgas just before launch.

--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 15799
Subject: Re: 75% PAL video bars
From: Todd Kline <todd@wgate.com>
Date: Wed, 14 Apr 1999 20:23:16 GMT
Links: << >>  << T >>  << A >>

--------------C89AC26ECE44ECFB27356E1F
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hi Alessandro,

Can you get a copy of "Video Demystified" by Keith Jack (Hightext
Publications) or some other such book?  There are many little details in
generating the base timing signals which requires good documentation.

I assume you only need to support the 625 line PAL with a 4.43361875 MHz
color-subcarrier (csc) frequency (Fsc) and you will be feeding an 8-bit A/D.

There are three basic problems:

1.) Generate the base composite video (CV) signal.  This is done with two
counters, one to count horizontal pixel ticks, and another to count lines.
Decode these counters to generate the edge transitions and gating signals.

2.) Next you have to generate the color-subcarrier (a sine wave) and the
burst signal and insert the burst signal into the CV signal on the proper
lines at the proper location.  For PAL, the burst is rotated +/- 135 degrees
from the csc.  The +/- component is called the PAL switch.  If not handled
properly, the PAL switch will drive you batty.  =80

The csc frequency and the horizontal frequency are related as follows:

Fsc = (1135/4 + 1/625) * Fh, where Fh = horizontal line frequency

1135/4=283.75 => the .75 causes the csc to drift backwards by 90 degrees per
line,

1/625 => every frame (i.e. two fields) an extra cycle has accumulated.

Both of these factors will conspire to make your life interesting.  The
clock frequency you select to generate your video will dictate how you
manage these two factors.  If you select a clock running at 4xFsc, your csc
generation is easy, but you need to add two extra clocks (1137) at the end
of each field to "catch-up" to the 1/625 term which you are ignoring.  You
can also run at 13.5 MHz but you will need sin/cos look-up tables.  This is
O.K. for FPGA's.  It is not appropriate for PLD's.

3.) Finally, you have:

Em = E'y + E'v * sin(2nFsc') +/- E'v * cos(2nFsc') = Yuck!

It's not really as bad as it looks.  The +/- comes from the PAL switch
again.  The sin and cos are the color-subcarriers.  E'y, E'v, and E'v are
the YUV components of the video.  If running at 4xFsc, the sin/cos
multiplies become simple shift/add functions.  If running at 13.5MHz, you
need real multipliers.

The Em term then gets added to the CV signal from 2.


75% amplitude, 100% saturation color bars:
   White  Yellow  Cyan  Green  Magenta  Red  Blue  Black
Y   137     91     72     60     42      31   12     0
U    0     -45     15    -30     30     -15   45     0
V    0      10    -63    -53     53      63  -10     0

I repeat, GET GOOD DOCUMENTATION.

Hope this helps to get you started.

Todd

Alessandro Caserta wrote:

> Hello to everyone who can help.
> I would like to implement a PAL cinescope (PAL monitor 75% color BAR)
> using a PLD alone or in conjunction with an EPROM, does any experienced
> programmer of such devises know how to implement such a thing? could you
> help in this "to me" very important matter ?
>
> the second Q. may be stupid. any one knows what is the differences
> between microcontrollers and EPROMs, which is better?
>
> reply to following emails:
>
> alcasert@tin.it
> Alessandro.Caserta@orbit.net
>
> solong and onece again thanks.

--------------C89AC26ECE44ECFB27356E1F
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Hi Alessandro,
<p>Can you get a copy of "Video Demystified" by Keith Jack (Hightext Publications)
or some other such book?&nbsp; There are many little details in generating
the base timing signals which requires good documentation.
<p>I assume you only need to support the 625 line PAL with a 4.43361875
MHz color-subcarrier (csc) frequency (Fsc) and you will be feeding an 8-bit
A/D.
<p>There are three basic problems:
<p>1.) Generate the base composite video (CV) signal.&nbsp; This is done
with two counters, one to count horizontal pixel ticks, and another to
count lines.&nbsp; Decode these counters to generate the edge transitions
and gating signals.
<p>2.) Next you have to generate the color-subcarrier (a sine wave) and
the burst signal and insert the burst signal into the CV signal on the
proper lines at the proper location.&nbsp; For PAL, the burst is rotated
+/- 135 degrees from the csc.&nbsp; The +/- component is called the PAL
switch.&nbsp; If not handled properly, the PAL switch will drive you batty.&nbsp;
=80
<p>The csc frequency and the horizontal frequency are related as follows:
<p>Fsc = (1135/4 + 1/625) * Fh, where Fh = horizontal line frequency
<p>1135/4=283.75 => the .75 causes the csc to drift backwards by 90 degrees
per line,
<p>1/625 => every frame (i.e. two fields) an extra cycle has accumulated.
<p>Both of these factors will conspire to make your life interesting.&nbsp;
The clock frequency you select to generate your video will dictate how
you manage these two factors.&nbsp; If you select a clock running at 4xFsc,
your csc generation is easy, but you need to add two extra clocks (1137)
at the end of each field to "catch-up" to the 1/625 term which you are
ignoring.&nbsp; You can also run at 13.5 MHz but you will need sin/cos
look-up tables.&nbsp; This is O.K. for FPGA's.&nbsp; It is not appropriate
for PLD's.
<p>3.) Finally, you have:
<p>Em = E'y + E'v * sin(2nFsc') +/- E'v * cos(2nFsc') = Yuck!
<p>It's not really as bad as it looks.&nbsp; The +/- comes from the PAL
switch again.&nbsp; The sin and cos are the color-subcarriers.&nbsp; E'y,
E'v, and E'v are the YUV components of the video.&nbsp; If running at 4xFsc,
the sin/cos multiplies become simple shift/add functions.&nbsp; If running
at 13.5MHz, you need real multipliers.
<p>The Em term then gets added to the CV signal from 2.
<br>&nbsp;
<p>75% amplitude, 100% saturation color bars:
<br><tt>&nbsp;&nbsp; White&nbsp; Yellow&nbsp; Cyan&nbsp; Green&nbsp; Magenta&nbsp;
Red&nbsp; Blue&nbsp; Black</tt>
<br><tt>Y&nbsp;&nbsp; 137&nbsp;&nbsp;&nbsp;&nbsp; 91&nbsp;&nbsp;&nbsp;&nbsp;
72&nbsp;&nbsp;&nbsp;&nbsp; 60&nbsp;&nbsp;&nbsp;&nbsp; 42&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
31&nbsp;&nbsp; 12&nbsp;&nbsp;&nbsp;&nbsp; 0</tt>
<br><tt>U&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp; -45&nbsp;&nbsp;&nbsp;&nbsp;
15&nbsp;&nbsp;&nbsp; -30&nbsp;&nbsp;&nbsp;&nbsp; 30&nbsp;&nbsp;&nbsp;&nbsp;
-15&nbsp;&nbsp; 45&nbsp;&nbsp;&nbsp;&nbsp; 0</tt>
<br><tt>V&nbsp;&nbsp;&nbsp; 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 10&nbsp;&nbsp;&nbsp;
-63&nbsp;&nbsp;&nbsp; -53&nbsp;&nbsp;&nbsp;&nbsp; 53&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
63&nbsp; -10&nbsp;&nbsp;&nbsp;&nbsp; 0</tt>
<p>I repeat, GET GOOD DOCUMENTATION.
<p>Hope this helps to get you started.
<p>Todd
<p>Alessandro Caserta wrote:
<blockquote TYPE=CITE>Hello to everyone who can help.
<br>I would like to implement a PAL cinescope (PAL monitor 75% color BAR)
<br>using a PLD alone or in conjunction with an EPROM, does any experienced
<br>programmer of such devises know how to implement such a thing? could
you
<br>help in this "to me" very important matter ?
<p>the second Q. may be stupid. any one knows what is the differences
<br>between microcontrollers and EPROMs, which is better?
<p>reply to following emails:
<p>alcasert@tin.it
<br>Alessandro.Caserta@orbit.net
<p>solong and onece again thanks.</blockquote>
</html>

--------------C89AC26ECE44ECFB27356E1F--



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