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Can anyone help with this? I've got an XCV300, and all the I/O is LVTTL. I need a lot of I/O pins, and so I'm using all the VREFs as I/O, since you don't need a VREF for LVTTL. So far, so good... except that there's some small print in the libraries guide that says: "The configuration pins on a Virtex device are on the right side of the chip. When configuring the device through a serial prom the user is required to use a VREF of 3.3V in the two banks on the right hand side of the chip. If the user is not configuring the device through a serial prom, the VREF requirement is dependent upon the configuration source". I'm using master serial mode - does this mean that I have to connect these 8 VREFs to 3.3V, making them unusable for I/O? If so, why? This doesn't seem to make sense. Thanks EvanArticle: 15926
Hi!
--
Arnaldo Oliveira <arnaldo@ua.pt>
>
> I need a EEPROM to program a Xilinx XC4010XL FPGA.
> This device requires a 283,424 bits memory for full programming.
> Atmel has "FPGA Configuration Memories" with 512Kbit and 1Mbit
> but the package I need is not available (PDIP8).
> Could someone please tell me the names of other companies which
> supply these memories in a PDIP8 package?
> Thanks.
Information was on the yesterday's seminar.
New Product Introduction
FPGA Configurators
Product Tape Out Samples Production
17C/LV512/010/A 6/99 9/99 10/99
Shrink to 8-pin DIP
^^^^^^^^^
Contact with the ATMEL Corp., if want to hear more details.
> Arnaldo Oliveira
> Dep. de Electronica e Telec. - Univ. de Aveiro
> Campus Universitario
> 3810 Aveiro
> Portugal
> tel.: +351 34 370200 fax.: +351 34 381128
> email: arnaldo@ua.pt
Bye!
<< Pardon, I mildly panick!
Kuznetsov Dmitry, Moscow, http://www.orc.ru/~dkuzn/index.htm
Alias http://attend.to/dkuzn
Article: 15927On Tue, 20 Apr 1999 19:14:20 GMT, Alan Chan <achan@designpr.com> wrote: >Hi, > >I am trying to run my Virtex xcv300 design using Synplify and Xilinx >Alliance. After place and route, I always get the same error message >saying "5 out of 4 GCLKs" used. My design uses only one global clock and >I have instantiated one DLL Macro BUFGDLL in my RTL source. The 50 MHz >clock is connected one of the 4 clock pins, and the rest are used as >normal I/Os. There is also a synchronous reset that is connected to all >flip-flops. Can anyone tell me how to get rid of this error? Many thanks >in advance! > >Regards, >Alan > GCK0/1/2/3 are dedicated pins - you can't use them for normal I/O. Sounds like you've got one on your 50MHz clock, one on the BUFGDLL, and three other ones on the other GCK pins. EvanArticle: 15928
In article <371e2f10.5120875@news.dial.pipex.com>, <ems@riverside-machines.com.NOSPAM> wrote: >"The configuration pins on a Virtex device are on the right side of >the chip. When configuring the device through a serial prom the user >is required to use a VREF of 3.3V in the two banks on the right hand >side of the chip. If the user is not configuring the device through a >serial prom, the VREF requirement is dependent upon the configuration >source". > This was a typo in the libraries guide. Replace VREF with VCCO. EdArticle: 15929
According to the Virtex data sheet, the dedicated clock pins can be used as normal inputs, but not I/Os. I have solved the the problem by replacing BUFGDLL with IBUFG, CLKDLL and BUFG, and ended up with 4 instances of BUFGs only. Before the change, Synplify treated BUFGDLL as a single instance and it generated 1 BUFGDLL plus 4 BUFGs. Then, Xilinx Alliance would generate 5 GCLKs! Leonardo Spectrum doesn't have any problem with that. I was confirmed by Xilinx people that there is a bug in Synplify, and will be fixed in the new release. Alan ems@riverside-machines.com.NOSPAM wrote: > > > GCK0/1/2/3 are dedicated pins - you can't use them for normal I/O. > Sounds like you've got one on your 50MHz clock, one on the BUFGDLL, > and three other ones on the other GCK pins. > > EvanArticle: 15930
http://www.latticesemi.com/whatnew/prvantis.html Cheers Terry...Article: 15931
J Mills writes: > 1) Will the lookup tables behave well from an asynchronous point of view. > ie. a single transition at an input causes one or zero transitions at > the output. I seem to remember that Xilinx 4000-series devices had such a > specification, but the Altera documentation I have doesn't say. Yes. Look harder. Can't remember where :-) but it's in the on-line documentation with Maxplus2 and its been discussed here before. > 2) Is there any possibility of damaging the chip by downloading a > pathological oscillating design? It must be student-proof. (Or at least > student-resistant) Sorry, don't know. I'd expect it depends on how fast the oscillations are -- i.e., if the current due to switching at a node is very high because of rapid switching it might get unhappy. I think you can check for designs that will oscillate with the Design Doctor which is part of Maxplus2. If you're doing self-timed asynchronous logic, e.g. as in a microprocessor you might find Design Doctor doesn't help, as those things can be deliberately pathological in their oscillations :-) [But slow enough so as not to damage the device]. -- JamieArticle: 15932
I have acquired a design that has some circuitry that remains powered while the rest of the logic can be power cycled independently. As it turns out, an Altera FLEX 8000 FPGA that remains powered-on shows a significant increase in current consumption when the rest of the circuit is powered-off. The current increase occurs when the +5VDC drops to approximately 1.5V. And, Altera has spec'd a maximum input rise/fall time of 40ns for the FLEX 8000 family. Now, my question. I thought that it might be possible to gate the inputs with a power inhibit signal to reduce the current drain. That doesn't seem to work, although maybe I am wondering if I may not be implementing what I want correctly. Anyone else run into this and know more about my options? One thing that works is to place a separate tri-state buffer on the inputs and disable the buffer with the power inhibit signal. I also place pull-ups on the line between the buffer and FPGA, but I haven't checked to see if this is necessary. Also, I was wondering if anyone knew what the exact mechanism for this behavior was? Clearly, the FPGA is sensitive when the input at the I/O pin is hovering at or about the transistion region. Would this be internal oscillation or something else? Dan Jones -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15933
On Wed, 21 Apr 1999 23:13:59 GMT, dmjones6040@my-dejanews.com wrote: >I have acquired a design that has some circuitry that remains powered >while the rest of the logic can be power cycled independently. As it >turns out, an Altera FLEX 8000 FPGA that remains powered-on shows a >significant increase in current consumption when the rest of the circuit >is powered-off. The current increase occurs when the +5VDC drops to >approximately 1.5V. And, Altera has spec'd a maximum input rise/fall time >of 40ns for the FLEX 8000 family. CMOS device input buffers are typically constructed with a P- and N-channel totem pole, with the P-channel FET connected to the Vcc rail and the N-channel FET to the ground rail; the input signal is fed to the gates of both devices. If the input is close to the Vcc rail, the P channel FET is off and the N channel FET is on; just the opposite occurs if the input signal is close to ground. In either case, there's little or no quiescent current flowing from Vcc to ground. If the input buffer is TTL-compatibile, the FETs are designed so that one begins turning on and the other begins turning off somewhere around--you guessed it--1.5V. The on/off transitions are gradual, so that if you have an input hovering at 1.5V, both transistors are partly on, and some current, perhaps a considerable amount, will flow from Vcc to ground. (In fact, most TTL-compatible CMOS inputs on 5V parts will exhibit some Vcc-to-ground current flow even if the input is as high as 3.2V to 3.4V. This current, called delta Icc, is spec'ed in some data sheets.) There are other ways to construct TTL-compatible CMOS inputs, so not all device inputs will behave like this. But most do. Could you damage the FPGA by holding its inputs at 1.5V indefinitely? I doubt it, but it could be tough to get a guarantee to that effect. And I can tell you from experience that if you hold the input of a high-drive (combinatorial) buffer, like an ABT device, in the threshold region too long, the output may go to a halfway level, but at a much higher current drain, possibly destroying the part. Some fun. Bob Perlman ----------------------------------------------------- Bob Perlman Cambrian Design Works Digital Design, Signal Integrity http://www.best.com/~bobperl/cdw.htm Send e-mail replies to best<dot>com, username bobperl -----------------------------------------------------Article: 15934
HI, We have about 20 Xilinx 4000XL chips daisy chained and we would like to program them with a single EEPROM/Flash with more than 12Mbits if possible. Is there such a device out there that can be socketed easily? Thanks a lot for your info in advance. ----------------------- Louis Zhang lzhang@eecg.toronto.eduArticle: 15935
We have XC40110XV device but we want to use the pin-to-pin compatiable XC40150XV instead of that. 110 needs 3 x 1 Mb PROM but 150 needs 4 x 1 Mb PROM. But the board of XC40110XV does only have 3 PROMs. Despite that, is it possible to load XC40140XV configuration data into 3 x 1 Mb PROMs? Is it possible to restrict the size of XC40150XV data to the one for XC40110XV? Utku -- I feel better than James Brown.Article: 15936
On 21 Apr 1999 14:16:09 -0700, mcgett@efc3.xsj.xilinx.com (Ed McGettigan) wrote: >In article <371e2f10.5120875@news.dial.pipex.com>, > <ems@riverside-machines.com.NOSPAM> wrote: >>"The configuration pins on a Virtex device are on the right side of >>the chip. When configuring the device through a serial prom the user >>is required to use a VREF of 3.3V in the two banks on the right hand >>side of the chip. If the user is not configuring the device through a >>serial prom, the VREF requirement is dependent upon the configuration >>source". >> > >This was a typo in the libraries guide. Replace VREF with VCCO. > >Ed thanks ed - evanArticle: 15937
Could anyone confirm that this cable, taken from the europractice web site (for european universities) will work with the VCC virtual workbench? PC XChecker Cable UW-XCHCBL-PC 200 EURO each Also, we have several serial download cables already in our department. Will these work with the board Many thanks Daryl -- Bio-Inspired Architectures Department of Electronics University of York, UK 01904 432379 (office) http://www-users.york.ac.uk/~dwb105Article: 15938
I've tried this, but doesn't work. You have to insert OBUF and TDO by script commands after synthesis. Thanks. Bruce Nepple schrieb in Nachricht ... >Instantiate an OBUF and connect it to a TDO. Obvious huh? This worked in >Synopsys, seems like it would work for Exemplar > > //Do the TDO thing (not in Xilinx documentation) > TDO rclk(.O (regclkout)); //regclk uses the TDO pin P181 > OBUF rclko (.O (regclkout), .I (regclk));Article: 15939
Hi all, Can anyone tell me (or point me in the direction of) any rules or guidelines for posting Job adverts here? (eg. Don't, or prefix the subject with "Job:"). Thanks, Ian Jamison ----------------------------------------------------------- Integrated Silicon Systems Ltd. Tel: +44 1232 664 664 50 Malone Road Fax: +44 1232 669 664 Belfast BT9 5BS Web: www.iss-dsp.comArticle: 15940
Hi NO-SPAM damiano wrote: > Ok, Finally I'm going on with VHDL I found a good interactive tutorial > an a good VHDL book from Cypress, which comes with some useful > examples. > Now I'm looking for free or low cost software for circuit simulation, > starting from VHDL code. > Any suggestion welcome. Check out Part 3, Section 3 of the VHDL FAQ (http://www.vhdl.org/comp.lang.vhdl/). It lists some free and commercial VHDL compilers for PC's. -- EdwinArticle: 15941
Ingmar Hohmann wrote: > I've tried this, but doesn't work. > You have to insert OBUF and TDO by script commands after synthesis. > > Thanks. > > Bruce Nepple schrieb in Nachricht ... > >Instantiate an OBUF and connect it to a TDO. Obvious huh? This worked in > >Synopsys, seems like it would work for Exemplar > > > > //Do the TDO thing (not in Xilinx documentation) > > TDO rclk(.O (regclkout)); //regclk uses the TDO pin P181 > > OBUF rclko (.O (regclkout), .I (regclk)); This one works in VHDL with Synplicity: component TDO port(O: in STD_LOGIC); end component; attribute black_box: boolean; attribute black_box of TDO: component is true; attribute syn_noprune:boolean; attribute syn_noprune of TDO:component is true; attribute black_box_pad_pin: string; attribute black_box_pad_pin of TDO:component is "O"; signal SIGOUT:STD_LOGIC; jt:TDO port map(O=>SIGOUT); Catalin BaetoniuArticle: 15942
In article <37180916.AB9993CC@ids.net>, Ray Andraka <randraka@ids.net> wrote: >Virtex >suffers in partial reconfiguration somewhat because a a whole column has >to be done at a time. That has the potential to disrupt signals routed >across the column while the configuration is occuring, which means you >need either stop the clock or configure synchronously with the clock to >avoid problems in the rest of the circuit. Virtex does not require designers to reconfigure the entire column, but only a frame (multi-bits each row) of the column. In addition the re-configuration of a frame is glitchless, so if you don't change a bit it stays the same without undergoing a 1-0-1 or 0-1-0 transition. So you can leave logic and nets running around and through the column without interference. EdArticle: 15943
The only one I can think of is: don't do it. But, if you absolutely
MUST do it, please just do it once. Seeing something posted here
several times is crappy.
Cheers,
Jake
In <371F40E5.B7FE0022@iss-dsp.com> Ian Jamison <IJamison@iss-dsp.com> writes:
>Hi all,
>
>Can anyone tell me (or point me in the direction of) any rules or
>guidelines for posting Job adverts here? (eg. Don't, or prefix the
>subject with "Job:").
>
>Thanks,
>Ian Jamison
>-----------------------------------------------------------
>Integrated Silicon Systems Ltd. Tel: +44 1232 664 664
>50 Malone Road Fax: +44 1232 669 664
>Belfast BT9 5BS Web: www.iss-dsp.com
>
>
--
janovetz@uiuc.edu | Once you have flown, you will walk the earth with
University of Illinois | your eyes turned skyward, for there you have been,
| there you long to return. -- da Vinci
PP-ASEL | http://www.ews.uiuc.edu/~janovetz/index.html
Article: 15944Ian Jamison <IJamison@iss-dsp.com> wrote in message news:371F40E5.B7FE0022@iss-dsp.com... > Hi all, > > Can anyone tell me (or point me in the direction of) any rules or > guidelines for posting Job adverts here? (eg. Don't, or prefix the > subject with "Job:"). Post only once. Prefix with job: Have geographical area on subject. Have salary range on subject. Have job title or important specifics on subject. Don't fight with posters. Post only jobs relevant to the special interest of the NG. Have full details in message body. Post only real specific jobs. No 'fishing expeditions' to get resume's.Article: 15945
On Thu, 22 Apr 1999 12:34:35 +0200, "Ingmar Hohmann" <ih@seh.de>
wrote:
>I've tried this, but doesn't work.
>You have to insert OBUF and TDO by script commands after synthesis.
No you don't
module and2test (a,b);
input a, b;
reg result_int;
wire result_buf;
always@(a or b)
begin
result_int = a & b ;
end
TDO my_tdo (.O (result_buf));
OBUF my_tdo_buffer (.O (result_buf), .I (result_int));
endmodule //
save this as a file called and2test.v
In the quick setup, load the file, specify the source technology as
xilinx 4000xl (IMPORTANT) and pick a 4000xl as target technology.
Hit the run button
Run P&R from Spectrum
Works for me. Leonardo Spectrum 1998.2e Level2 or Level3, no script,
no garbage in the HDL.
Cheers
Stuart
An employee of Saros Technology:
Model Technology, Exemplar Logic, TransEDA, Renoir.
www.saros.co.uk
Article: 15946Hello, I'm the developer of Xilinx WebFITTER -- a free CPLD design tool on the web at http://www.xilinx.com/sxpresso/webfitter.htm . You can submit your design in VHDL/Verilog/EDIF and get back a jedec file and reports in a few minutes. Please give it a try -- I am interested in comments/feedback. Regards SanjeevArticle: 15947
That is good news. Previous conversations indicated otherwise (as far as guaranteeing no upset on unchanged logic). Still there is the issue of keeping the routing the same. Right now, the tools provide very very little support for locking routing between successive time slices. One of the issues I've been pushing is adding a capability to put up 'fences' to keep routing in or out of an area and the ability to do incremental routes. Ed McGettigan wrote: > In article <37180916.AB9993CC@ids.net>, Ray Andraka <randraka@ids.net> wrote: > >Virtex > >suffers in partial reconfiguration somewhat because a a whole column has > >to be done at a time. That has the potential to disrupt signals routed > >across the column while the configuration is occuring, which means you > >need either stop the clock or configure synchronously with the clock to > >avoid problems in the rest of the circuit. > > Virtex does not require designers to reconfigure the entire column, but only > a frame (multi-bits each row) of the column. In addition the re-configuration > of a frame is glitchless, so if you don't change a bit it stays the same > without undergoing a 1-0-1 or 0-1-0 transition. So you can leave logic > and nets running around and through the column without interference. > > Ed -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15948
This is a multi-part message in MIME format. --------------4CB1423AF1CA8599D648AC0E Content-Type: multipart/alternative; boundary="------------EE18DCA47324B48CB483DF8D" --------------EE18DCA47324B48CB483DF8D Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit I think the problem that Ingmar may have encountered may be due to the fact that he is declaring the TDO port as an output in his code which could cause an incorrect connection to that port (although some synthesis tools allow this, but can't speak for Exemplar). The trick (as you could call it) as illustrated by Stuart's code is to not declare the special pins as a port. Simply instantiate them as a component and forget that they are pins. I know this can make simulation a little sticky but that is one of the prices you pay for using one of the special deul-purpose pins. I consider it part of the persuation not to use these pins unless absolutly necessary. Unless precautions are taken with these pins, a designer could design a board in which the FPGA would not configure properly. Hopefully you got this working for you by now, Ingmar, but if you need another example, there is an example in both VHDL and Verilog of a Boundary Scan instantiation including the Boundary Scan pin is the Xilinx Synhtesis and Simulation Guide at: http://support.xilinx.com/appnotes/hdl_dg.pdf -- Brian Stuart Clubb wrote: > On Thu, 22 Apr 1999 12:34:35 +0200, "Ingmar Hohmann" <ih@seh.de> > wrote: > > >I've tried this, but doesn't work. > >You have to insert OBUF and TDO by script commands after synthesis. > > No you don't > > module and2test (a,b); > input a, b; > reg result_int; > wire result_buf; > always@(a or b) > begin > result_int = a & b ; > end > TDO my_tdo (.O (result_buf)); > OBUF my_tdo_buffer (.O (result_buf), .I (result_int)); > endmodule // > > save this as a file called and2test.v > > In the quick setup, load the file, specify the source technology as > xilinx 4000xl (IMPORTANT) and pick a 4000xl as target technology. > > Hit the run button > Run P&R from Spectrum > > Works for me. Leonardo Spectrum 1998.2e Level2 or Level3, no script, > no garbage in the HDL. > > Cheers > Stuart > An employee of Saros Technology: > Model Technology, Exemplar Logic, TransEDA, Renoir. > www.saros.co.uk -- ------------------------------------------------------------------- / 7\'7 Brian Philofsky (brian.philofsky@xilinx.com) \ \ ` Xilinx Applications Engineer hotline@xilinx.com / / 2100 Logic Drive 1-800-255-7778 \_\/.\ San Jose, California 95124-3450 1-408-879-5199 ------------------------------------------------------------------- --------------EE18DCA47324B48CB483DF8D Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> <p>I think the problem that Ingmar may have encountered may be due to the fact that he is declaring the TDO port as an output in his code which could cause an incorrect connection to that port (although some synthesis tools allow this, but can't speak for Exemplar). The trick (as you could call it) as illustrated by Stuart's code is to not declare the special pins as a port. Simply instantiate them as a component and forget that they are pins. I know this can make simulation a little sticky but that is one of the prices you pay for using one of the special deul-purpose pins. I consider it part of the persuation not to use these pins unless absolutly necessary. Unless precautions are taken with these pins, a designer could design a board in which the FPGA would not configure properly. <p>Hopefully you got this working for you by now, Ingmar, but if you need another example, there is an example in both VHDL and Verilog of a Boundary Scan instantiation including the Boundary Scan pin is the Xilinx Synhtesis and Simulation Guide at: <A HREF="http://support.xilinx.com/appnotes/hdl_dg.pdf">http://support.xilinx.com/appnotes/hdl_dg.pdf</A> <br> <p>-- Brian <br> <br> <p>Stuart Clubb wrote: <blockquote TYPE=CITE>On Thu, 22 Apr 1999 12:34:35 +0200, "Ingmar Hohmann" <ih@seh.de> <br>wrote: <p>>I've tried this, but doesn't work. <br>>You have to insert OBUF and TDO by script commands after synthesis. <p>No you don't <p>module and2test (a,b); <br> input a, b; <br> reg result_int; <br> wire result_buf; <br>always@(a or b) <br>begin <br> result_int = a & b ; <br>end <br>TDO my_tdo (.O (result_buf)); <br>OBUF my_tdo_buffer (.O (result_buf), .I (result_int)); <br>endmodule // <p>save this as a file called and2test.v <p>In the quick setup, load the file, specify the source technology as <br>xilinx 4000xl (IMPORTANT) and pick a 4000xl as target technology. <p>Hit the run button <br>Run P&R from Spectrum <p>Works for me. Leonardo Spectrum 1998.2e Level2 or Level3, no script, <br>no garbage in the HDL. <p>Cheers <br>Stuart <br>An employee of Saros Technology: <br>Model Technology, Exemplar Logic, TransEDA, Renoir. <br>www.saros.co.uk</blockquote> <pre>-- ------------------------------------------------------------------- / 7\'7 Brian Philofsky (brian.philofsky@xilinx.com) \ \ ` Xilinx Applications Engineer hotline@xilinx.com / / 2100 Logic Drive 1-800-255-7778 \_\/.\ San Jose, California 95124-3450 1-408-879-5199 -------------------------------------------------------------------</pre> </html> --------------EE18DCA47324B48CB483DF8D-- --------------4CB1423AF1CA8599D648AC0E Content-Type: text/x-vcard; charset=us-ascii; name="brianp.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brianp.vcf" begin:vcard n:Philofsky;Brian tel;fax:(408) 879-4442 tel;work:1-800-255-7778 x-mozilla-html:TRUE org:<br><img src="http://www.xilinx.com/images/xlogoc.gif" alt="Xilinx"><BR><BR>;Xilinx Design Center version:2.1 email;internet:brianp@xilinx.com title:Application Engineer adr;quoted-printable:;;2100 Logic Drive=0D=0ADept. 2510;San Jose;CA;95124-3450;USA x-mozilla-cpt:;-12504 fn:Brian Philofsky end:vcard --------------4CB1423AF1CA8599D648AC0E--Article: 15949
In comp.lang.vhdl Ian St John <istjohn@spamcop.net> wrote: > Ian Jamison <IJamison@iss-dsp.com> wrote in message > news:371F40E5.B7FE0022@iss-dsp.com... >> Can anyone tell me (or point me in the direction of) any rules or >> guidelines for posting Job adverts here? (eg. Don't, or prefix the >> subject with "Job:"). > Post only once. > Prefix with job: > Have geographical area on subject. > Have salary range on subject. > Have job title or important specifics on subject. > Don't fight with posters. > Post only jobs relevant to the special interest of the NG. > Have full details in message body. > Post only real specific jobs. No 'fishing expeditions' to get > resume's. Don't do it (as someone else said). But if you must rather than a long posting, just post a URL to the information not suggested by Ian St. John for the subject line. And, crossposting is preferred to multiposting, when the job may be relevant to multiple groups. That way, people who read multiple groups will see it only once. Thanks for asking, Paul -- Paul Menchini | mench@mench.com | "Non si vive se non il OrCAD | www.orcad.com | tempo che si ama." P.O. Box 71767 | 919-479-1670[v] | --Claude Adrien Helvetius Durham, NC 27722-1767 | 919-479-1671[f] |
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