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Messages from 22925

Article: 22925
Subject: Convert Xilinx Foundation ourput to C/C++ compatible file.
From: steveh@link-comm.com (Steve Holle)
Date: Fri, 02 Jun 2000 20:37:50 GMT
Links: << >>  << T >>  << A >>
I have a small utility I wrote to take the ASCII bit file output of
the Foundation tools and convert it to a C/C++ compatible file.  It
creates an unsigned long array of 32-bit long words and a variable
with the bit length and word length.  This file can be used to program
the Xilinx parts from a controller programmed in either of those
languages.  The exe is make file compatible.  I offered to trade it to
Xilinx for a XChecker cable but they wouldn't go for it.  If anyone is
interested they can contact me by email and I would be glad to email
the exe and source.
steveh@link-comm.com
Article: 22926
Subject: Re: Virtex Block Select RAM Timing Problem
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Fri, 02 Jun 2000 22:26:42 +0100
Links: << >>  << T >>  << A >>


Eirik Esp wrote:

> .  After further investigation, I think we have found a problem with
> constraints around the block RAMs.  We are using the block RAMs for an
> asynchronous FIFO interface, with Write Clk A @ 14.5 ns and Read Clk B @
> 9.5 ns.  Even though Read Clk B is constrained, when I follow the output
> data from the BR through the logic into a flip flop using the timing
> analyzer, the path comes in at 12.5 ns on a 9.5 ns constraint on Read Clk
> B.  I would like to see this report an error in the tool, but the timing
> analyzer doesn't seem to think this is a problem!  To get the timing
> analyzer to see this path and analyze it properly, I had to set a
> constraint from Write Clk A to Read Clk B of 9.5 ns, and then the timing
> analyzer was able to report the errors, and presumably try to place and
> route the device to make the necessary timing.  I think this a BUG in the
> timing analyzer for Alliance, using 2.1i SP6, and even in the new 3.1 tool,
>
> which we have also tried.  Anyone else see this problem?  We are working
> with Xilinx to look into it, but I just can't believe we are the first
> people to experience this problem.

I've come across this as well - its in the answers database #6448. The issue is
that although the A & B ports should be considered independently from the point
of view of timing they are not. If  you use period timespecs on TNM groups for
the 2 ports the timegroups generated in the PCF file from the 2 contraints each
contain BOTH the A & B ports. After wasting time trying to implement their idea
of hacking the PCF with a perl script I came up with this instead:

Add separate timespecs like this:

TIMESPEC TSBlkRAMIFast = FROM fastffs TO BlockRAMs 9.5;
TIMESPEC TSBlkRAMOFast = FROM BlockRAMs TO fastffs 9.5;

Where fastffs is a TNM timegroup consisting of  the FFs on the 9.5nsec clock. A
similar set of Tspecs is defined for the slow clock side. This works since a
FROM/TO timespec has a higher priority than a period contraint. To absolutely -
belt, braces, and RSJ - certain I actually added a ``PRIORITY'' value to the
timespecs.



Article: 22927
Subject: Re: Microprocessors in FPGA
From: "Domagoj" <domagoj@engineer.com>
Date: Sat, 3 Jun 2000 00:51:36 +0200
Links: << >>  << T >>  << A >>
Hi,
    I had a look on www.circuitcellar.com , downloaded their article indeces
and couldn't find any author named Jan Gray. There are some interesting
articles, so thanks anyway.
regards,
-------------------------------------------
-             Domagoj              -
- Domagoj@engineer.com -
-------------------------------------------

Ray Andraka <ray@andraka.com> wrote in message
news:39366E67.6C0CC2BB@andraka.com...
> You can design a RISC processor around the FPGA architecture and get
> pretty good performance.  You might look at the series by Jan Gray in
> Circuit Cellar for an example.  If you are trying to emulate a commercial
> processor, you are going to be considerably slower and more expensive
> than the purpose-made processor, except in those cases where the
> processor is in a really old (several microns) technology.
>
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com



Article: 22928
Subject: Re: Microprocessors in FPGA
From: Dave Vanden Bout <devb@xess.com>
Date: Fri, 02 Jun 2000 20:05:54 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------54BD1DBA1313D61DC06478E5
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Go to http://www.fpgacpu.org and you will find the XSOC micro from the Circuit Cellar articles.  There are pointers PDF files for the first and second Circuit Cellar articles.




Domagoj wrote:

> Hi,
>     I had a look on www.circuitcellar.com , downloaded their article indeces
> and couldn't find any author named Jan Gray. There are some interesting
> articles, so thanks anyway.
> regards,
> -------------------------------------------
> -             Domagoj              -
> - Domagoj@engineer.com -
> -------------------------------------------
>
> Ray Andraka <ray@andraka.com> wrote in message
> news:39366E67.6C0CC2BB@andraka.com...
> > You can design a RISC processor around the FPGA architecture and get
> > pretty good performance.  You might look at the series by Jan Gray in
> > Circuit Cellar for an example.  If you are trying to emulate a commercial
> > processor, you are going to be considerably slower and more expensive
> > than the purpose-made processor, except in those cases where the
> > processor is in a really old (several microns) technology.
> >
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com  or http://www.fpga-guru.com

--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||


--------------54BD1DBA1313D61DC06478E5
Content-Type: text/x-vcard; charset=us-ascii;
 name="devb.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Dave Vanden Bout
Content-Disposition: attachment;
 filename="devb.vcf"

begin:vcard 
n:Vanden Bout;Dave
tel;fax:(919) 387-1302
tel;work:(919) 387-0076
x-mozilla-html:FALSE
url:http://www.xess.com
org:XESS Corp.
adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA
version:2.1
email;internet:devb@xess.com
title:FPGA Product Manager
x-mozilla-cpt:;-16464
fn:Dave Vanden Bout
end:vcard

--------------54BD1DBA1313D61DC06478E5--

Article: 22929
Subject: Re: Microprocessors in FPGA
From: bobperl@best_no_spam_thanks.com (Bob Perlman)
Date: Sat, 03 Jun 2000 00:41:34 GMT
Links: << >>  << T >>  << A >>
On Sat, 3 Jun 2000 00:51:36 +0200, "Domagoj" <domagoj@engineer.com>
wrote:

>Hi,
>    I had a look on www.circuitcellar.com , downloaded their article indeces
>and couldn't find any author named Jan Gray. There are some interesting
>articles, so thanks anyway.
>regards,

Go to:

     http://www.fpgacpu.org/

Bob Perlman


>-------------------------------------------
>-             Domagoj              -
>- Domagoj@engineer.com -
>-------------------------------------------
>
>Ray Andraka <ray@andraka.com> wrote in message
>news:39366E67.6C0CC2BB@andraka.com...
>> You can design a RISC processor around the FPGA architecture and get
>> pretty good performance.  You might look at the series by Jan Gray in
>> Circuit Cellar for an example.  If you are trying to emulate a commercial
>> processor, you are going to be considerably slower and more expensive
>> than the purpose-made processor, except in those cases where the
>> processor is in a really old (several microns) technology.
>>
>> -Ray Andraka, P.E.
>> President, the Andraka Consulting Group, Inc.
>> 401/884-7930     Fax 401/884-7950
>> email ray@andraka.com
>> http://www.andraka.com  or http://www.fpga-guru.com
>
>

-----------------------------------------------------
Bob Perlman
Cambrian Design Works
Digital Design, Signal Integrity
http://www.best.com/~bobperl/cdw.htm
Send e-mail replies to best<dot>com, username bobperl
-----------------------------------------------------
Article: 22930
Subject: Re: Microprocessors in FPGA
From: "Domagoj" <domagoj@engineer.com>
Date: Sat, 3 Jun 2000 03:58:59 +0200
Links: << >>  << T >>  << A >>
    I found it ! Thanks.

-------------------------------------------
-             Domagoj              -
- Domagoj@engineer.com -
-------------------------------------------
Bob Perlman <bobperl@best_no_spam_thanks.com> wrote in message
news:39385428.119120095@nntp.best.com...
> On Sat, 3 Jun 2000 00:51:36 +0200, "Domagoj" <domagoj@engineer.com>
> wrote:
>
> >Hi,
> >    I had a look on www.circuitcellar.com , downloaded their article
indeces
> >and couldn't find any author named Jan Gray. There are some interesting
> >articles, so thanks anyway.
> >regards,
>
> Go to:
>
>      http://www.fpgacpu.org/
>
> Bob Perlman
>
>
> >-------------------------------------------
> >-             Domagoj              -
> >- Domagoj@engineer.com -
> >-------------------------------------------
> >
> >Ray Andraka <ray@andraka.com> wrote in message
> >news:39366E67.6C0CC2BB@andraka.com...
> >> You can design a RISC processor around the FPGA architecture and get
> >> pretty good performance.  You might look at the series by Jan Gray in
> >> Circuit Cellar for an example.  If you are trying to emulate a
commercial
> >> processor, you are going to be considerably slower and more expensive
> >> than the purpose-made processor, except in those cases where the
> >> processor is in a really old (several microns) technology.
> >>
> >> -Ray Andraka, P.E.
> >> President, the Andraka Consulting Group, Inc.
> >> 401/884-7930     Fax 401/884-7950
> >> email ray@andraka.com
> >> http://www.andraka.com  or http://www.fpga-guru.com
> >
> >
>
> -----------------------------------------------------
> Bob Perlman
> Cambrian Design Works
> Digital Design, Signal Integrity
> http://www.best.com/~bobperl/cdw.htm
> Send e-mail replies to best<dot>com, username bobperl
> -----------------------------------------------------


Article: 22931
Subject: Re: to make few modifications on a design
From: "llandre" <andmars@tin.it>
Date: Sat, 3 Jun 2000 20:11:47 +0200
Links: << >>  << T >>  << A >>
I never used it, but I thing you have to do the so-called "incremental
design"
(please somebody correct me if  I'm wrong). The manual of Foundation
explains how to make it (I read about it in a .pdf file but I don't remeber
its
name now, sorry).

--
l'landre
 e-mail : andmars@tin.it
 web    : http://www.dei.unipd.it/~patch




<jthioude@my-deja.com> ha scritto nel messaggio
news:8h8jei$pfa$1@nnrp1.deja.com...
> First of all, exuse me for my poor english.I've got a disign on a
XC4044XLA
> , implemented with Foundation 1.5i. This design is "critiqal in delay".I'd
> like to make few modifications on this design if possible, without
modifying
> the first routing. What is the best method??
>
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.


Article: 22932
Subject: Free sources on the net
From: "llandre" <andmars@tin.it>
Date: Sat, 3 Jun 2000 20:13:51 +0200
Links: << >>  << T >>  << A >>
I recently visited a very interesting site (www.opencores.com) where you can
find open sources of cores for FPGA. Anybody knows about other similar
sites?

--
l'landre
 e-mail : andmars@tin.it
 web    : http://www.dei.unipd.it/~patch



Article: 22933
Subject: Re: Where's OptiMagic?
From: malex@intranet.ca (Alex P.Martin)
Date: Sun, 04 Jun 2000 01:50:57 GMT
Links: << >>  << T >>  << A >>
bobperl@best_no_spam_thanks.com (Bob Perlman) wrote:
Where are you; Opti.....?

Article: 22934
Subject: VirtexE prototype board
From: Allan James Cantle <a.cantle@nallatech.com>
Date: Sun, 4 Jun 2000 15:36:27 +0100
Links: << >>  << T >>  << A >>
Hi David

Nallatech provide a range of PCI prototyping platforms along with DIME
module sites that allow for additional FPGAs and different types of
interfaces to be attached to a users design. The Ballynuey2 card is
probably the most appropriate as it also includes a PCI interface and
also configures the FPGAs through the PCI bus and therefore doesn't need
any download cables(it's also fast, an XCV1000 only takes
550milliseconds to configure).

Take a look at Nallatech's website www.nallatech.com 

Best Regards

Allan Cantle
Nallatech Ltd


-----Original Message-----
From: dave_admin@my-deja.com [mailto:dave_admin@my-deja.com]
Posted At: 29 May 2000 01:37
Posted To: fpga
Conversation: VirtexE prototype board
Subject: VirtexE prototype board


Hi,

I am looking for a  VirtexE prototype board with at least 1 million
gates capability (1 VirtexE1000 or bigger) and PCI interface.

regards,
Dave.


Sent via Deja.com http://www.deja.com/
Before you buy.

Article: 22935
Subject: Re: Convert Xilinx Foundation ourput to C/C++ compatible file.
From: Christian Mautner <at@utanet.cmautner>
Date: 04 Jun 2000 21:52:56 +0200
Links: << >>  << T >>  << A >>
steveh@link-comm.com (Steve Holle) writes:

> I have a small utility I wrote to take the ASCII bit file output of
> the Foundation tools and convert it to a C/C++ compatible file.  It
> creates an unsigned long array of 32-bit long words and a variable
> with the bit length and word length.  This file can be used to program
> the Xilinx parts from a controller programmed in either of those
> languages.  The exe is make file compatible.  I offered to trade it to
> Xilinx for a XChecker cable but they wouldn't go for it.  If anyone is
> interested they can contact me by email and I would be glad to email
> the exe and source.
> steveh@link-comm.com

Sorry to say this, but you can't blame Xilinx for not accepting your
(presumably DOS) executable which fulfills a task that can be done in
one line of perl:

undef $/; print "const unsigned char fpga [] = {\n" . join(",\n",unpack("C*",<>) ) . "};\n";

Find a full featured version below.

sometimes a missionary of _sharing_ ideas and Open Source,
regards,
chm.

--------------------------------------------------------------------------------
#!/usr/bin/perl

# The data wil be padded with 0xff to be a multiple of $alignment
# This value also defined the number of columns in the *.c file
$alignment=8;

# The name of the *.[ch] files and the name of the defined variable
$name="FPGABitstream";

# The warning string
$warning="/* This file was generated automatically by $0 */";

#################### end of configurable stuff

$file = shift();

die "usage: $0 <filename>\n" unless $file;

open(B, $file) or die "can't open $file";

$m=$/;
undef $/;
$dat = <B>;
$/=$m;

close B;

$reallen=length($dat);

$len= ( $reallen + $alignment ) & ~($alignment-1);

$dat .= "\377" x ($len-$reallen);

open(H, ">$name.h") or die "can't open $name.h";
print H "$warning

const unsigned int ${name}Size = $reallen;
extern const unsigned char $name [ $len ] ;

";
close H;

open(C, ">$name.c") or die "can't open $name.h";
print C "$warning
/*
 * Generation date: ". scalar(localtime) ."
 * Bitstream source: $file
 * Bitstream original size: $reallen
 * Bitstream padded size: $len
 * Alignment: $alignment
 */

#include \"$name.h\"

const unsigned char $name [] = {
";

for ( $i = 0; $i < $len ; $i += $alignment ) 
{
    print C join(", ", unpack("C$alignment", substr($dat, $i, $alignment)));
    print C ",\n";
}

print C "};

";

close C;
--------------------------------------------------------------------------------


-- 
cmautner@  -  Christian Mautner
utanet.at  -  Vienna/Austria/Europe

Article: 22936
Subject: Altera FPGA/CPLD in-system-programmer
From: lone_traveler@my-deja.com
Date: Sun, 04 Jun 2000 21:54:45 GMT
Links: << >>  << T >>  << A >>
Altera FPGA/CPLD in-system-programmer, a 100%
compatible replacement for ByteBlaster MV, at $75
(versus Altera $150) is availeble at:
http://www.amboy.com/


Sent via Deja.com http://www.deja.com/
Before you buy.

Article: 22937
Subject: Altera and Atmel FPGA/CPLD in-system-programmer from SmartChip
From: "Willy_Tsai" <Willy_tsai@smartchip.com.tw>
Date: Mon, 5 Jun 2000 12:19:16 +0800
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

------=_NextPart_000_0022_01BFCEE8.44702D00
Content-Type: text/plain;
	charset="big5"
Content-Transfer-Encoding: quoted-printable

Hello !

Altera and  Atmel FPGA/CPLD in-system-programmer,=20
a 100% compatible replacement for ByteBlaster,
US$10 for PCB board (DIY parts by you.)

Altera and Atmel FPGA/CPLD in-system-programmer and Application Board
only for 84pins PLCC and debug Pin out.
US$10 for PCB board (DIY parts by you.)


Thanks in advance.

Any leads greatly appreciated.

*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/-=
\*/*/-\*/*/-\*/*/-\*/-\*/*/-\*/*/-\*/*/-\*/
Willy_Tsai  ADD:6F,NO.103,SEC.2 NAN CHANG ROAD,TAIPEI,TAIWAN, R.O.C
Email: Willy_Tsai@Smartchip.com.tw                 =20
*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/-=
\*/*/-\*/*/-\*/*/-\*/-\*/*/-\*/*/-\*/*/-\*/



------=_NextPart_000_0022_01BFCEE8.44702D00
Content-Type: text/html;
	charset="big5"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Dbig5" http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2722.2800" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT size=3D2>Hello !</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2><FONT size=3D2>Altera and&nbsp; Atmel FPGA/CPLD=20
in-system-programmer, </FONT></FONT></DIV>
<DIV><FONT size=3D2><FONT size=3D2>a 100% compatible replacement for=20
ByteBlaster,</FONT></FONT></DIV>
<DIV><FONT size=3D2><FONT size=3D2>US$10 for PCB board (DIY parts by=20
you.)</FONT></FONT></DIV>
<DIV><FONT size=3D2><FONT size=3D2></FONT></FONT>&nbsp;</DIV>
<DIV><FONT size=3D2><FONT size=3D2>
<DIV><FONT size=3D2><FONT size=3D2>Altera and&nbsp;Atmel FPGA/CPLD=20
in-system-programmer and Application Board</FONT></FONT></DIV>
<DIV>only for 84pins PLCC and debug Pin out.</DIV>
<DIV><FONT size=3D2><FONT size=3D2>US$10 for PCB board (DIY parts by=20
you.)</FONT></FONT></DIV></FONT></FONT></DIV>
<DIV><FONT size=3D2><FONT size=3D2><BR>&nbsp;</DIV></FONT>
<DIV>Thanks in advance.</DIV>
<DIV>&nbsp;</DIV>
<DIV>Any leads greatly appreciated.</DIV>
<DIV>&nbsp;</DIV>
<DIV>*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/=
-\*/-\*/*/-\*/*/-\*/*/-\*/-\*/*/-\*/*/-\*/*/-\*/<BR>Willy_Tsai&nbsp;=20
ADD:6F,NO.103,SEC.2 NAN CHANG ROAD,TAIPEI,TAIWAN, =
R.O.C<BR>Email:&nbsp;<A=20
href=3D"mailto:Willy_Tsai@Smartchip.com.tw">Willy_Tsai@Smartchip.com.tw</=
A>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
<BR>*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-=
\*/-\*/*/-\*/*/-\*/*/-\*/-\*/*/-\*/*/-\*/*/-\*/</DIV>
<DIV>&nbsp;</DIV>
<DIV></FONT>&nbsp;</DIV></BODY></HTML>

------=_NextPart_000_0022_01BFCEE8.44702D00--

Article: 22938
Subject: Synopsis DesignWare PCI-Core (DWPCI) implemented on FPGA?
From: Patrick Schulz <schulz@rumms.uni-mannheim.de>
Date: Mon, 05 Jun 2000 10:20:36 +0200
Links: << >>  << T >>  << A >>
Hello there,

does any of you implemented the DWPCI on an FPGA maybe with FPGACompiler II?
I'm interested in the area and P&R complexity.
I know about the PCI LogiCORE from Xilinx, so please don't point on that ;-)

The reason for my interest is the complete implementation of a PCI-hosted ASIC prototype on an FPGA.


Thanks for your comments.

Patrick

-- 
Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org)
University of Mannheim - Dep. of Computer Architecture
68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de
Phone: +49-621-181-2720     Fax: +49-621-181-2713
Article: 22939
Subject: PLA to ABEL converter?
From: leinone3@lehtori.cc.tut.fi (Leinonen Mika)
Date: 5 Jun 2000 10:22:05 GMT
Links: << >>  << T >>  << A >>
I need a program that converts PLA description to ABEL HDL.
Where can I find such (or maybe I'll have to program it myself)?
The PLA description looks like this:
AAAA AAAA  OOOO
7654 3210  4321
---------------
0000 0000  1011
.... ....  ....
0111 0111  1011
0111 1000  1010
.... ....  ....
0111 1111  1010

1000 0000  0110
1000 0001  0111
1000 0010  1111
1000 0011  1111
1000 0100  0010
1000 0101  0011
1000 0110  1010
1000 0111  1011
1000 1000  0110
... Continues
--
mika.leinonen"at"cc.tut.fi
http://www.students.tut.fi/%7Eleinone3/
Article: 22940
Subject: Virtex: How to Map 2 Functions to one Slice
From: Ulrich Seidl <Seidl@regent.e-technik.tu-muenchen.de>
Date: Mon, 05 Jun 2000 13:42:00 +0200
Links: << >>  << T >>  << A >>
Assume the following description of a circuit in XNF:

SYM, TSIG_21_CLB,  CLB
      CFG, Base FG
      CFG, CONFIG X:F Y:G CLK: F:A:B:C:D G:A:B:C:D
      CFG , Equate F = ((D)+(A*B*C))
      CFG , Equate G = ((C*~D)+(A*B*~D)+(~B*~C*D))
               PIN,A, I,S763,
               PIN,B, I,S762,
               PIN,C, I,S761,
               PIN,D, I,S760,
               PIN, X,O, TSIG_21,
               PIN, Y,O, TSIG_22,
               END

When mapping that description to VIRTEX the Xilinx M1-Tools usually
remap the F-and the G-Funktion to different Slices. Is there a way to
ensure, that the F and the G functions get mapped to Logic Cells within
the same Slice? Is there a way to prohibit the remapping performed by
the M1-Tools?

Ulrich

--

Ulrich.Seidl@ei.tum.de

Article: 22941
Subject: Re: Help with Coregen
From: Ray Andraka <ray@andraka.com>
Date: Mon, 05 Jun 2000 13:36:35 GMT
Links: << >>  << T >>  << A >>
You can create RPMs in VHDL by structurally instantiating the xilinx primitives
and attaching RLOC attributes to the component labels.  It works fine in
Synplicity and Exemplar.  I'm not sure if it is 100% in FPGA express at this
point or not.  The combinatorial logic is a littel trickier than the flip-flops
because you have to put the RLOC on  the LUT.

jgarrigo wrote:

> Hi friends,
>
> I have another question regarding blackbox instantiation: can you obtain
> something similar to Xilinx RPM (Relational Placed Macros) with this
> method?. Can it help selecting  a "preserve hierarchy" or similar command?.
>
> Thanks in advance for your time.
>
> Ray Andraka <ray@andraka.com> wrote in 3932EFB5.439D15EA@andraka.com...
> > Unless you intend to package and sell the CORE, there is really no need to
> > put it under coregen.  Coregen is not much more than a pretty wrapper for
> > edif netlist files.  Instead, just instantiate your code as a component in
> a
> > hierarchical VHDL design.  If you are trying to do placement as well, I've
> > found the best way to do it hierarchically is to put placement attributes
> > right into the VHDL, which means you build the components from the
> > structural level (I think this is probably why you want to create a
> > component under the COREGEN).  Alternatively, you can instantiate your
> core
> > as a blackbox in VHDL under which you have an edif netlist (that is all
> > coregen does with it).  Look under the design guides for mixed
> schematic/HDL
> > design methodology for details on instantiating black boxes in your
> design.
> >
> > Vipan Kakkar wrote:
> >
> > > Dear friends:
> > >
> > > I have a vhdl description for an FIR filter make one of the tap as  a
> > > core to use it to implement the FIR filter in FPGA. I was trying to
> > > build one tap as a core using the Xilinx COREGEN, but don't know how to
> > > do it. Coregen library has FIR filter, but I want to build a core from
> > > my vhdl description of the tap, which is shown below:
> > >
> > > Could anyone help me that ... if it is possible to build a core from the
> > > vhdl description I have ... if yes then what commands (in the COREGEN)
> > > should be given and what files (e.g. .xco etc.).
> > >
> > > entity FIRTAP is
> > >   port(
> > >     CLK_S   : in  std_logic_vector( 8 downto 0);
> > >     RSTn_S  : in  std_logic_vector( 8 downto 0);
> > >     LDCOEF  : in  std_logic;
> > >     COEFi   : in  std_logic_vector(15 downto 0);
> > >     COEFo   : out std_logic_vector(15 downto 0);
> > >     I       : in  std_logic_vector(15 downto 0);
> > >     O       : out std_logic_vector(15 downto 0);
> > >     PI      : in  std_logic_vector(63 downto 0);
> > >     PO      : out std_logic_vector(63 downto 0));
> > > end FIRTAP;
> > >
> > > Regards,
> > > Vipan
> >
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com  or http://www.fpga-guru.com
> >
> >
> --
> -----------------------------------------------------------------------
> Javier Garrigos Guerrero
> Departamento de Electronica, Tecnologia de Computadoras y Proyectos
> E.T.S. de Ingenieros Industriales - Univ. Politecnica de Cartagena
> Paseo Alfonso XIII, 48.   30203  CARTAGENA (MURCIA)   -SPAIN-
> Phone:+34 968 325567 Fax:+34 968 325433 E-mail: Javier.Garrigos@upct.es
> -----------------------------------------------------------------------

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 22942
Subject: Call for Papers: FPGA'2001
From: tessier@spock.ecs.umass.edu (Russell Tessier)
Date: 5 Jun 2000 13:41:49 GMT
Links: << >>  << T >>  << A >>
                   FPGA 2001: Call for Papers
Ninth ACM* International Symposium on Field-Programmable Gate Arrays

                     Monterey, California
                     February 11-13 2001

Submissions due: September 29, 2000
web site: http://www.ecs.umass.edu/ece/fpga2001


The annual ACM/SIGDA International Symposium on Field-Programmable 
Gate Arrays is the premier conference for presentation of advances 
in all areas related to FPGA technology. For FPGA 2001, we are 
soliciting submissions describing novel research and developments 
in the following (and related) areas of interest:

* FPGA Architecture: Logic block & routing architectures, I/O 
  structures and circuits, new commercial architectures, 
  Field-Programmable Interconnect Chips and Devices (FPIC/FPID), 
  Field-Programmable Analog Arrays (FPAA).
* CAD for FPGAs: Placement, routing, logic optimization, 
  technology mapping, system-level partitioning, logic generators, 
  testing and verification, CAD for FPGA-based accelerators.
* Applications: Innovative use of FPGAs, exploitation of FPGA 
  features, novel circuits, high-performance and 
  low-power/mission-critical applications, DSP techniques, 
  uses of reconfiguration, FPGA-based cores.
* FPGA-based computing engines: Compiled accelerators, reconfigurable 
  computing, adaptive computing devices, systems and software.
* Rapid-prototyping: Fast prototyping for system-level design, 
  Multi-Chip Modules (MCMs), logic emulation.

Authors are invited to submit PDF of their paper (12 pages maximum) by 
September 29, 2000 via E-mail to fpga2001@cse.ucsc.edu.  Notification of 
acceptance will be sent by November 22, 2000.  The authors of the accepted 
papers will be required to submit the final camera-ready copy by 
December 6, 2000.  A proceedings of the accepted papers will be published 
by ACM, and included in the Annual ACM/SIGDA CD-ROM Compendium publication.*

Address questions to:

Martine Schlag, Program Chair, FPGA 2001
Dept. of Computer Engineering,
University of California, Santa Cruz
Santa Cruz, CA  95064
phone: (831) 459-3243
fax: (831) 459-4829
Email: martine@cse.ucsc.edu


General Chair: Scott Hauck, U. of Washington
Program Chair: Martine Schlag, UCSC
Publicity Chair: Russ Tessier, U. Mass.-Amherst
Finance Chair: Steve Trimberger, Xilinx

Program Committee

Ray Andraka, Andraka Consulting         Arun Kundu, Actel 
Mike Bershteyn, Quickturn               Miriam Leeser, Northeastern U.
Richard Cliff, Altera                   Wayne Luk, Imperial College 
Jason Cong, UCLA                        Margaret Marek-Sadowska, UCSB 
Andre DeHon, Caltech                    Jonathan Rose, U. Toronto 
Eugene Ding, Lucent                     Martine Schlag, UCSC 
Carl Ebeling, U. Washington             Herman Schmit, CMU 
Scott Hauck, U. Washington              Charles Stroud, UNC-Charlotte 
TingTing Hwang, Natl. Tsing Hua U.      Russ Tessier, U. Mass.-Amherst 
Sinan Kaptanoglu, Adaptive Silicon      Steve Trimberger, Xilinx 
Tom Kean, Algotronix                    Steve Wilton, U. British Columbia

Sponsored by ACM SIGDA, with support from industry.*

Please visit the web site <http://www.ecs.umass.edu/ece/fpga2001> for 
more information.

*Pending approval
Article: 22943
Subject: Re: Help for Spartan XCS10
From: "Hans Kester" <hans@ellips.nl>
Date: Mon, 5 Jun 2000 07:07:12 -0700
Links: << >>  << T >>  << A >>
Hi Ikostov,

You forgot the clock?

Hans

Article: 22944
Subject: Re: Convert Xilinx Foundation ourput to C/C++ compatible file.
From: steveh@link-comm.com (Steve Holle)
Date: Mon, 05 Jun 2000 14:11:10 GMT
Links: << >>  << T >>  << A >>
I like your Perl script.  Sorry I couldn't find it earlier.  I have
two questions.
1) Can it be compiled so that I don't need to run an interpreter every
time.
2) Is it relatively easy to add to a make file so that the conversion
is done automatically when built?

It would be nice if Xilinx would post this kind of thing on their
site.  The only utility I could find was an old DOS version that used
some kind of memory extender that was incompatible with Win95 and
Win95/DOS.

On 04 Jun 2000 21:52:56 +0200, Christian Mautner <at@utanet.cmautner>
wrote:

>Sorry to say this, but you can't blame Xilinx for not accepting your
>(presumably DOS) executable which fulfills a task that can be done in
>one line of perl:

Article: 22945
Subject: Re: CPLD: gang programming
From: "Hans Kester" <hans@ellips.nl>
Date: Mon, 5 Jun 2000 07:11:50 -0700
Links: << >>  << T >>  << A >>
Hi Augusto,

Buy a gang programmer?! Several vendors exist, look on the web.

Hans
Article: 22946
Subject: Re: PLA to ABEL converter?
From: "Austin Franklin" <austin@dark00room.com>
Date: 5 Jun 2000 14:33:37 GMT
Links: << >>  << T >>  << A >>
Use PLA2EQN....and then you would have to do your own conversion from EQN
to Abel...

Leinonen Mika <leinone3@lehtori.cc.tut.fi> wrote in article
<8hfv0d$kr0$1@baker.cc.tut.fi>...
> I need a program that converts PLA description to ABEL HDL.
> Where can I find such (or maybe I'll have to program it myself)?
> The PLA description looks like this:
> AAAA AAAA  OOOO
> 7654 3210  4321
> ---------------
> 0000 0000  1011
> .... ....  ....
> 0111 0111  1011
> 0111 1000  1010
> .... ....  ....
> 0111 1111  1010
> 
> 1000 0000  0110
> 1000 0001  0111
> 1000 0010  1111
> 1000 0011  1111
> 1000 0100  0010
> 1000 0101  0011
> 1000 0110  1010
> 1000 0111  1011
> 1000 1000  0110
> ... Continues
> --
> mika.leinonen"at"cc.tut.fi
> http://www.students.tut.fi/%7Eleinone3/
> 
Article: 22947
Subject: Virtex-E and SCSI
From: "Dan Kuechle" <dan_kuechle@i-tech.com>
Date: Mon, 05 Jun 2000 15:27:17 GMT
Links: << >>  << T >>  << A >>
Does anyone know if the new Virtex-E LVDS differential I/O will work 
with a SCSI LVD bus?  I'm interested in monitoring the SCSI bus, so I 
would only be inputing SCSI signals.  I'm interested in Ultra160 and 
Uttra320 speeds.  

Thanks

   Dan
Article: 22948
Subject: SPICE help
From: yose@wam.umd.edu (Joe Wetstein)
Date: 5 Jun 2000 13:24:35 -0400
Links: << >>  << T >>  << A >>

Hello. I am trying to do some analysis on parts of a custom board that we
are designing. Specifically, I am trying to analyze a Virtex FPGA
connected to a few banks of SDRAM, and want to model the current draw from
the memories during an autorefresh cycle, as well as the current draw (to
make sure that the fpga can provide the drive) for both registered
(buffered) and unregistered memory modules. I have the spice models for
the memory, and the IBIS models for the Xilinx part.

Problem is that I haven't used SPICE in about 10 years.

Has anyone done anything like this before?

Does anyone have any (non flame) recommendations for me?

Does anyone have any book recommendations to get up to speed on SPICE VERY
VERY quickly?

IS there a better group to post to?

Any advice or solutions would be appreciated.

Thanks,
Joe

yose@wam.umd.edu

Article: 22949
Subject: 3.3V I/O TO 5V LOGIC?
From: myself@magma.ca (myself)
Date: Mon, 05 Jun 2000 19:36:45 GMT
Links: << >>  << T >>  << A >>
Hi I will need to interface the spartan-II 3.3V I/O to 5V standard
logic levels. eg address lines out of the FPGA to a older 5v dram.

What ic's ore out there that could perforn this function?

I looked at the old 4050 that converts cmos to ttl but it was ment to
step higher voltage cmos down to ttl 5v levels.

Any suggestions or part #'s appreciated

Martin


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