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Messages from 24700

Article: 24700
Subject: Re: 8251 USART
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 17 Aug 2000 00:03:07 -0400
Links: << >>  << T >>  << A >>
So I should assume that this board is connected to a PC so that the PC
is the microcontroller for the USART experiment. 

What you are attempting to do fits into the catagory of reconfigurable
hardware. As you have discovered, reconfigurable hardware has high NRE
for the individual designs. Also, since you have to size the FPGA to the
largest project you plan to ever do, it will be overpriced for simple
projects. 

Is there some reason that you can't design your own simple USRT? I don't
think you need to be compatible with any standard device to connect to a
manchester decoder. Something as simple as an SPI port with a word sync
detector should suffice. 

In any event, good luck with you search. As I said none of the devices
you have considered work in a synchronous mode, IIRC. 



Eduardo Augusto Bezerra wrote:
> 
> Sorry, I think my explanation wasn't very clear. The idea is to have
> a specialized hardware for each course. For example:
> 
> COURSE 1: Data Communications
> --------
>          Hardware necessary: USART and manchester encoder/decoder
> 
> COURSE 2: Microprocessors
> --------
>          Hardware necessary: 8051 microcontroller
> 
> COURSE 3: Computer architecture
> --------
>          Hardware necessary: RISC CPU
> 
> COURSE 4: ...
> --------
> 
> I'll use the same board, with the same chips (a big FPGA), in different
> courses. Students from COURSE 1, for instance, do not need to use an
> 8051, and so they will download to the board the bitstream for COURSE 1,
> which has only the USART and the manchester encoder/decoder. There are
> some extra details related to the prototyping area available on the
> board, but I think they are not relevant in this discussion.
> 
> Eduardo.
> 
> rickman wrote:
> >
> > You can use a chip for the USART which will work with both CPU types.
> >
> > Eduardo Augusto Bezerra wrote:
> > >
> > > I'm developing a kit to be used in the lab sections of a data
> > > communications course. My goal is to have a generic board
> > > which can be used in different courses. For instance, in a
> > > microprocessors course the students will be able to use the
> > > same board to learn how to program a RISC CPU or an 8051
> > > microcontroller. That's the reason why I want to use cores
> > > instead of the real chips.
> > >
> > > Eduardo.
> > >
> > > rickman wrote:
> > > >
> > > > Eduardo Augusto Bezerra wrote:
> > > > >
> > > > > Basically, I'm looking for a USART, and the free core I found is a
> > > > > UART. I agree that the 16550 is better, but where can I find it? As I
> > > > > said before, it's an academic project and our budget is very low.
> > > > >
> > > > > Thanks
> > > > >
> > > > > Eduardo.
> > > >
> > > > The opencores UART is loosly based on the 16550 I believe. I have
> > > > emailed with the author of that core and we may work together to convert
> > > > it to a 16550. But it is also not a USART.
> > > >
> > > > If you need a USART device, the 85C30 is a very common device with a
> > > > large base of software, but I know of no core for it. It is also a much
> > > > more complex device than the 16550 and would take a lot more work to
> > > > design.
> > > >
> > > > Why do you need a core and not a chip? The 85C30 is very inexpensive
> > > > ($5) although not terribly small (44 pin PLCC).

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 24701
Subject: Re: When will SpartanII be in ditribution
From: Peter Alfke <palfke@earthlink.net>
Date: Thu, 17 Aug 2000 04:21:45 GMT
Links: << >>  << T >>  << A >>
As I suppose you know, the functionality of  the Spartan-II family has been
available for over a year in the 2.5-V original Virtex family.
Package options and speeds files are different, powerdown was added, and the
family was extended downwards. And, perhaps most importantly, the price for
this redesigned family is reduced rather drastically. I will investigate
whether the delay ( I know there was a delay) is as bad as you see it.

Anyhow, if you need to experiment, or even build prototypes, you can use
Virtex for that. You may have to change the package, but that should be all.
Remember also, in Xilinx you can use a bigger part to do the job of a smaller
part, without a speed penalty.

Peter Alfke, Xilinx Applications



Article: 24702
Subject: multiple drivers & foundation 2.1i
From: Richard Meester <rme@quest-innovations.com>
Date: Thu, 17 Aug 2000 07:06:58 +0200
Links: << >>  << T >>  << A >>
Hello all,

I have some problems with multiple drivers. I have a vhdl macro which
indeed has a "bus" on one side, with 10 registers writing that bus. It
can NOT happen that all registers write on the bus at the same time(i
know this) but that can not be concluded from the logic automatically.
Now when i compile this foundation keeps complainging about multiple
drivers.

Does anyone know what specials to do to programm it so that it skips the
test or something? I use the STD_LOGIC_VECTOR as a signal type.

--
Quest Innovations
tel: +31 (0) 227 604046
http://www.quest-innovations.com


Article: 24703
Subject: Re: Permanently programming FPGAs
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Thu, 17 Aug 2000 05:36:24 +0000
Links: << >>  << T >>  << A >>
> I've finished programming my FPGA and the system is ready to be used. However, I must reprogram the FPGA after each power-up. I would like to implement a quick and simple solution to "save" the information...such as using a PROM. The FPGA I'm programming is the XC4010E-4PG191I chip using the XCHECKER cable via the serial port. Is there anyway to connect the PROM here instead? (or something else simple?)

What I would like to see is a low cost development board
using Nonvol SRAM. The chips that look like core memory - on power
down they save to EEPROM and power up they restore to ram.
While the chips are slow 150ns and low density 64k bit they
would have the advantage for both programing FPGA's and use
as memory in CPU  designs. You load both sets of chips from
the host computer and then take your board off to use else where.
Ben. 
PS. 110 volts AC will also Permanently program FPGAs,or any other chip
just be careful not to let out the Magic Smoke :).

-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
"Octal Computers:Where a step backward is two steps forward!"
 http://www.jetnet.ab.ca/users/bfranchuk/index.html
Article: 24704
Subject: Distributor attitude !!
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Thu, 17 Aug 2000 06:19:52 GMT
Links: << >>  << T >>  << A >>
Hello FPGA designers,

Several years ago I attended a Xilinx promotional seminar hosted by the
local rep.

One of the speakers was a regional sales manager. He promissed all
developers the 'one hundred piece price', on any 'single piece' purchase,
for all new prototype designs. This policy was said to be backed by the
distees. When I heard him present this offer, it sounded like a self
initiated policy that likely, would not receive suffcient administering to
be consumated. (based on my stereo type of the sales person 'personality
type' and the character of this presenter) I could care less about the offer
( I'll still take it) but I did learn something.

Well, I brought this up with Insight several months later. They said, ' We
wouldn't do that. There is nothing in it for us....'  (I countered, that
fostering a lasting profitable relationship may justify foregoing initial
profits but they just didn't buy it.)  I was reminded of this conversation
recently when an Insight Xilinx FAE said to me, 'If you don't buy from us,
then why should I help you ?'

It looks like Insight has a calculated approach to their business. They have
discarded diplomatic nicities in favor of the cut to the chase direct
approach.

I understand them clearly but still feel some 'culture surprise' (one notch
less than 'shock')  This blunt talk does have an effect on my purchasing
behaviour. I capitulate, against my nature.  I want to keep them on my side.
I have been helped in a pinch by their FAE in the past. His office is just
around the corner from mine. I just shake my head and say to myself, '
Wow..., now they're direct ! '

I would like to know the nature of the relationship that others have
experienced with the licensed FPGA distees.

Sincerely
Daniel DeConinck
High Res Technologies, Inc.





Article: 24705
Subject: Re: what does 0.35 micron mean
From: "disk" <personne@microsoft.com>
Date: Thu, 17 Aug 2000 09:12:44 +0200
Links: << >>  << T >>  << A >>
> Sorry, me reply should not offend you or Jon.

So, ok, You welcome, I'm sorry too.

Paul




Article: 24706
Subject: Re: clock skew problem please help!!
From: "Jasper Hendriks" <REMOVE_mijJasper.Hendriks@sci.kun.nl>
Date: Thu, 17 Aug 2000 09:50:35 +0200
Links: << >>  << T >>  << A >>
Thanks!
I found out I can use global signals in altera and I think/hope this solves
my problem also.

Regards,

Jasper

Peter Alfke <peter@xilinx.com> wrote in message
news:39981ED4.460D78F0@xilinx.com...
> If you need to build a shift register, but your clock uncertainty is
large, use
> two flip-flops per bit and clock the even numbered flip-flops on the
rising
> edge, and the odd numbered ones on the falling edge.
> That gives you a clock High or Low time tolerance against clock skew.
> Very safe, but wasteful. But then FPGAs have lots of flip-flops...
>
> Peter Alfke, Xilinx Applications
> ==========================================
> Jasper Hendriks wrote:
>
> > Hello,
> >
> > I having a problem with a signal which needs to be connected to
d-flipflop
> > clock input which is not a globally defined clock such as used with
flex10k
> > devices.
> >
> > The problem is very fundemental one:
> > A change in a signal must occur after a clock change from low->high and
not
> > before it.
> >
> > I'm having this problem with a shift register:
> > suppose we have:
> >
> > DFF1.clk= semiclk
> > DFF2.clk= semiclk + delay1
> >
> > DFF1.q= DFF2.d (after delay2)
> >
> > I need to be sure that delay2 > delay1 + holdtime(DFF2)?
> > How do I accomplish this? Can I assign a special status to my clk line
which
> > cant be a globally defined clock line?
> >
> > Regards,
> >
> > Jasper
>


Article: 24707
Subject: multiplying DLL in Virtex
From: Christophe Heyert <heyertc@rsd.bel.alcatel.be>
Date: Thu, 17 Aug 2000 09:57:38 +0200
Links: << >>  << T >>  << A >>
Hi all,

I was wondering if it is possible to use the Virtex Dll's to create a
clock multiplied by a factor 8.
The application notes only discuss clocks multiplied by 2 or 4.
Thanks...

Christophe
Article: 24708
Subject: Re: Non-disclosures in job interviews, Round One
From: p.kootsookos@remove.ieee.org
Date: 17 Aug 2000 07:58:18 +0000
Links: << >>  << T >>  << A >>
rickman <spamgoeshere4@yahoo.com> writes:

> The funny part was that on the way out they asked me to complete the
> signout procedure. While doing that they noticed that I had not signed
> the mini-NDA. This was pointed out. I pointed out that it was an NDA. I
> was asked to sign it by the HR person. I could not help but laugh a bit.

It sounds like that company has been following procedures which were
laid out in the dim and distant past and that no-one remembers why. It
also seems that the people internal to the company have been doing it
for so long, they cannot understand why others might baulk at it.

Perhaps it says something about the loyalty of the staff (or more
likely, my cynicism), but I have always found unquestioning loyalty a
little off-putting.

I think you are well to be out of the place.

Thanks for the report!

Ciao,

Peter K.

-- 
Peter J. Kootsookos
Wb: www.clubi.ie/PeterK
Article: 24709
Subject: Re: Non-disclosures in job interviews, Round One
From: Jon Kirwan <jkirwan@easystreet.com>
Date: Thu, 17 Aug 2000 01:10:12 -0700
Links: << >>  << T >>  << A >>
On Wed, 16 Aug 2000 23:54:06 -0400, rickman <spamgoeshere4@yahoo.com>
wrote:

>I had my interview with company A this morning. It started out a little
>uneven. I entered and was presented with the application, NDA and some
>other paperwork to fill out. I was also asked to sign into the visitors
>log. However the visitor's log was like none I had ever seen before.
>Each visitor had an entire page with a three paragraph agreement to
>sign. One of the paragraphs was a brief, but broadly worded NDA. Words
>to the effect that I would not divulge any information that I obtained
>while at this facility. 

Interesting.  I've been presented with NDAs, by fax, mail and
directly.  But I haven't yet seen a sign in log like that.  And I've
worked at secret facilities, gov't and otherwise, had the FBI running
around my neighborhood...  I would have enjoyed this as much as you
did!


>I did not sign. 
>
>I just filled in my name and other info and left it at that. 

Excellent.  It was either that or else modify it, as you did the NDA
offered later.


>I then proceded to fill in the application. When it came to the NDA, I
>had decided that the best approach was to add a line to the NDA that
>indicated that a written statement would be provided of all confidential
>information divulged to me. 

Boy, that was a gentle approach.  I'd have simply drawn thick lines
through anything I didn't like.  Last time I had to do that, about a
year and a half ago, it reduced 4 pages to just under 1 page.


>When the first interviewer came to greet me, I spoke with him about my
>concerns. He told me that no proprietary information would be shared
>with me during the interview.

You were being as clear as possible and he reasonably told you the
truth, I suspect.  They probably don't often divulge anything during
interviews, but love to bury their interviewees with formidable
looking paperwork.  And if they ever have a bout with some competitor
over a patent or other squabble, they dredge through their laundry
list of applicants looking for a shred of innuendo that might prove
useful in court.


>I asked then if the NDA was not needed.
>The receptionist said it was required.

I assume you mean that you asked the 1st interviewer and mentioned to
that interviewer about a conversation you earlier had with the
receptionist.


>I stated my need for a written
>statement of what was disclosed to me and the interviewer indicated that
>this was not a problem. I added my line to the NDA and signed it.

All this was in front of him, I assume.  And he naturally presumed
that any reasonable person would agree with your approach.  Soon both
he and you would be surprised by how irrational these processes can
become.


>The interview proceded in the lunch room as they were doing mass
>interviews and the conference rooms were all booked. We spoke for about
>a half an hour during which I was told only superficial information
>about their products and processes. 
>
>A second interviewer began and presented me with a series of "test"
>questions that were well thought out although a bit vague. This actually
>simulated a real project rather well. Again, no information that could
>be considered confidential was disclosed to me. 
>
>The third interview was conducted by a pair of mechanical engineers who
>almost immediately confessed that they were in no way qualified to test
>my knowledge of EE work. So I took the lead and we discussed some of the
>issues relating to integration of electromechanical systems. Nothing
>proprietary was discussed. Only very general statements like, "we use
>photodiodes to detect the light along with high gain amplifiers". 

So typical.  hehe.  Managers just email around and line up a few
likelies to carry the load.  Some volunteer, some enlisted.  Some have
the time or inclination to consider how to handle it, some don't.

But since all the conference rooms were all filled up, it sounds like
they had lots of applicants willing to herd through the NDA cattle
chutes.


>The fourth interviewer was a person that I had spoken to on the phone.
>We prepared to move to another building when a party of several people
>entered and asked if I was Rick Cole. I identified myself and listened
>to an explanation of why they were terminating the interview.

uh oh.   (hehe)


>When I
>altered the NDA, I broke their policy so that they needed to get me out
>of their building.

The policy police had arrived!


>They were polite about it, but it was clear that they
>considered me a threat.

So I gather they weren't smiling?


>So I left on good terms mentioning that they
>were welcome to consider me for future consulting work. I am not sure if
>I will be receiving a call anytime soon.  ;)

Yeah, but were you able to get them to crack a smile?


>In retrospect, I think it would have been better if instead of changing
>the NDA, which I could only expect to be met with considerable
>resistance, I should have simply taken good notes and asked each
>interviewer to sign. This would have been more likely to slip past
>scrutiny and I would likely have an offer that I then would be able to
>accept or turn down. 

Except that once you signed, they'd be in control and they can refuse
to sign your stuff and then where exactly would that leave you?


>The funny part was that on the way out they asked me to complete the
>signout procedure. While doing that they noticed that I had not signed
>the mini-NDA. This was pointed out.

That's nice.  You mean... they proved that they can actually read?


>I pointed out that it was an NDA.

Yup.  A fact they wished you hadn't cared to notice.


>I was asked to sign it by the HR person.

After all that???  You had talked to the 1st interviewer about this
stuff, probably the receptionist too, and maybe others, mentioned your
concerns and made a modification to an NDA in from of him, and they
had decided on that basis to chase you out of the place... and after
all that, they asked you to sign???

Hehe!!!

I would have been in stitches on the lobby floor by then.


>I could not help but laugh a bit.

Me, either.  Cripes!  I absolutely love it!


>I guess they thought I had as much nerve as I thought they did. 

You just weren't their kind of person.  hehe.


>Meanwhile I spoke to a manager from company B. They also have a NDA for
>the interview. We discussed the issues of my signing an NDA and agreed
>that the best thing would be to have the interview and for them to not
>divulge any confidential information. 
>
>So I will interviewing tomorrow with company B. We will see if the
>manager was stepping beyond his bounds and I get the boot in the middle
>of the interview. 

hehe.  I suspect it will go okay.  I can't honestly believe there are
two of those A-type places in the world.  It's just too hilarious.

Jon
Article: 24710
Subject: Board suggestion for high gate count FPGA board
From: Starry Hung <starry@hotpop3.com>
Date: Thu, 17 Aug 2000 17:15:13 +0800
Links: << >>  << T >>  << A >>
Hi,

I am going to buy some prototyping boards with high gate count FPGA such
as Xilinx Virtex or Altera APEX, and would like to hear more suggestions
from you gurus. Xilinx or Altera? Which board is good? etc.

Thanks,

- starry.

Article: 24711
Subject: Re: Permanently programming FPGAs
From: Vladislav Vasilenko <vlad@comsys.ntu-kpi.kiev.ua>
Date: Thu, 17 Aug 2000 13:20:27 +0300
Links: << >>  << T >>  << A >>
But this series (XC17XX )  has some lack-it is one-time programmable
SPROM :( 

Best regards, Vlad.

Ray Andraka wrote:
> 
> The easiest way is to use one of the serial PROMs offered by Xilinx or Atmel.
> The FPGAs will automatically load from these if you set the mode pins
> correctly.  Look on the Xilinx site for the XC17XX prom family
> 
> Ramy wrote:
> >
> > Hello,
> >
> > I've finished programming my FPGA and the system is ready to be used. However, I must reprogram the FPGA after each power-up. I would like to implement a quick and simple solution to "save" the information...such as using a PROM. The FPGA I'm programming is the XC4010E-4PG191I chip using the XCHECKER cable via the serial port. Is there anyway to connect the PROM here instead? (or something else simple?)
> >
> > Also, If any of you know some web-sites that could provide information on programming FPGAs with PROM that would be helpful too.
> >
> > Thanks,
> > Ramy
> 
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com
Article: 24712
Subject: Re: how to use script file in the Design Manager
From: Jan Vermaete <maetej@rsd.bel.alcatel.be>
Date: Thu, 17 Aug 2000 12:48:09 +0200
Links: << >>  << T >>  << A >>
Is this on Unix (or linux, why not) or windows?

On unix, you can do something like this

#!/bin/ksh
ngdbuild -p xc4013e-2-pq240 -sd ../common/ -uc ../common/main.ucf -dd .
../common/main.xnf main.ngd
if [[ $? != 0 ]] then
  echo "NGDBUILD failed."
  exit 99
fi
 .
 .
 .
 .


Call this file whatever you want and make it executable (chmod u+x
filename).
Execute the file with ./file-name .



zheng Daixun wrote:
> 
> I want to ask how to use script file in Xilinx Design Manager.
> I need to run the following command with the parameter by sequence.
> ngdbuild
> map
> par
> bitgen
> promgen
> 
> I know I can write them to a script file.  But how to use this script file?
> What is the suffix of this script file.
> 
> Thanks!
> 
> Hu
> ________________________________________________________________________
> Get Your Private, Free E-mail from MSN Hotmail at http://www.hotmail.com
> 
> --
> Posted from [131.227.8.189] by way of f119.law3.hotmail.com [209.185.241.119]
> via Mailgate.ORG Server - http://www.Mailgate.ORG

-- 
                                              ____________________
______________________________________________\                  /____
 JAN VERMAETE                                  \     ALCATEL    /
 Development Engineer- Space Systems            \              /
 phone : +32-3-829 5328                          \            /
 fax   : +32-3-829 5502                         Berkenrodelei 33
 mailto:jan.Vermaete@Alcatel.be              2660  Hoboken(ANTWERPEN)
                                                     Belgium
_____________________________________________________\    /___________
                                                      \  /
                                                       \/
Article: 24713
Subject: Re: error during synthesis
From: eml@riverside-machines.com.NOSPAM
Date: Thu, 17 Aug 2000 11:04:08 GMT
Links: << >>  << T >>  << A >>
On Wed, 16 Aug 2000 08:24:38 -0700, Philip Freidin
<philip@fliptronics.com> wrote:

>But the section you identified is inside the if(GATE) block, with an
>always @(posedge GATE .... ) controlling it. 
>
>Maybe the issue is that the "posedge intoCounter" does not seem to be
>used in the block, or maybe the final "LOAD15_reload=1'b0;" which is
>in the else clause of "if (GATE)" is confusing it, since this I think mean
>that since I only enter this block if either GATE or intoCounter have a
>posedge, and the else clause means that it wasn't posedge GATE,
>so it must be posedge intoCounter, this implies a FF with two clock pins???

Verilog is a bit obtuse about this, and it does look like a FF with 2
clock pins. However, consider:

1) GATE has a higher priority than intoCounter. If there's a posedge
on intoCounter, but GATE is already active, then the edge on
intoCounter is ignored.

2) When there's a posedge on GATE, the output is only loaded with a
constant - no other signal is loaded through.

3) The output holds its current value until it's told to do something
else.

In principle, then (but see below) this simulates the same as a
conventional async set/reset FF would do; the synth recognises this
and puts in a FF. This code won't work, though, for the reason Rick
pointed out, and also because MODE15, TRIGGER_WORKS, and COUNT_ENABLE
aren't in the sensitivity list. If they change while GATE is active,
then the output won't change, and the simulation will be incorrect.

I'd also replace the blocking assignments with non-blocking (= to <=)
to avoid potential races.

Evan
Article: 24714
Subject: Re: Xilinx design flow with Mentor
From: eml@riverside-machines.com.NOSPAM
Date: Thu, 17 Aug 2000 11:04:33 GMT
Links: << >>  << T >>  << A >>
On Wed, 16 Aug 2000 16:30:45 -0500, Paul Smith <ptsmith@indiana.edu>
wrote:

>It looks like the Mentor FPGA Advantage suite (Renoir, ModelSim, and
>Leonardo) will work for me.  Anyone out there have experience with this
>toolset for the Spartan II target?
>
>I assume I also need the Xilinx Alliance software?

You can't go wrong with ModelSim and Spectrum but, as for Renoir,
forget it unless you're a masochist and you've got lots of spare time.
If you need schematics, try to find a proper schematic tool you can
fit into your design flow. You'll need Foundation or Alliance as well.

Evan

PS: Ok, Mr. Mentor, that wasn't too bad, was it? I trust you won't be
mailing me about this....   :)
Article: 24715
Subject: Re: When will SpartanII be in ditribution
From: eml@riverside-machines.com.NOSPAM
Date: Thu, 17 Aug 2000 11:04:53 GMT
Links: << >>  << T >>  << A >>
On Thu, 17 Aug 2000 04:21:45 GMT, Peter Alfke <palfke@earthlink.net>
wrote:

>Remember also, in Xilinx you can use a bigger part to do the job of a smaller
>part, without a speed penalty.

I thought this had been fixed in Apex, by putting in segmented
routing. Anyone know for sure?

Evan
Article: 24716
Subject: Multilinx cable problem
From: Daixun <daixun.zheng@ee.surrey.ac.uk>
Date: Thu, 17 Aug 2000 04:17:41 -0700
Links: << >>  << T >>  << A >>
Xilinx Software: Chipscope
Cable: Multilinx (Vcc=3.3V)
Prototyping board:XESS XSV-800 (Supporting Virtex-800hq240)
Connection mode: Slave Serial Mode and JTAG mode.
Problem:  
First I connected the Multilinx cable with the board by Slave Serial Mode and download top.mcs in the Chipscope. During the downloading, when the progress is 65%,then the LED on the Multilinx is off and stop to downloading the data. At this time, the working current is down from 1.2A to 0.5A.
Then I change to the JTAG mode (also changing the connection mode), it is the same problem. When the progress is 52%, the LEDs on the Multilinx and on the prototyping boards are all off.
And the downloading stops.

Thanks!
Article: 24717
Subject: Re: Implementing an All Digital PLL in FPGA
From: "John B. Sampson" <johns@xetron.com>
Date: Thu, 17 Aug 2000 07:22:25 -0400
Links: << >>  << T >>  << A >>

Artur Leung wrote in message <399B5718.F6498094@REMOVEittc.ukans.edu>...
>Folks,
>
>     I am working on a digital QPSK demodulator and run into problems of
>designing an all-digital phase-locked loop (ADPLL) for the carrier
>recovery circuitry.
>     The basic design of the QPSK demodulator is being simulated in
>Matlab/Simulink, and the design uses a Costas Loop to recover the
>carrier.  I am closely following the design as suggested in figure 8.38
>(p. 444) of Marvin E. Frerking's book "Digital Signal Processing in
>Communication Systems".  If anyone is interested in the block diagram, I
>can redraw and post the block diagram onto my web page for reference.
>     Anyway, The Costas Loop generates an error signal +/- A/2 *
>sin(theta), where theta is the phase difference between the incoming
>signal and the VCO's output.  I also have an NCO design from my
>colleague which takes two inputs: frequency word and phase offset word,
>and generates the corresponding cosine and sine signal for I/Q
>demodulation.  My biggest problem is how do I design the loop filter to
>map the error signal to the corresponding phase offset word, and how do
>I design the system so that it is stable?  I have read some books on the
>design of phase-locked loops in general, but none of them really dig
>deep into the details of a design: what is the effect of the table size,
>how to design the loop filter (FIR, IIR, etc.), how to design the NCO,
>and how to analyze the loop for ensure it is stable, etc.
>     I would appreciate if someone could point me to a good book, a
>paper, or online reference about the design of such a PLL.  Thank you
>very much.
>
>Artur
>8.16.2000
>

You might want to have a look at the data sheet for Intersil's Digital
Costas Loop IC. I think this IC implements much of what you want, and the
data sheet has lots of details on how it works.

http://www.intersil.com/data/fn/fn3/fn3652/fn3652.pdf

As for your biggest problem, if your application is like many then you
should apply your phase error signal to a proportional + integral (PI)
digital filter that works like this:

y = Ki * sum(e) + Kp * e

The output of this filter is applied as an offset to your nominal NCO phase
increment (which corresponds to your nominal center frequency).

You can get to the equation above by applying a bilinear transform to the
following standard loop filter for a "Type 2 Second Order Loop" which you
see in books:

F(s) = (1 + tau2 * s) / (tau1 * s)

With this loop filter your digital PLL should have zero steady state error
to a phase and frequency step.

John




Article: 24718
Subject: Re: Non-disclosures in job interviews, Round One
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 17 Aug 2000 07:52:43 -0400
Links: << >>  << T >>  << A >>
Jon Kirwan wrote:
> >I then proceded to fill in the application. When it came to the NDA, I
> >had decided that the best approach was to add a line to the NDA that
> >indicated that a written statement would be provided of all confidential
> >information divulged to me.
> 
> Boy, that was a gentle approach.  I'd have simply drawn thick lines
> through anything I didn't like.  Last time I had to do that, about a
> year and a half ago, it reduced 4 pages to just under 1 page.

I don't have a problem with the idea of an NDA for an interview. My
concern is about what happens later due to the ambiguity of what is
covered by the NDA. I don't want to be hamstrung by this NDA when
working for other employers. 

 
> >When the first interviewer came to greet me, I spoke with him about my
> >concerns. He told me that no proprietary information would be shared
> >with me during the interview.
> 
> You were being as clear as possible and he reasonably told you the
> truth, I suspect.  They probably don't often divulge anything during
> interviews, but love to bury their interviewees with formidable
> looking paperwork.  And if they ever have a bout with some competitor
> over a patent or other squabble, they dredge through their laundry
> list of applicants looking for a shred of innuendo that might prove
> useful in court.

This is exactly one of my concerns. Since this is a biotech company, I
think they are very likely to go to the lawyers as soon as they see
someone else working on the same products.

 
> >I asked then if the NDA was not needed.
> >The receptionist said it was required.
> 
> I assume you mean that you asked the 1st interviewer and mentioned to
> that interviewer about a conversation you earlier had with the
> receptionist.
 
No, this was still in the lobby in front of the receptionist. The
engineer/manager was just a little clueless about the paperwork, but the
receptionist had clearly been told to get all the papers signed before
letting anyone into the building. 


> >I stated my need for a written
> >statement of what was disclosed to me and the interviewer indicated that
> >this was not a problem. I added my line to the NDA and signed it.
> 
> All this was in front of him, I assume.  And he naturally presumed
> that any reasonable person would agree with your approach.  Soon both
> he and you would be surprised by how irrational these processes can
> become.

Yes, but I am not sure if either he or the receptionist really
understood what I was doing. I think I was pushing the envelope a bit. 
 

> >The fourth interviewer was a person that I had spoken to on the phone.
> >We prepared to move to another building when a party of several people
> >entered and asked if I was Rick Cole. I identified myself and listened
> >to an explanation of why they were terminating the interview.
> 
> uh oh.   (hehe)
> 
> >When I
> >altered the NDA, I broke their policy so that they needed to get me out
> >of their building.
> 
> The policy police had arrived!
> 
> >They were polite about it, but it was clear that they
> >considered me a threat.
> 
> So I gather they weren't smiling?

The gentleman doing all the talking was actually very apologetic. But at
the same time I sensed that there was a great deal of concern. I am not
sure if they felt that I might be dangeous or if they just thought I had
some intent to "steal" their technology. 

 
> >So I left on good terms mentioning that they
> >were welcome to consider me for future consulting work. I am not sure if
> >I will be receiving a call anytime soon.  ;)
> 
> Yeah, but were you able to get them to crack a smile?

I tried to make a joke of the fact that I would not be getting the
"free" lunch. The speaker immediately started talking about making some
provision for my inconvenience. I think he intended to give me five
bucks and send me to Wendy's. No one smiled.

I also made a point of shaking the engineer's hand and asking him to
consider me for any consulting work they might have. Again no smiles...

 
> >In retrospect, I think it would have been better if instead of changing
> >the NDA, which I could only expect to be met with considerable
> >resistance, I should have simply taken good notes and asked each
> >interviewer to sign. This would have been more likely to slip past
> >scrutiny and I would likely have an offer that I then would be able to
> >accept or turn down.
> 
> Except that once you signed, they'd be in control and they can refuse
> to sign your stuff and then where exactly would that leave you?

If they were not willing to state that I had actually received any
proprietary information, I would be off the hook. 

 
> >I could not help but laugh a bit.
> 
> Me, either.  Cripes!  I absolutely love it!
> 
> >I guess they thought I had as much nerve as I thought they did.
> 
> You just weren't their kind of person.  hehe.

Understatement of the year...


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 24719
Subject: Clock recovery in FPGA
From: oivan@my-deja.com
Date: Thu, 17 Aug 2000 13:10:54 GMT
Links: << >>  << T >>  << A >>
Hi,
Has anyone designed circuit that performs clock recovery from serial
data stream, in FPGA. I would appreciate any info.
Thanks.


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 24720
Subject: Category : Subject : test benchs and CPU core
From: boaz <boaz_h@espro.com>
Date: Thu, 17 Aug 2000 06:20:07 -0700
Links: << >>  << T >>  << A >>
Hi,
I'm looking for a simple behavioral description of a CPU.
I need to simulate a PPC401 that is connected to our FPGA and looking for a model of it or any similar CPU.
Boaz
Article: 24721
Subject: Re: Non-disclosures in job interviews
From: ".`..>Strings" <ggilbert@prsguitars.com>
Date: Thu, 17 Aug 2000 09:26:55 -0400
Links: << >>  << T >>  << A >>
I guess you've never had to protect your assets?
To say "stupid" is short-sighted.  Sorry.  There
are situations that warrant protection.


Jon Kirwan <jkirwan@easystreet.com> wrote in message
news:isaaOU3BtEi0KLcB=c+h+dyJI5cV@4ax.com...
> On Wed, 16 Aug 2000 11:11:51 -0400, ".`..>Strings"
> <ggilbert@prsguitars.com> wrote:
>
> >What are ya gonna do?  Catch 22.  Sign it and see, or go elsewhere.
> >I personally haven't found it so difficult to sign the NDA.
> >It's dependent upon the level of employment, and the directness of
> >competition.
>
> I'd not sign and I haven't ever done so, for a job interview, in the
> nearly 30 years I've been in business.  There hasn't been a need yet.
>
> I suppose if the business was interested in sitting down with me to
> explain in great detail, on paper as an addendum, what exactly it was
> they intended and if it made sense when made concrete that way, I
> might.  But for a job interview, that sounds like a big burden to
> start on.  We'd probably both be better off saving the effort.
>
> No NDAs just for a job interview.  The fact that some people are in a
> bad enough situation, job wise, to need to sign such things doesn't
> make them sensible.  They aren't.
>
> However, I'll have to defer on whether there is substance with which
> to enforce them on.  I don't really know.  But it doesn't seem that
> there is much worthy of enforcement, since there is no way the signer
> knows what they are expected to do under it.  They probably don't
> know, even after they leave.  There is no meeting of the minds and
> probably no value received.  But I'm not an attorney.
>
> It's still stupid to sign one for an interview, in my opinion.
>
> Jon


Article: 24722
Subject: Re: Non-disclosures in job interviews
From: ".`..>Strings" <ggilbert@prsguitars.com>
Date: Thu, 17 Aug 2000 09:29:19 -0400
Links: << >>  << T >>  << A >>
I'm not exposing myself to a potential lawsuit unless I disclose
information.
It's not as difficult as you might think.  Nor as dangerous.
The problem with newsgroups is the topic gets too hyped up.

In fact, a great way to handle the situation is to tell people that
you are interviewing with multiple companies.  The ball actually is in their
court
to not tell you too much stuff.  It MAY prevent an interview.  It should be
on paper.
That is the choice you make.  Oh well.  But it AIN'T THAT BAD.


Article: 24723
Subject: Re: Distributor attitude !!
From: sulimma@my-deja.com
Date: Thu, 17 Aug 2000 13:39:38 GMT
Links: << >>  << T >>  << A >>
On a german holiday, I had a really urgent request, so I called
insight in the netherlands. They had 24 chips listed in munich, so they
suggested, that I should call Insight in germany, the next day.

The usual happend: Inisght refused to sell them to me:
"We have 14 chips, and they are reserved allready".

Xilinx GB confirmed, that Insight listed 24 Stock, of which 10 are
reserved. But Insight Germany insisted, they would have no chips
available.

I finally succeeded to buy two chips from Memec in GB.

During that process the only helpfull sales rep was Insight Norway.
They were extremely friendly, and explained to me, that Xilinx was
very interested that each design project got engineering samples.
They offer to call Xilinx in case I could not get those chips.

But Insight germany clearly preferred to sell the hole bunch of 24
chips to a sinlge customer (e.b. Siemens/Infineon) instead of servicing
a dozen different projects.


I believe, that the distributors did not understand the nature of FPGAs,
that Prototype and high revenue products are an important part of the
market. It's not a market were you can wait for 2M Parts orders as with
FlasRAMs for example.


CU,
	Kolja
> I would like to know the nature of the relationship that others have
> experienced with the licensed FPGA distees.
>
> Sincerely
> Daniel DeConinck
> High Res Technologies, Inc.
>
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 24724
Subject: Re: Non-disclosures in job interviews
From: steveh@link-comm.com (Steve Holle)
Date: Thu, 17 Aug 2000 13:52:31 GMT
Links: << >>  << T >>  << A >>
On Mon, 14 Aug 2000 20:25:41 -0400, rickman <spamgoeshere4@yahoo.com>
wrote:
Is it possible that this discussion should be taken to another group?


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