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Messages from 24350

Article: 24350
Subject: Re: Verilog multiplier in Xilinx...
From: "Austin Franklin" <austin@d44arkroom.com>
Date: 4 Aug 2000 15:12:18 GMT
Links: << >>  << T >>  << A >>
Torbjörn Stabo <etxstbo@kk.ericsson.se> wrote in article
<398A8153.6E265E32@kk.ericsson.se>...
> > Anyone have any Verilog code they'd be willing to share for a 'decent'
> > multiplier?  I am looking for something that can do a 24 x 24
multiply...it
> > can take quite a few cycles, and it's for a Virtex architecture.
> 
> Have you tried Coregen? No source, but it sounds like it's the result
that matters to you..
> 

Thanks for the suggestion, I did look at it, but it doesn't appear to have
a Verilog output mode.
If I don't get the Verilog source (or a protected model) then how do I unit
delay simulate it?


Article: 24351
Subject: Q: JTAG BOUNDARY SCAN FOR FPGA's?
From: Asher Martin-CRAY <martin2@uiuc.edu>
Date: Fri, 04 Aug 2000 10:52:29 -0500
Links: << >>  << T >>  << A >>

Surprisingly there are very few postings (maybe a handful) on
how/why/anything about JTAG Boundary Scan for FPGA's.  And yet, just
about every LSI to VLSI device from CPLD's to FPGA's to Microprocessors
has a JTAG port for boundary scan.  Yet I counted only about 6 newsgroup
postings that seemed relevant to my particular application, FPGA's...

...
My application is quite simple... toggle an an LED and detect that I did
this via Boundary Scan (See Block Diagram Below)... Ok, maybe not quite
that simple but this is fundamentally what is happening...
...

The Boundary Scan that I am doing is somewhat non-conventional. It's
non-conventional in that I don't want to do a Boundary Scan on the pins
of the device -- of the FPGA -- I want to do a Boundary Scan so that I
can capture the INTERNAL logic of the device.  And I want to do all this
without sending my chip into a deep-freeze.  Apparently such a dream is
possible to implement on FPGA's... specifically the Virtex and XC4000
line by Xilinx.  

So, it's your basic, plain and simple boundary scan...  here are some
questions I have about this...

1.) I would like to know first off is anyone knows if this is possible
(not just "yeah, I read about it").  I.E. Is possible to do a readback
via Boundary Scan of the internal logic of an FPGA and make sense of it?

2.) Second, I would like to know if you can capture parts of the FPGA's
logic and then use this to see -- live -- what is happening to the LED's
(See my Block Diagram).  I figure that I should be able to do this since
the values of the pins that the LED's are connected to are determined by
some internal logic inside the FPGA.  How do I find where that internal
logic is located?

3.) Lastly, does anyone know if it is possible to readback a single
frame of data for the Virtex FPGA?  I believe it is...  If this is
possible how do you translate this to your Verilog logic?  Apparently I
am suppose to use the .ll file that is generated by the Xilinx design
manager.  

Anyhow, for those who are working on similar projects I found the
following documents helpful or interesting.

http://www.xilinx.com/xapp/xapp138.pdf
http://www.xilinx.com/xapp/xapp139.pdf
http://www.xilinx.com/xapp/xapp151.pdf

--------------
BLOCK DIAGRAM:
--------------

    +--------------+
    |              |
LED-|              |       (TAP Controller)      
LED-|    Xilinx    +--TDI--+--------+--TDI--+--------+      
    |    VIRTEX    +--TDO--+ Xilinx +--TDO--+ Xilinx +--to-PC
    |     FPGA     +--TCK--+ EEPROM +--TCK--+MultLinx+
    |              +--TMS--+--------+--TMS--+--------+
    |              |
    +--------------+   
 

I would greatly appreciate your advice on the above... 

Take care,
>Asher<

<<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>
 Asher C. Martin
<<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>
WORK ADDRESS: 
   1050 Lowater Road, Room 272
   Chippewa Falls, WI 54729
   (715) 726-4761
<<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>
 martin2@uiuc.edu
 http://www.uiuc.edu/~martin2/
<<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>
Article: 24352
Subject: Re: Who needs all those printed ac parameters?
From: David Kessner <davidk@free-ip.com>
Date: Fri, 04 Aug 2000 09:57:35 -0600
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> Let me pose a provocative question to this smart, diverse, and vocal
> audience. (Shameless flattery might help me get a few additional
> answers...)

Hi Peter!  Long time no talk/type!  :)


> What benefit is there in publishing a select subset of these values
> in the data sheet, necessarily excluding most routing delays ?

I feel that having those values is very useful as a sanity check
and reference.  For example:

Let's say that I'm sitting down, writing a chunk of VHDL.  While
the VHDL is rather generic, there are some things that I can do 
to make it better optimized for one chip architecture than another.
Rather than doing a lot of trial and error to find the more optimal
approach, it can be useful to just read the timing values and make
a semi-informed decision from that.  Take a large MUX...  Is it
better to build it completely out of LUT's, or use the F5/F6 muxes,
or use tristate buffers (remember, this is a contrived example)?
By looking at the timing values, we might be able to quickly throw
out some of these paths and more quickly arrive at an optimal 
solution.

So once I write my VHDL, it'll fail all timing constraints.  I can
then go to the data sheets and look at the timing values there.
By comparing the timing in the data sheets with the timing reports
I can do a 1st order sanity check-- I.E., am I even close?  This will
tell me if my VHDL is getting synthesized into what I really think
it is, or if I'm completely off target.


> How would you react if we reduced the published on-chip delay
> parameters to a limited number of relevant performance values, and
> then referred you to the software tool for the detailed, complete
> and very accurate  analysis ?
> Wouldn't you be better off ?

I would react badly.   And no, I would not be better off.  

For one thing, I don't trust the Xilinx tool set (or any FPGA/ASIC
tool set).  Too many bugs!  And just recently I ran across a "bug"
in the timing report generator (trace) that caused me major problems
due to missing my timing goal by 5 ns (on a 100 MHz clock) even
though trace said I met all my timing.  

I don't believe that FPGA/ASIC tools are robust and reliable enough
to not have some sort of checks and balance system in place.  Having
a detailed data sheet, separate from the software, is very useful for
this.


> This was triggered by the recent debate over the delay differences
> between the 4 different LUT inputs. I feel strongly that the
> designers should not be bothered with such details. The software
> should analyze and synthesize this for you.

In an ideal world, you'd be right.  If you wrote software you'd
be a "no-assembly-programming" kind of guy.  There is nothing 
wrong with that, except that it isn't always the most efficient.
There are some people (a.k.a., Ray Andraka) that will always
want to squeeze out the last drop of performance from an FPGA.
To do this, he/we often need to do things that require very specific
knowledge about the chip architecture.  Software cannot possibly
use all of these to our advantage.

Here's some examples of logic that a VHDL synthesizer + PAR should
take advantage of, but currently Foundation 2.1i+sp6 does not:
	- Tristate registers in Spartan-II
	- Automatic use of carry chain logic to make large and gates.
	- Automatically using block RAM's for large "case...when=>"
	  type "ROM"'s.
	- Automatically inferring LUT/Block RAM's from VHDL arrays
	  (a.la. Synplify)

Until these issues are addressed, we can not view the FPGA
as a "black box".



> This is Peter speaking. It is not an official  Xilinx proposal.

Understood.


> It is just a fresh look at a 40-year old habit.
> Every couple of dozen years one should clean out the closet   :-)

Always a good idea.


David Kessner
davidk@free-ip.com
http://www.free-ip.com
Article: 24353
Subject: Re: Interview Questions
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Fri, 4 Aug 2000 09:14:31 -0700
Links: << >>  << T >>  << A >>
yshamir wrote in message <040d9897.1cdefc39@usw-ex0104-031.remarq.com>...
>Hi Guys
>I will be attending interview for ASIC designer position.
>Can someone tell me what sort of technical questions are asked.
>Tricky questions etc .

"How many registers are required to implement a vending machine?"


--
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"A sufficiently advanced technology is indistinguishable from magic"
     --Arthur C. Clarke



Article: 24354
Subject: 5v -> 1.8v switcher supply for FPGA ??
From: sja@world.std.com (Stuart J Adams)
Date: Fri, 4 Aug 2000 17:50:41 GMT
Links: << >>  << T >>  << A >>
Can anyone recommend a switching regulator
controller with integrated FETs for building
a 5v -> 1.8v switching supply to power an
FPGA ??

I wanted to use the MAX1692 (which only requires
a couple external parts) but it has a 
18 week lead time.

-- Stuart


Article: 24355
Subject: Re: 5v -> 1.8v switcher supply for FPGA ??
From: nweaver@boom.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: 4 Aug 2000 18:00:51 GMT
Links: << >>  << T >>  << A >>
In article <Fys48H.319@world.std.com>,
Stuart J Adams <sja@world.std.com> wrote:
>Can anyone recommend a switching regulator
>controller with integrated FETs for building
>a 5v -> 1.8v switching supply to power an
>FPGA ??

	You look at these?  No external components, 6A maximum
current, and can be quickly ganged together to handle greater current
requirements (5A/module).  Available in 1.5, 1.8, 2.0, 2.5, and 3.3V
output, 3.3 or 5V input.

http://www.lucent.com/networks/power/pdf/949347465__austin_data_sheet_jan_00.pdf
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu
Article: 24356
Subject: Virtex system gate count
From: jimmy75@my-deja.com
Date: Fri, 04 Aug 2000 19:10:55 GMT
Links: << >>  << T >>  << A >>
Hi Folks,

I am pretty confused, how does Xilinx count the system gates for their
Virtex series? I understand that the logic cell count is 4.5 logic cell
per CLB (4.5 4LUT).

Cheers,


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 24357
Subject: Re: Large CPLD
From: mikeandmax@aol.com (Mikeandmax)
Date: 04 Aug 2000 19:14:14 GMT
Links: << >>  << T >>  << A >>
qwerty(must be easy to remember the spelling!) posted
>embedded flash).  
>Lattice has a 840 macrocell device but their software has 
>been less than promising.  They are supposed to give me a new version.  

My best suggestion is to take a good look again at the Lattice 8K family.  We
continue to improve performance on the tools, with version 8.1 just beginning
to ship.  I would recommend working with your local Lattice FAE - he/she can
provide some pretty good support, both locally and 'in factory'.  600 flops -
any connected directly to I/O? - the I/O cell on the 8K gives some nice
flexability, as well as the onchip tristate busses.  High I/O and BGA packages
are offered.  
Good luck with the design - 


Michael Thomas
LSC SFAE
631-874-4968 fax 631-874-4977
michael.thomas@latticesemi.com
for the latest info on Lattice products - http://www.latticesemi.com


Article: 24358
Subject: Packaging info overwhelms timing (was Who needs ... printed ac parameters?)
From: "Marc Klingelhofer" <marckEATSSPAM@omneon.com>
Date: Fri, 04 Aug 2000 20:20:28 GMT
Links: << >>  << T >>  << A >>
    All information is valuable, and although I currently use the tools
rather than the specs to analyze timing, I have used the datasheet
parameters in the past. There's a lot of detail in the Xilinx parts, but
when I start a project I like to make reasonable estimates and it's much
easier with more, rather than less, information. At such a time firing up
tools (which I wouldn't have, when evaluating new devices) to make estimates
doesn't make sense.

    Besides, I wouldn't quibble about 16 pages of AC timing when there's
over 140 pages of packaging info! (Check v1.6 of the Virtex-E datasheet.)
:^0

    Maybe some of this should be broken out into separate documents.
Features and functions are what I look at first. Depending on the
application, packaging or timing is next, followed by the other. Needless to
say, I also end up looking at application notes, the answers database, and
software reference manuals and guides before all's said and done.


                        Marc





Article: 24359
Subject: Re: Who needs all those printed ac parameters?
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 04 Aug 2000 16:24:41 -0400
Links: << >>  << T >>  << A >>
David Kessner wrote:
> I feel that having those values is very useful as a sanity check
> and reference.  For example:


Several of these posts have made me realize that having the AC timing
parameters in the data sheets is not just useful, but absolutely
essential. Initially working a design on paper does so much more than
just letting a designer trade off alternatives. It lets the designer get
a "feel" for the chip and the circuit. This "feel" then allows the
designer to control the entire development process in a useful way.
Without the "feel" of the circuit and chip it is much more difficult to
spot many problems in the design process, independant of whether the
problems stem from the tools or the design. 

So I would say that most good designers *require* the AC timing
parameters to be in the data sheets. 


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 24360
Subject: Re: models of digital ICs
From: com@mail.cmautner (Christian Mautner)
Date: Fri, 4 Aug 2000 22:43:06 +0200
Links: << >>  << T >>  << A >>
On 3 Aug 2000 03:52:43 GMT, Eric L <lamb_baa@hotmail.com> wrote:
>Are there any archives of digital ICs available? I checked the FAQ and there 
>didn't seem to be any. What I need is say a model of a 74373 or whatever 
>(doesn't matter - the more models the better). It would make sense that no one 
>has collected them or even bothered programming them since FPGAs/CPLDs you can 
>usually make your logic very specific to your needs and ICs are pretty basic. I 
>know it's not that hard to program it myself I'd just rather not waste my time 
>on modeling simple IC devices if it's already available. 

I'd say that this very much depends. A simple behavioural model is 
certainly a matter of minutes, but who would need this?
Some vendors have models of their chips, but these models are by far more
complicated, including all the timing specification and checking. 

Btw, I was looking for memory chip models some weeks again, and had to learn
that most vendors stopped giving them away for free, now you have to pay for
a software license of some denali (?) memory model software. I wouldn't be 
surprised if this is going to happen with the 74xx ICs too.

chm.

-- 
cmautner@  -  Christian Mautner
mail.com   -  Vienna/Austria/Europe
Article: 24361
Subject: Re: FPGA selection
From: com@mail.cmautner (Christian Mautner)
Date: Fri, 4 Aug 2000 23:00:20 +0200
Links: << >>  << T >>  << A >>
On Thu, 03 Aug 2000 08:02:50 +0200, Jamil Khatib <Khatib@opencores.org> wrote:
>OK I give more priority on the price and the size of memory that can be
>implemented on it
>

Now, if you could tell us _how_much_ memory you need, it would be easier for
us to give a hint into the right direction. Like spartan/ACEX (cheap) or 
virtex/APEX (large). 

And, if you tell me if you are more a EE or a CS person, I will recommend
Altera or Xilinx, respectively. ;-)

chm.

-- 
cmautner@  -  Christian Mautner
mail.com   -  Vienna/Austria/Europe
Article: 24362
Subject: Re: 5v -> 1.8v switcher supply for FPGA ??
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 04 Aug 2000 17:17:00 -0400
Links: << >>  << T >>  << A >>
Linear Tech makes some good parts. Their data sheets are top notch as
well. Check out the LTC1626. The only problem is their web site which
has no usable device search capability. You can either get one part if
you know the part number or you get all the parts in a given catagory
with no capability for sorting or selection. 

A lot depends on the current level you need. We are using the MAX1644
IIRC. It works well up to about 2 Amps. In fact we are making this as a
module 0.4" x 1.1" which can be surface mounted. Would you be interested
in buying modules instead of building your own? We are currently working
on a similar module that will be closer to 0.5" x 0.6" with the same
current capability. Voltage is resistor programmable from 1.5v to 3.3v
and up. 



Stuart J Adams wrote:
> 
> Can anyone recommend a switching regulator
> controller with integrated FETs for building
> a 5v -> 1.8v switching supply to power an
> FPGA ??
> 
> I wanted to use the MAX1692 (which only requires
> a couple external parts) but it has a
> 18 week lead time.
> 
> -- Stuart

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 24363
Subject: Memory specification
From: Rodolfo Jardim de Azevedo <rjazevedo@ic.unicamp.br>
Date: Fri, 04 Aug 2000 18:45:09 -0300
Links: << >>  << T >>  << A >>
Hi,

	I'm trying to make an experimental board which will use 2 modules of
memory. I will write some VHDL code and use a FPGA to implement it. But
I could not find some information yet. I need SRAM modules (I think some
PCs use them as cache memory, that would be the best choice). Where can
I get some specification of such modules? How to make an interface?
(pinouts, time diagrams, ...)
	In fact, I could even use EEPROMs, because I don't need to change the
system memory too much. But I would prefer SRAM modules due to space
constraints in my board.

		Thanks in advance,

			Rodolfo
Article: 24364
Subject: Re: Memory specification
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 04 Aug 2000 18:32:51 -0400
Links: << >>  << T >>  << A >>
SRAM modules are not terribly common although they do exist. Much more
common are DRAM modules although standard DRAM and EDO DRAM are being
phased out. SDRAM and DDSDRAM (or whatever the acronym is for double
data rate SDRAM) are the newer standards with more years left in them. 

SRAMs are easy to get as chips (other than for allocation problems >:).
But you mention that you want density. EEPROMs are much more dense than
SRAM. EEPROM in the Flash form are nearly as dense as DRAM and about 16
times more dense than SRAM. I can get 64 Mbit Flash chips but I don't
think anyone is making async SRAM bigger than 4 Mbit. Sync SRAMs (the
stuff they use as PC cache memory) comes up to 8 or 16 Mbit, IIRC. 

Of course Flash is much slower than SRAM, but you didn't say what speeds
you need. If you don't need speed, SDRAM can be faster than Flash, but
you need a more complex controller. Of course that all depends on what
you are connecting it to. 

Sound complicated? It is! Until you learn about the different memory
flavors. 


Rodolfo Jardim de Azevedo wrote:
> 
> Hi,
> 
>         I'm trying to make an experimental board which will use 2 modules of
> memory. I will write some VHDL code and use a FPGA to implement it. But
> I could not find some information yet. I need SRAM modules (I think some
> PCs use them as cache memory, that would be the best choice). Where can
> I get some specification of such modules? How to make an interface?
> (pinouts, time diagrams, ...)
>         In fact, I could even use EEPROMs, because I don't need to change the
> system memory too much. But I would prefer SRAM modules due to space
> constraints in my board.
> 
>                 Thanks in advance,
> 
>                         Rodolfo

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 24365
Subject: Re: Who needs all those printed ac parameters? (sw should be the data
From: Hernan Saab <hernan@synplicity.com>
Date: Fri, 04 Aug 2000 17:21:37 -0700
Links: << >>  << T >>  << A >>


From version to version of place and route software, the speed
characterization
of FPGAs will be more accurate (sometimes more aggressive)
for a given speedgrade.

I propose the data sheet be sw generated by the current version
of the place and route tool, route delays included.
A nice GUI that generates user specified  timing
AC specs will be nicely appreciated. This way, the report file
will not be a 2MB mammoth.

As of today, current place and route technology (any vendors) has
a very hard time making a 2 million gate FPGA run at 60MHZ or more
at a  push of a button with just plain synthesis. The worst timing
violations
need to be analyzed very carefully in order to improve timing.

Keep in mind users like Ray need this type of information to make
some speed aggresive ASIC designs possible in FPGAs.



eml@riverside-machines.com.NOSPAM wrote:

> <the original post isn't on my server, so this is probably in the
> wrong place...>
>
> My vote is to keep the detailed specs on paper somewhere, though not
> necessarily on the data sheet. It's too difficult to use the tools to
> get detailed info before starting a design.
>
> I'd be happy to see less information on the real datasheet, but it
> would have to be more usable. Remember the old advice that used to
> appear here regularly - "50% CLB, 50% routing"? Ok, this is far too
> inaccurate to put on a datasheet, or anywhere else, but at least it
> had the merit that you could get a first approximation to how fast
> your block would go. The main factor that originally stopped me from
> using Xilinx devices was that I couldn't get any feel for how fast
> they were by reading the datasheet.
>
> Perhaps you could come up with a better way to estimate relative CLB
> and routing ratios - maybe a datasheet section giving some typical
> routing delays for tracks of various lengths and fanouts, and then a
> subset of the CLB and IOB delays. Have a look at Lattice's old
> 1000-series datasheets (they may still be the same - I've only got the
> '94 databook). It's not directly applicable, of course, since the
> architecture is different and the routing is more deterministic, but
> the idea is nice - a block diagram including CLB and IOB elements, and
> some potential ways to join them up, referencing some delay and
> typical routing parameters. This would give new (and old) users a
> really nice way to get a feel for a block before starting the design.
>
> Evan

--



Hernan Javier Saab
Western Area Applications Engineer
Email: HERNAN@synplicity.com
Direct Phone: 408-215-6139
Main Phone: 408-215-6000
Pager: 888-712-5803
FAX: 408-990-0295
Synplicity, Inc.
935 Stewart Drive
Sunnyvale, CA  94086  USA
Internet <http://www.synplicity.com >


Article: 24366
Subject: Re: Memory specification
From: "Eric Braeden" <braeden@erinet.com>
Date: Fri, 4 Aug 2000 21:49:21 -0400
Links: << >>  << T >>  << A >>
What about the RAM they put on High end video cards.
I'm looking at one right now that had 32 MB of on-board
RAM and it only has two chips. What is this?
Eric



Sender: eric@ruckus.brouhaha.com
Article: 24367
Subject: Re: Memory specification
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 04 Aug 2000 19:07:25 -0700
Links: << >>  << T >>  << A >>
"Eric Braeden" <braeden@erinet.com> writes:
> What about the RAM they put on High end video cards.
> I'm looking at one right now that had 32 MB of on-board
> RAM and it only has two chips. What is this?

128 Megabit SDRAM or SGRAM chips, most likely.  The chips are probably
each organized as 4 Megawords of 32 bits, although other organizations
are also available.
Article: 24368
Subject: CoolRunner Tri-State...
From: Chipman <andyf@telerama.com>
Date: Fri, 04 Aug 2000 22:42:44 -0400
Links: << >>  << T >>  << A >>
I am using a CoolRunner XCR3128A device.  Everything works great except
an 8 bit bus interface that has tri-state outputs.  The output buffers
never drive the bus even though the enable signal for the buffers is
active.  I have brought this signal out to look at it and it is
correct.  The simulation works great, there are no errors from the
compiler and fitter, yet the output buffers appear that they are not
recognized.  This is a Synario interface.  The software is the XPLA
Professional, Version 3.31 downloaded from the web.

Any input would be appreciated.

Thanks!

Chipman

Article: 24369
Subject: 8251 USART
From: Peter Alfke <palfke@earthlink.net>
Date: Sat, 05 Aug 2000 03:58:09 GMT
Links: << >>  << T >>  << A >>

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Eduardo Augusto Bezerra wrote:

  Hi

  <Does anybody know the price of a synthesizable 8251A core? I'm also
  looking for a Manchester encoder/decoder. Is there a place where I
  can find these cores for free? I'll decide which FPGA to use in my
  design as soon as I find the cores. >


A Manchester encoder is trivial, essentially an XOR.
A Manchester decoder is described in the Xilinx XCell magazine in 1995.
The design uses only three XC3000 or XC4000 or Spartan CLBs.

http://www.xilinx.com/xcell/xl17/xl17-30.pdf

Peter Alfke, Xilinx Applications

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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Eduardo Augusto Bezerra wrote:
<p>&nbsp; Hi
<p>&nbsp; &lt;Does anybody know the price of a synthesizable 8251A core?
I'm also
<br>&nbsp; looking for a Manchester encoder/decoder. Is there a place where
I
<br>&nbsp; can find these cores for free? I'll decide which FPGA to use
in my
<br>&nbsp; design as soon as I find the cores. >
<br>&nbsp;
<p>A Manchester encoder is trivial, essentially an XOR.
<br>A Manchester decoder is described in the Xilinx XCell magazine in 1995.
<br>The design uses only three XC3000 or XC4000 or Spartan CLBs.
<p><u><A HREF="http://www.xilinx.com/xcell/xl17/xl17-30.pdf">http://www.xilinx.com/xcell/xl17/xl17-30.pdf</A></u>
<p>Peter Alfke, Xilinx Applications</html>

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Article: 24370
Subject: Clock quadrupling
From: Peter Alfke <palfke@earthlink.net>
Date: Sat, 05 Aug 2000 04:00:04 GMT
Links: << >>  << T >>  << A >>
"R. T. Finch" wrote:

> Is there a cheesy way to quadruple an input clock frequency to a FPGA
> (XC4000 series) internally ? I'd like to take an 8MHz input to 32MHz
>

You have two choices, both "cheesy":

1.
First double the clock by differentiating the clock edge, as described
in the Xilinx 1994 data book, page 9-7.
Input clock drives one side of an XNOR gate, which then drives a
flip-flop
clock input.
Flip-flop Q feeds back onto its own D input through an inverter (
typical
toggle connection)
The inverted Q, i.e. the D input also drives the other XNOR input.
The output of the XNOR is the double frequency output.

The High pulse width is determined by the round-trip delay of clock-to-Q

plus the inverter. If necessary, one can lengthen this creatively.
 In this particular case, you must lengthen it substantially.

Then do the doubling  again.

The problem is that the first differentiation ( clock High time) must be

substantially longer than the second one.

2.
Create a free-running oscillator from a multi-stage buffer with an odd
number of inversions, feeding back on itself. Use a counter to stop
after 4 counts.
Your oscillator must run faster than 32 MHz, even at high temp and low
Vcc. So it should normally run around 100 MHz, to be safe.

Both methods are, as you say "cheesy", but if you have no alternative...

Peter Alfke, Xilinx Applications








Article: 24371
Subject: Look-up tables in Altera
From: Peter Alfke <palfke@earthlink.net>
Date: Sat, 05 Aug 2000 04:01:45 GMT
Links: << >>  << T >>  << A >>
Since Altera never answers...
Topologically, the tree-structure decoder has different delays from the
four
address inputs.
Xilinx software knows these differences, and the delay calculator will
show
each delay, and in a constrained design will pick the optimal input pin.

So, it's all out there in the open.
I know very little about Altera...

Peter Alfke, Xilinx Applications


Article: 24372
Subject: Virtex DLL and external clocks
From: Peter Alfke <palfke@earthlink.net>
Date: Sat, 05 Aug 2000 04:03:05 GMT
Links: << >>  << T >>  << A >>
seamus wrote:

> My question is, what does this method of using two DLL's gain you
> over using just one DLL in the standard implementation and
> driving the externally generated clock to the Xilinx part as well
> as the other external chips?  I don't see any benefit.

The DLL acts as a servo loop that can "eliminate" the delay from an
input to an output ( by inserting the right amount of additional
delay, so that the delay of a continuously running clock seems to be
zero).
This loop can have only one perfect output. If you try to drive two
signals, like a chip output plus an internal clock, you can achieve
zero clock delay for only one of the two, and the other one will
have an uncontrolled and uncontrollable delay, which depends on the
difference between certain on-chip buffer and routing delays.

Peter Alfke, Xilinx Applications




Article: 24373
Subject: Which one is good coding style?
From: Peter Alfke <palfke@earthlink.net>
Date: Sat, 05 Aug 2000 04:04:29 GMT
Links: << >>  << T >>  << A >>
"K. Orthner" wrote:

> <snip>  I'm implementing a bunch of 1-shot
> timers in some unused space in a Xilinx FPGA.  When the input bit goes
to
> '1', I asynchronously reset my counter to all '1's.  Then, I count
down
> with a rather slow clock.  My output is all the bits of the counter
'or'ed
> together.

Pretty clever! If the trailing edge of asynchr. preset collides with the
first
count clock, this problem gets resolved in the LSB only. It does not
matter if
other bits are still being preset for a few nanoseconds, or have been
released
earlier.

At first look I was worried about the notoriously dangerous parallel
resolution of an asynchronous interface, but your design is safe.

Peter Alfke, Xilinx Applications



Article: 24374
Subject: VirtexE FF set/reset
From: Peter Alfke <palfke@earthlink.net>
Date: Sat, 05 Aug 2000 04:06:59 GMT
Links: << >>  << T >>  << A >>
Jian Lin wrote:

> I use XCV200-6 to implement my design
> I found some delay for 4-input LUT is 2.08ns and some delay for
4-input LUT is 1.18ns.
> Why there are deferents?
>

The LUT delays in this part and speed grade are between 0.6 and 0.8 ns.
You seem to be looking at a different, composite delay.

Peter Alfke, Xilinx Applications






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