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Messages from 1225

Article: 1225
Subject: Is anybody using FPGA's to do PCI interfaces?
From: courtrig@hweng.syr.ge.com (Glenn Courtright 7650)
Date: 18 May 1995 10:39:00 GMT
Links: << >>  << T >>  << A >>
There's an excellent article in the February issue of  Integrated
System Design (formerly ASIC & EDA) entitled "Practical
State Machine Design Using VHDL".  The example and code
developed is centered around a PCI interface.  The article starts
on page 58 and the author is Sundar Rajan.
Good Luck!




Article: 1226
Subject: AT&T FPGA support ftp site
From: aweir@onsys.com (Alan Weir)
Date: 18 May 1995 13:36:32 GMT
Links: << >>  << T >>  << A >>
Subject says it all. Does anyone have the address or failing that
a BBS number. I would like to see their PCI / VHDL implementation.
-- 
========================================================
Alan Weir                         Voice  708-247-2210
On Systems Inc.                   Fax    708-549-8940
14090 Lambs Lane,                 e-mail aweir@onsys.com
Libertyville, IL 60048



Article: 1227
Subject: Re: 1000 pin fpga's ?
From: wolf@aur.alcatel.com (William J. Wolf)
Date: 18 May 1995 15:04:59 GMT
Links: << >>  << T >>  << A >>
From: cburns@crl.com (Charlie Burns)
> (not logic bound, but io bound) 

Have you looked at XC4000H devices?  
They have twice the I/O for the same logic.

You can get fairly high pin counts, BGAs, QFPs at a cost 
much less than an Aptix package/device.  Maybe not 1000 
pins but you can get 223/240 pin devices for lower cost 
than 240 pin devices with twice the logic (which you 
don't need).  Was this your point?

---
- Bill Wolf, Raleigh NC
- My opinions, NOT my employer's




Article: 1228
Subject: Lattice isp Development Tools
From: root@ee142.ex.ac.uk (root)
Date: Thu, 18 May 1995 21:45:41 GMT
Links: << >>  << T >>  << A >>

We have just obtained the Lattice isp starter kit. As an introducton,
the software is acceptable. I'd like to find out what other tools are
in use to suport the Lattice ispLSI 1k,2k and 3k families. I.E. are
there any PD tools I can run under Linux (or dos/windows/OS2).

The support for Orcad apparently retails at over 800 pounds sterling !
We can't afford that, this cost may push us away from Lattice into a
vendor supported by Orcad but I want to examione the p.d. offerinfs
first.

Why do development tools cost so much ? 



--
                             --------------------                            
First Law of Bicycling:
     No matter which way you ride, it's uphill and against the wind.
 			
	        ,__o  		Phil Vossler
	       -\_<,			Electronics Workshop
	     (*)/'(*)				Dept of Physics
     University of Exeter, Stocker Rd, Exeter, Devon ,UK. 
	   tel: 44-392-264100 	fax: 44-392-264111
 		email: p.j.vossler@ex.ac.uk


Article: 1229
Subject: Re: Is anybody using FPGA's to do PCI interfaces?
From: Leon Heller <Leon@lfheller.demon.co.uk>
Date: 19 May 1995 07:06:39 +0100
Links: << >>  << T >>  << A >>
In article <3pf844$73c@morgan.vf.mmc.com>
           courtrig@hweng.syr.ge.com "Glenn Courtright 7650" writes:

> There's an excellent article in the February issue of  Integrated
> System Design (formerly ASIC & EDA) entitled "Practical
> State Machine Design Using VHDL".  The example and code
> developed is centered around a PCI interface.  The article starts
> on page 58 and the author is Sundar Rajan.
> Good Luck!

The 1994 Lattice Handbook has a section on using a Lattice ispLSI device
for PCI bus implementation.

Leon
-- 
Leon Heller, G1HSM                | "Do not adjust your mind, there is
E-mail leon@lfheller.demon.co.uk  |  a fault in reality": on a wall
Phone: +44 (0)1734 266679         |  many years ago in Oxford.


Article: 1230
Subject: FPGA market shares
From: klindwor@tech17.informatik.uni-hamburg.de (Andre Klindworth)
Date: 19 May 1995 08:01:38 GMT
Links: << >>  << T >>  << A >>

I am looking for data on the respective market shares of
mayor FPGA/CPLD vendors. Does anyone know where to look for it?
Any pointers appreciated.
-- 
-----------------------------------------------------------------------
Andre' Klindworth                   Universitaet Hamburg, FB Informatik
klindwor@informatik.uni-hamburg.de  Vogt-Koelln-Str.30, D-22527 Hamburg
                                    Phone: +49 40 54715-501,  Fax: -397


Article: 1231
Subject: Re: FPGA market shares
From: Ruchir Puri <rpuri@bnr.ca>
Date: 19 May 1995 14:36:09 GMT
Links: << >>  << T >>  << A >>
klindwor@tech17.informatik.uni-hamburg.de (Andre Klindworth) wrote:
>
>I am looking for data on the respective market shares of
>mayor FPGA/CPLD vendors. Does anyone know where to look for it?
>Any pointers appreciated.
>-- 

Reference : Programmable Logic - News and View , Jan'95 issue.

----------
1994 SALES
----------
Xilinx  : 321.3 million $s
Altera  : 198.8 million $s
Lattice : 134.0 million $s
Actel   : 76.0  million $s

--Ruchir



Article: 1232
Subject: Re: FLEXlogic opinions?
From: billaltfae@aol.com (Billaltfae)
Date: 19 May 1995 13:03:33 -0400
Links: << >>  << T >>  << A >>
Greeting to all:

>> roger@coelacanth.com (Roger Williams) wrote:
>> Is the FLASHlogic family (the EPX740/780/8160) *really* related to the
>> FLEX 8K series? 

No.  The FLEX8000 family was developed by Altera while the FlexLogic
family was developed by Intel.
Altera aquired the FlexLogic family when it purchased the Intel PLD biz. 
Because of the confusion
caused by the similarities of the two names, Altera renamed the FlexLogic
family to FlashLogic, justified
by the fact that the newest member of the family (EPX8160) uses a FLASH
cell for the non-volatile 
storage in the device.  Altera is continuing to expand the FlashLogic
family, adding the EPX880 
sometime this year.

The architectures of the two families are totally different, with the
Flex8000 parts using a look-up table 
based logic element and the FlashLogic parts using a more traditional
sum-of-products macrocell structure.  
The interconnect structure is totally different also.  Architecturally,
the FlashLogic parts are closer to the 
Altera MAX7000 family than they are to the FLEX8000 parts.  This is true
in size as well.  The *largest* 
FlashLogic part (EPX8160) is specified as a 3200 usable gate device, while
the *smallest* FLEX8000 
part is 2500 gates, and ranges all the way to 16,000 gates.   

The only hangup right now is that MAX+Plus II does not yet support the
FlashLogic stuff.  You still have 
to use the Intel developed PLDShell tool.  It is still free and is
available though Altera sales reps and 
distributors.  The latest version is 4.01.  MAX+plus II si supposed to
support the FlashLogic family by 
the end of the year.  

>>  Guess I'll have to get the Viewlogic
>> libraries, as the MaxPlus-II schematic editor is pretty Byzantine.

All of the libraries for Viewlogic Powerview (workstation based) are on
the Max+Plus II CD ROM.  
The libraries for Viewlogic Workview and ProSeries (PC based) have to be
downloaded from the 
Altera BBS (408-954-0104).

>> (I *do* wish that Altera would decide if they're in the chip business,
>> or the software business.)

Ya gotta be in both these days, witness the aquisition of NeoCad by
Xilinx.

---

Bill Harris
Altera FAE
Raleigh, NC


Article: 1233
Subject: Re: PLDShell Plus
From: billaltfae@aol.com (Billaltfae)
Date: 19 May 1995 13:09:54 -0400
Links: << >>  << T >>  << A >>
msnook@armltd.co.uk (Mark Snook) wrote:

>> Does anyone know where I can download a copy of PLDShell Plus software
>> fro Altera FlashLogic parts.

I presume by your address that you are in the UK.
Contact:
Altera UK Limited
Solar House
Globe Park, Fieldhouse Lane
Marlow, Bucks SL7 ITB
England
TEL: 1628 488-800
FAX: 1628 890-078

They should be able to point you to the right place.
Altera distys in the UK are Ambar-Cascom and Thame Components


Article: 1234
Subject: 6502 processor
From: sutera@nwu.edu (Thomas A. Sutera)
Date: 19 May 1995 18:46:19 GMT
Links: << >>  << T >>  << A >>
I am now looking for a Verilog/VHDL description of a 6502 processor or 
equivalent.  We have descriptions of simple and very complex processors, but 
nothing in-between.  If anyone knows where I can find one, please let me 
know.  Thanks.
-- 
Thomas A. Sutera
Northwestern University
sutera@nwu.edu



Article: 1235
Subject: Multi-chip partitioning for XC4k devices
From: jshah@cs.iastate.edu (Jatan Shah)
Date: 19 May 95 22:45:02 GMT
Links: << >>  << T >>  << A >>
Are there any multi chip partitioners for XC4000 devices which can be used to ge-nerate  multiple XNF files from a single XNF file given the resource constraints for each of the smaller devices into which the bigger design is to be partitioned into?

It appears to me that it would'nt be very difficult to build a tool to do it.
Particularly, with reference to Synopsys, it is possible to generate an XNF 
which has CLBs instead of the Xilinx primitives recognized by XACT ppr.  This
XNF, though completely useless for ppr, can be used as an input to a partitioner  A partitioner at the CLB level would be simple (almost trivial) because the 
different types of cells that are to be partitioned are very limited (CLBs, IOBs and buffers).

Please feel free to comment because I am seriously planning to build  a tool to do this if it is not already available.

Jatan



Article: 1236
Subject: Re: FLEXlogic opinions?
From: roger@coelacanth.com (Roger Williams)
Date: 20 May 1995 17:22:17 GMT
Links: << >>  << T >>  << A >>
   >> Is the FLASHlogic family (the EPX740/780/8160) *really* related to the
   >> FLEX 8K series? 

   No.  The FLEX8000 family was developed by Altera while the FlexLogic
   family was developed by Intel...Because of the confusion
   caused by the similarities of the two names, Altera renamed the FlexLogic
   family to FlashLogic...

With good reason--I got an amazing number of responses from people
telling me about *FLEX8000* parts.  (Fortunately, I'm using those too,
so the advice was useful...)

-- 
Roger Williams
Coelacanth Engineering  |  Numeric stability is probably not all
Middleborough, Mass     |  that important when you're guessing...


Article: 1237
Subject: Re: Can the X4010 replace a X4003 ?
From: nsoria@hertz.elee.calpoly.edu (Nelson Soria)
Date: 20 May 1995 21:05:33 GMT
Links: << >>  << T >>  << A >>
In article <fliptronD8rBI0.GJo@netcom.com>,
Philip Freidin <fliptron@netcom.com> wrote:
>In article <D8q4M1.2ro@animal.inescn.pt> jca@picasso.inescn.pt (Jose Carlos Alves) writes:
>>
>>Hi,
>>
>>I've made a card for the PC-AT bus with one X4003 and one
>>X4010 in daisy chain configuration (the 4003 is first in the chain).
>>The bitstream is downloaded from the PC bus,
>>through some logic to decode i/o addrs and generate the
>>clock and data from the PC port. It worked fine till
>>I replaced the 4003 by one 4010D. Now the PC crashes when my program
>>starts sending the configuration bits. I'm using a bit stream generated
>>for a 4010 (without the 'D'), but as far as i've seen, it is identical
>>to the 4010D (but what happens to any RAM cell, if they are in the
>>configuration bitstream ?).
>>
>>Any ideas about this ?
>>
>>Thanks for any help
>>
>>jose'
>
>
Maybe you need to recompile your bitstream for the particular hardware you
are using (i.e., for the 4010D).

Nelson Soria





Article: 1238
Subject: Re: affordable fpga design tools?
From: "Eric T. Brewer" <Eric@cup.portal.com>
Date: 20 May 1995 21:55:25 GMT
Links: << >>  << T >>  << A >>
stephens@nic.cerf.net (Robert Stephens) wrote:
>I am interested in migrating some of my 22v10 level
>pld designs to fpgas. Is there a public domain, shareware
>or *cheap* commercial compiler/fitter available? Even'
>a full featured demo would be a help. I hate to spend
>Kbucks just to evaluate the potential benifits of consolidation.
>                                         ^e
>Cypress is offering a great deal on Warp2, but it only
>supports plds and cplds. The Warp3 (which does support fpgas)
>pricing isn't mentioned so I assume it is exorbitant.
>
>                          TIA
>                              Bob S.
>
>
>-- 
>Bob Stephens                           
>stephens@cerf.net   | "Just machines that make big decisions
>310-540-3525 vox    |  programmed by fellas with compassion and vision"
>310-540-8380 fax    |                           - Donald Fagen

Check out QuickLogic. They have a $99 eval package which is there complete
set of tools minus the programming software. Their parts/tools are nice
beacuse they are auto-place and auto-route as well as high speed. Also, they
have Verilog synthesis!

Cheers,
eric




Article: 1239
Subject: Re: PLDShell Plus
From: roger@coelacanth.com (Roger Williams)
Date: 20 May 1995 23:24:18 GMT
Links: << >>  << T >>  << A >>
   Does anyone know where I can download a copy of PLDShell Plus software
   fro Altera FlashLogic parts. 

You can FTP a full copy of v4.0 (11/94, FTP'ed from Intel just before
they sold off the FLEXLogic family to Altera) from us:
	ftp://coelacanth.com/e/pub/pldshell.zip

-- 
Roger Williams
Coelacanth Engineering  |  Numeric stability is probably not all
Middleborough, Mass     |  that important when you're guessing...


Article: 1240
Subject: Re: 6502 processor
From: Roland <rsimonis@mcs.com>
Date: 21 May 1995 02:26:14 GMT
Links: << >>  << T >>  << A >>
sutera@nwu.edu (Thomas A. Sutera) wrote:
>I am now looking for a Verilog/VHDL description of a 6502 processor or 
>equivalent.  We have descriptions of simple and very complex processors, but 
>nothing in-between.  If anyone knows where I can find one, please let me 
>know.  Thanks.
>-- 
>Thomas A. Sutera
>Northwestern University
>sutera@nwu.edu
>
There is a flashy App. Note from Data I/O Synario describing the use of 
their product to implement a 6502 VHDL processor in an FPGA. Call DataI/O 
for info.
So long.
-Roland 



Article: 1241
Subject: Re: affordable fpga design tools?
From: Jack Mott <jackm@pmafire.inel.gov>
Date: Sun, 21 May 95 13:53:21 GMT
Links: << >>  << T >>  << A >>
On 20 May 1995, Eric T. Brewer wrote: 
> Check out QuickLogic. They have a $99 eval package which is there complete
> set of tools minus the programming software. Their parts/tools are nice
> beacuse they are auto-place and auto-route as well as high speed. Also, they
> have Verilog synthesis!

I have used Altera HDL with some success.  Is Verilog synthesis another
type of HDL?  When I last looked at Quicklogic a year-and-a-half ago, they
only had schematic entry, but not HDL.

The Quicklogic parts are fast (like using 10K ECL), but they are one-time
programmable.  In addition, the fuse burning process seems to be much
slower than the EEPROM or UV-EPROM parts I have used. 

An engineer using Quicklogic at the time also told me that the software 
timing simulation was not so good.  He claimed to be able to do a better 
job by looking at the data sheet and working things out with paper and 
pencil.

I would appreciate hearing comments from others who are more experienced 
using Quicklogic.

Charles Mott



Article: 1242
Subject: Re: affordable fpga design tools?
From: "Eric T. Brewer" <EricB@best.com>
Date: 21 May 1995 19:57:31 GMT
Links: << >>  << T >>  << A >>
Jack Mott <jackm@pmafire.inel.gov> wrote:
>On 20 May 1995, Eric T. Brewer wrote: 
>> Check out QuickLogic. They have a $99 eval package which is there complete
>> set of tools minus the programming software. Their parts/tools are nice
>> beacuse they are auto-place and auto-route as well as high speed. Also, they
>> have Verilog synthesis!
>
>I have used Altera HDL with some success.  Is Verilog synthesis another
>type of HDL?  When I last looked at Quicklogic a year-and-a-half ago, they
>only had schematic entry, but not HDL.

They have Verilog HDL now. They are releasing VHDL synthesis sometime in August
was the last I heard.

>>The Quicklogic parts are fast (like using 10K ECL), but they are one-time
>programmable.  In addition, the fuse burning process seems to be much
>slower than the EEPROM or UV-EPROM parts I have used. 

Being OTP is probably my only gripe with them. But given their process, they have
no other choice. Unlike XILINX, QuickLogic forms a connection (link) at the desired
routing intersection. The advantage is speed, no silicon at each interconnect, and
density.

>An engineer using Quicklogic at the time also told me that the software 
>timing simulation was not so good.  He claimed to be able to do a better 
>job by looking at the data sheet and working things out with paper and 
>pencil.

I would say the tools are very robust these days. You would be hard pressed to do
a better job by hand. If there are a handful signals (or more if you desire) which
need to be faster than the default routing you can:
    1. Turn the placer/router to a higher level of optimization. It just takes
							longer to place and route.
				2. Define what the worst case delay you want the net to be. The placer/router
       will do its best to meet or exceed the criteria. In my experience, if it
       cannot meet the criteria, it cannot be done in the part.

>I would appreciate hearing comments from others who are more experienced 
>using Quicklogic.
>
>Charles Mott
>

cheers,
eric




Article: 1243
Subject: Searching >Programmable Logic - News and View<
From: Michael Tremel <michaelt@sparc23.m30x.nbg.scn.de>
Date: 22 May 1995 12:43:04 +0100
Links: << >>  << T >>  << A >>
Hi out there,

on 19.05.1995  rpuri@bnr.ca (Ruchir Puri) mentioned the
following as a reference for the infos he gave.

> Reference : Programmable Logic - News and View , Jan'95 issue.

I never heard of this journal. Where can i find it?

So long and thanks for all the fish

michael
michaelt@m30x.nbg.scn.de


Article: 1244
Subject: What's happening with NeoCAD?
From: Roland Welte <100070.3321@CompuServe.COM>
Date: 22 May 1995 12:18:31 GMT
Links: << >>  << T >>  << A >>
Just a few questions regarding the future of NeoCAD. They
may have been answered in this newsgroup before, but due to
my vacation I might have missed them.

  - What company bought NeoCAD (Xilinx, AT&T) ?
  - Since NeoCAD was the only design system for FPGAs from
    Motorola, what is happening with the support for these
    devices, now that NeoCAD is not independent anymore.
  - Will NeoCAD eventually disappear?

Half a year ago, I decided that NeoCAD is the tool of choice
for our company's FPGA designs, mainly because of its
device independent philosophy. But now it looks quite
differently.

Thanks a lot for any help to the above. I'll appreciate it.

Roland


Article: 1245
Subject: Xilinx Download
From: sjba@ukc.ac.uk (S.J.B.Acock)
Date: Mon, 22 May 95 13:44:19 GMT
Links: << >>  << T >>  << A >>

I would like to know if anyone has a simple Xilinx XC4000 series fpga download
program which would allow me to send a raw bit file or exormax file via a PC
parallel port (lpt1) to a Xilinx device working in slave serial mode.
I have XACT software installed on a PC and a workstation allowing downloading
from the XDE, but a simple DOS based downloader for the PC would be preferable.

Thanks in advance.

Steven Acock,
Electronic Laboratories,
University of Kent,
Kent,
England CT2 7NT
sjba@ukc.ac.uk



Article: 1246
Subject: Re: Is anybody using FPGA's to do PCI interfaces?
From: Paul Walker <paul@walker.demon.co.uk>
Date: 22 May 1995 18:35:39 +0100
Links: << >>  << T >>  << A >>
Pardon if this repeats something already said, but I've just received a disk 
and info pack from Xilinx for PCI, which includes VHDL for an XC3100A,
ABEL for XC73108 and XC7354, and VHDL for a 73144.

They all contain disclaimers about the design being thought to be correct 
but Xilinx take no responsibility for their use.

Has anyone any experience of using them?

This pack seems to have arrived as a result of my mailing pci@xilinx.com
with a request for info. 

Altera's publicity also claims to offer something on PCI, but I have so far
had no joy in extracting any info.

Paul
-- 
Paul Walker                 4Links for technical help
+44 1908 566253             P O Box 816, Two Mile Ash
paul@walker.demon.co.uk     Milton Keynes MK8 8NS, UK


Article: 1247
Subject: Re: FLEXlogic opinions?
From: Paul Walker <paul@walker.demon.co.uk>
Date: 22 May 1995 18:35:40 +0100
Links: << >>  << T >>  << A >>
In article <3pij15$m3t@newsbf02.news.aol.com>
           billaltfae@aol.com "Billaltfae" writes:
[snipped]
>... Intel developed PLDShell tool.  It is still free and is
>available though Altera sales reps and 
>distributors.  The latest version is 4.01.  

Not sure it is any different from V4.01, but I was using V3.0 and
suffering from a couple of bugs, and received V5.0 today.

Although the older versions have a few bugs, most of the bugs are
livable with. Overall, the combination of PLDshell with a 
download cable and reloadable devices, all for not much more
than $100, is very good value.

Let's hope Altera stay with it.

Paul
-- 
Paul Walker                 4Links for technical help
+44 1908 566253             P O Box 816, Two Mile Ash
paul@walker.demon.co.uk     Milton Keynes MK8 8NS, UK


Article: 1248
Subject: Re: PLDShell Plus
From: Chris G Abbott <Chris@ruatha.demon.co.uk>
Date: 22 May 1995 18:47:06 +0100
Links: << >>  << T >>  << A >>
Why don't you just phone a distributor, they will send you FREE OF CHARGE
a box containing the manual, disk and every think you need.

-- 
God Bless

Chris Abbott
============================================================================


Article: 1249
Subject: Re: Searching >Programmable Logic - News and View<
From: billaltfae@aol.com (Billaltfae)
Date: 22 May 1995 14:26:47 -0400
Links: << >>  << T >>  << A >>
Greetings:

> Reference : Programmable Logic - News and View , Jan'95 issue.

> I never heard of this journal. Where can i find it?

I missed the original post, so I'm shooting in the dark here.  Altera
publishes a customer newsletter called News and Views.  There are usually
a number of technical articles along with the usual sales and marketing
hype.  If you want to subscribe (its free) you can e-mail your data to
Martin Wong at martinw@altera.com.  FAX # is (408)954-0348.

Regards,
Bill H.




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