Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 28050

Article: 28050
Subject: Re: 3V -> 5V clock signal level conversion
From: "Jim Pennell" <zapspam@ix.netcom.com>
Date: Tue, 19 Dec 2000 19:46:13 -0800
Links: << >>  << T >>  << A >>
   Another possibility is the LT1016 chip...   It is a fast comparator/TTL
out device that we use with a 10 MHz clock and it works very nicely.

   There is a Texas Instrument equivalent that may be easier to get,
although I forget the exact part number....   TI3016 or 3018 ???


   I have used it for years, and it will work nicely to convert from 3.3 to
5 volt logic.


               Jim Pennell

=======================

   jpennell

   at

   ix.netcom.com




Article: 28051
Subject: Re: Setup violation
From: Philip Freidin <philip@fliptronics.com>
Date: Tue, 19 Dec 2000 22:13:48 -0800
Links: << >>  << T >>  << A >>
On Mon, 18 Dec 2000 17:41:08 -0800, Peter Alfke <peter.alfke@xilinx.com> wrote:
>Greg Neff wrote:
>> II know nothing about Xilinx chip-level implementation of flip-flops,
>> but you say that they are cross-coupled inverter structures.  Thinking
>> about this, it seems to me that the only way that they can be
>> metastable is if they are stuck in the middle of their analog operating
>> areas.
>
>Yes, agreed

I agree too

>> IOW, they are both functioning as high gain inverting
>> amplifiers, with VOUT=VIN.  In this case, I would not be surprised to
>> see some brief oscillation before the inverter pair snaps back to
>> stable digital operating area states.
>
>No, I don't see how such a prmitive structure can sustain an oscillation.
>Once it leaves its metastable balanced state, there is no way to return
>back to or through it. ( As is possible in multi-stage structures popular
>with TTL technology)

Lots of ways for it to oscillate. The switching noise on VDD can push it
back the other way as it is comming out of the mid point, including the
noise of the latch itself. There is delay in the loop, and although the
phase shift is 360 degrees, a pulse could theoretically race around the
loop, and by pulse, it may be only picovolts high, away from the exact
midpoint voltage. Note that at the rate at which the output voltage of
the metastable latch moves away from the mid point to the final stable
state is an exponential. I.E.
If we measure |dV| ( | exact stable voltage - current voltage | ) at 100pS
into resolution it will be small (a few millivolts),
at 200pS it is much bigger (10s of millivolts), at 300pS it is WAY bigger
(100s of millivolts), and at 400pS, it is volts, and the metastable is well on
the way to being resolved.
During the start of resolution, there isnt much dV for the amplifier to
amplify, and so it is easier to kick the latch back to equilibrium. In
CMOS, the latch is probably drawing static power, because both
upper and lower transistors are on. So as it starts to move, the
current is changing, and so generates noise on VDD and GND.


>> In an earlier post you said something about the FF output always being
>> at a valid level, but taking longer to switch.  It seems to me that
>> cross-coupled inverters are inherently stable if they are at valid
>> logic levels.
>
>Well, the master latch ( the only one that can go metastable) is not
>brought out even from the flip-flop ( let alone the chip ). So you always
>have the gain of the slave latch in series. That's why ( I think) the
>flip-flop Q will never stay in the middle.

Ummmm, no.  The slave can go metastable too, because there is a
finite point in time when it takes its last view of what the master is
doing (For a rising edge FF, it is on the falling edge). If the master
was metastable, then for all of clock high time, its output is at the
midpoint, and the slave latch is probably in the analog region too.
If the silicon is identical (and it is damn close, only a few
microns away), then when the pass gate between master and
slave opens (when clock goes low) and the slave latch loop is
closed, it may well be close enough to its mid point to be in the
metastable region. If this were not true, you would never see
metastables that resolve during the second part of the cycle,
when the only thing driving the output is the slave, as it is isolated
from the master. Even if the ballance point for the slave is different
than for the master, if the master starts resolving as the clock falls,
then just enough energy injection from the master to the slave can
cause the slave to be metastable. 


>> Using the test in XAPP094 you wouldn't see the actual
>> output voltage because the output is buried on the chip, so maybe the
>> output voltage is stuck at Vth until the latch stabilizes.  What do you
>> think?
>
>As I said, the gain of the slave latch makes that (almost) impossible.

Thanks for the "almost" Peter.

There aren't many things Peter and I disagree on and this is the area
in which we do. Peter has pointed out several times that the current
silicon has far superior metastable characteristics, and the flipflops
go metastable far less often, and resolve the metastable event
typically in far fewer nanoseconds. So fast now that his previous
testing methodology cant get enough data. Great. I look forward to
the data for Virtex-II, which I suspect will be stunning. Peter has
usually followed up by saying that because things are so much
better, designers "almost" dont have to worry about metastability.
Or "it's not as big a problem as before".

Here's my religion:

	Either it is a problem or it isn't.

If it is a problem, then deal with it. Saying you can "almost" ignore
it is not acceptable, as there are too many "enginners" who will take
this as a license to ignore it. 

Peter and I agree that according to everything we have read, there
is no such thing as a flipflop that is metastable free, and therefore
metastables will continue to happen. The best support for engineers
is for vendors to supply some data to help the dedicated engineer
mitigate the problem by correct design. Peter/Xilinx has done more
of this than any other. Thanks.

>But I also question the importance of the question.
>For data, it is irrelevant whether it oscillates or not.

Assuming good design practice, where the data is not used
until it is known to be stable.

>And anybody using a metastable-prone signal as a clock should have his/her
>head examined.

Or removed.

>
>Peter Alfke
>
>> Greg Neff
>> VP Engineering

Philip Freidin

Philip Freidin
Fliptronics

Article: 28052
Subject: Re: 3V -> 5V clock signal level conversion
From: Nial Stewart <nials@sqf.hp.com>
Date: Wed, 20 Dec 2000 08:06:08 +0000
Links: << >>  << T >>  << A >>
Greg Neff wrote:
> > >
> >
> > Greg, it's a Spartan II so using a pull up on the op is
> > OK, it's not actively clamped.
> >
> > Nial.
> >
> 
> Take a look at page 4 of the Spartan II data sheet (V1.1).  It says
> that for non-5V compliant outputs, a clamp diode may be connected to
> VCCO.  So to be safe, make sure that you are using a 5V compliant
> output mode such as LVTTL.
> 

Should have said

"Greg, it's a Spartan II so using a pull up on the op is
OK _with out configuration (ie LVTTL)_ , it's not actively
clamped".


Nial.

Article: 28053
Subject: Re: dual port ram for altera
From: murray@pa.dec.com (Hal Murray)
Date: 20 Dec 2000 08:23:40 GMT
Links: << >>  << T >>  << A >>

> Simultaneous writes to the same location:
> The last clock wins, but in order to guarantee that, it must be Tbccs (~3
> ns ) later than the earlier clock. Otherwise there is even a small chance
> of corrupted data ending up in the memory location. Both writes clobbering
> each other.

Just checking to make sure I understand...

"corrupted data" means some of the bits were written
by one side and some of the bits were written by the other.  Right?

So this only matters if the RAM is more than 1 bit wide.
-- 
These are my opinions, not necessarily my employers.  I hate spam.

Article: 28054
Subject: Methods to speed up timings by hdl?
From: "Akito" <akito@nergal.net>
Date: Wed, 20 Dec 2000 08:25:50 GMT
Links: << >>  << T >>  << A >>
Greetings to any who read this post.

Currently I am writing a piece of a larger puzzle for a FPGA project,
using HDL via Xilinx Foundation.

Presently, my decode & process routine looks like this:

data_buf<=(I0 AND I1) WHEN FUNCTION_CODE =     "0010" ELSE (repeats similar
to this up to the binary count of 1011)

pretty much I get about 51.635nS propagation but I am shooting for about
40nS.

I'm using grade 4 of the XC4005E FPGA, using grade 1 i get 32nS but that
price is a tad high for the budget I am after, therefor,
any suggestions or help would be appreciated.

Thanks.



Article: 28055
Subject: Re: really fast counter in SpartanXL?
From: murray@pa.dec.com (Hal Murray)
Date: 20 Dec 2000 08:30:26 GMT
Links: << >>  << T >>  << A >>

[Context is making a fast counter to measure the width of a pulse.]

> In your case, just stay away from global clocks. Route the input clock
> signal to the clock input of a single CLB flip-flop ( best placed on the
> left edge of the device.) Make it toggle, using a tight feedback loop
> (<2ns)
> Then use this Q as a clock for the next CLB, configured as a 2-bit counter,
> since the two flip-flops have a common clock. Use the highest Q as clock
> for the nect CLB, etc.
> That gives you a ripple counter with the best possible input resolution (
> yes, and an awful ripple delay.)
> 400 MHz should be no problem.

Could you get an extra half bit of resolution by clocking things
on the other edge of the clock too?

I think that requires that both the clock-enable (pulse being measured)
and the clock be be routed to 2 CLBs with matching routing delays.

-- 
These are my opinions, not necessarily my employers.  I hate spam.

Article: 28056
Subject: HOT AREAS IN FPGAs
From: Saqib <saqib_03@hotmail.com>
Date: Wed, 20 Dec 2000 09:10:45 GMT
Links: << >>  << T >>  << A >>
It is said that the three areas of DSP, Communications and Networking
are very hot in FPGAs designs. DSP is ok...but what specifically is
meant by "communications"..does it include products like Encryptors,
Forward error correction products (Viterbi , RS codecs),Modems...or it
means telecommunications..if yes what are specific cores that are
suitable for FPGA implementation...
And what does NETWORKING mean..what are specific networking products
implemented in FPGAs?
Thanx

--
--saqib yaqub--


Sent via Deja.com
http://www.deja.com/

Article: 28057
Subject: Re: Question about Xilinx pins at high-frequency
From: "fred" <x@y.z>
Date: Wed, 20 Dec 2000 09:24:56 -0000
Links: << >>  << T >>  << A >>

"David Hawke" <dhawke@xilinx.com> wrote in message
news:3A3FAC55.A431F4BA@xilinx.com...
> If you use Map -pr b then the mapper will place the
registers for the Output Enable in the IOB, this is only the
case however if there is one source register per pin (eg 32
bit bus with single OE register will not be placed in the
IO). This will give you faster switch-over and make doing
ZBT interfaces much easier...
>
Thank you Dave, the one OE reg per IOB thing is obvious when
you look at it but I would have missed it - just saved me an
age in debug time.

Talk soon,

dmac



Article: 28058
Subject: Re: Methods to speed up timings by hdl?
From: Kent Orthner <korthner@hotmail.nospam.com>
Date: 20 Dec 2000 18:25:53 +0900
Links: << >>  << T >>  << A >>
Hi, Akito.

I'm far from an expert on the 4000 series, but I glances at the 
databook for the 4000E, and for the -4 speed grade, it gives a 
propogation delay of 4.7ns through H.

Using H gives you 5-input logic function, and your routine
has six inputs:  You can do this in two levels.  The logic
propogation delay alone will be less than 10ns.  Even with 
a hefty routing penalty, you should still be able to come 
in under 40 ns without too much difficulty.

If you open FPGA Express indepentdantly, and find where 
you synthesys results are, you should be able to look 
at a schematic version of the synth results.  It's not pretty,
but it might help you figure out what your synthesizer is doing.

You may also want to put this routine in a process of it's own; 
it might help the synthesizer out a bit. (Or maybe not; just a guess.)

HTH, Kent


"Akito" <akito@nergal.net> writes:

> Greetings to any who read this post.
> 
> Currently I am writing a piece of a larger puzzle for a FPGA project,
> using HDL via Xilinx Foundation.
> 
> Presently, my decode & process routine looks like this:
> 
> data_buf<=(I0 AND I1) WHEN FUNCTION_CODE =     "0010" ELSE (repeats similar
> to this up to the binary count of 1011)
> 
> pretty much I get about 51.635nS propagation but I am shooting for about
> 40nS.
> 
> I'm using grade 4 of the XC4005E FPGA, using grade 1 i get 32nS but that
> price is a tad high for the budget I am after, therefor,
> any suggestions or help would be appreciated.
> 
> Thanks.

Article: 28059
Subject: Re: jtag for fpga
From: harveytwyman@my-deja.com
Date: Wed, 20 Dec 2000 09:56:58 GMT
Links: << >>  << T >>  << A >>
JTAG has several uses apart from being able to download configuration
data to devices in the chain.

Devices in the chain are recognised by their unique ID, thus you only
have to configure the devices you want - not all of them.

Having parallel busses connected to every FPGA device on the board
would use TOO MANY valuable resourses such as:

Device I/O Pins
PCB Track Area

"Boundary Scan" is the other important feature that JTAG offers. The
ability to test the surrounding PCB track continuity as well as the
device's functionality is essential, especially on todays automatic PCB
assembly lines.

Devices are usually configuration on power-up so speed isn't so
important. However if devices are re-configured "on-the-fly", this may
be a problem, so would possibly justify a parallel bus configuration.

--
>                    ____________________________________________
>                   /                                           /|
>                  /         H A R V E Y   T W Y M A N         / |
>                 / ----------------------------------------- / \|
>             ===/ Department of Electronics,                / \/======
>            ===/ University of Kent.                       / \/======
>           ===/ Canterbury. U.K.                          / \/======
>          ===/ ----------------------------------------- / \/======
>         ===/ ABOUT ME: http://www.Twyman.org.uk/CV.htm / \/======
>        ===/ ----------------------------------------- / \/======
>       ===/ EMAIL ME: H.E.Twyman@ukc.ac.uk            / \/======
>      ===/___________________________________________/ \/======
>     ====|                                           |\/======
>    =====|___________________________________________|/======
>

  "Steven Zedeck" <saz@sonusnet.com> wrote:
> Hi:
> Assuming you always plan to program
> the FPGAs via an on-board microprocessor (such as a PowerPC),
> and you have many FPGAs (all different Xilinx) devices, why would you
want to use a JTAG chain ?
>
> Wouldn't it make sense to use serial
> parallel mode and create seperate image files so that you can
download any FPGA image you want at any time ? It also allows you to
upgrade (in the field) any image without having to program/update them
all. Comments ?
>
> Also, has anyone done any analysis of the image sizes and time to
program a JTAG chain with many FPGAs or to not use JTAG at all and
> to program each image individually, one at a time ?
> Thanks,
> Steve
>


Sent via Deja.com
http://www.deja.com/

Article: 28060
Subject: Re: Reverse-engineering FPGA's
From: harveytwyman@my-deja.com
Date: Wed, 20 Dec 2000 10:13:38 GMT
Links: << >>  << T >>  << A >>
We had a postgraduate student project a few years ago that investigated
the internal interconnections of a Xilinx device. The old Xilinx 2064
device was chosen as being the simplest.

He mananged to develop a method of discovering the interconnect
positions purely experimentally.

This was done by changing a single bit in the programming code file and
then observing the difference in Xilinx's "World View" graphics package
option.

Phrases like "needles in haystacks" springs to mind.

I think the project demonstrated that the major FPGA companies even
then, "built in" randomness into their internal configuration schemes
to make reverse engineering more difficult.

He found that a certain configuration bit in one device would be
totally different to another device, even within the same family.

Hence the project finished with those conclusions.

----------------------------
H A R V E Y      T W Y M A N

Department of Electronics,
University of Kent.
Canterbury. U.K.

ABOUT ME: http://www.Twyman.org.uk/CV.htm
EMAIL ME: H.E.Twyman@ukc.ac.uk
----------------------------


In article <3A256F33.6483C1C@libertysurf.fr>,
  Isabelle <isabelle.todescato@libertysurf.fr> wrote:
> Hello, I am a newbie in FPGAs and am interested especially in
> test-vector synthesis.
>
> My - naive - questions are :
>
> 1.Is it possible from the program file of some FPGA to deduce a gate
or
> functional block model for the internals of that FPGA ?
> 2.Do the FPGA manufacturers pusblish the mapping from program files to
> FPGA internals ?
>
> Thanks a lot for reading this
>
> Fabien TODESCATO
>
>


Sent via Deja.com
http://www.deja.com/

Article: 28061
Subject: Hand Soldering a PQ208 - It looks tough to do
From: harveytwyman@my-deja.com
Date: Wed, 20 Dec 2000 10:32:37 GMT
Links: << >>  << T >>  << A >>
Being involved with student projects, the ability to handle the latest
SMT devices has been essential.

I've developed techniques over the last few years that are successful
for beginners as they only require simple hand tools.

My Web Page below describes these techniques in detail:

http://www.Makaton-Signs.org.uk/PCB-Techniques

    ___________________________________________
===|                                           |===
===|        H A R V E Y    T W Y M A N         |===
===| ----------------------------------------- |===
===| Department of Electronics,                |===
===| University of Kent.                       |===
===| Canterbury. U.K.                          |===
===| ----------------------------------------- |===
===| ABOUT ME: http://www.Twyman.org.uk/CV.htm |===
===| ----------------------------------------- |===
===| EMAIL ME: H.E.Twyman@ukc.ac.uk            |===
===|___________________________________________|===



Sent via Deja.com
http://www.deja.com/

Article: 28062
Subject: Re: FPGA and Board for Microprocessor Design?
From: sulimma@my-deja.com
Date: Wed, 20 Dec 2000 10:37:43 GMT
Links: << >>  << T >>  << A >>
In article <3A3FA329.C726271@jetnet.ab.ca>,
  Ben Franchuk <bfranchuk@jetnet.ab.ca> wrote:
> Simon Gornall wrote:
> > I'll need to figure out how easy/stable it is when you get rid of
the
> > 24MHz clock. Presumably there's a good reason why they've crippled
it
> > like this
>
> This could be for VGA output. One clock does all.
As would a 48 MHz or 96 Mhz or 144 MHz Clock. So they really might
have a problem with the power supply or similar.

I use the ICS525-01 together with a bunch of DIP switches. This gives
me whatever clock I want (some kHz to 160MHz) from a single crystal.

You should be able to pathe this to the BED board.

CU,
	Kolja


Sent via Deja.com
http://www.deja.com/

Article: 28063
Subject: Re: Spartan2 and industrial temperatures
From: "Karl Olsen" <karl@micro-technic.com>
Date: Wed, 20 Dec 2000 11:44:17 +0100
Links: << >>  << T >>  << A >>
Peter Alfke wrote in message <3A3F981D.5F35D4D0@xilinx.com>...

>You named the two "problem areas".
>Also, since we did not production-test these parts at the low temperature,
>we do not guarantee the parameters.


Hi again,

ds001_3.pdf mentions 500mA startup current for commercial parts, and nothing
for industrial.  Is the startup current expected to be larger for industrial
parts in the whole -40°C to 100°C range?

Another thing -- I haven't found much info about Spartan2 dynamic power.
The closest is the Virtex power estimator at
http://support.xilinx.com/cgi-bin/powerweb.pl
Can this be used with any accuracy for XC2S15 and XC2S30 designs, if I
select XCV50 in the power estimator?

Thanks,
Karl Olsen



Article: 28064
Subject: Re: FPGA and Board for Microprocessor Design?
From: harveytwyman@my-deja.com
Date: Wed, 20 Dec 2000 10:51:37 GMT
Links: << >>  << T >>  << A >>
I'm currently working on a teaching board that contains an Altera Flex
10K FPGA and a PIC16F877 processor.

I have a Web Page describing it in detail:

http://www.Makaton-Signs.org.uk/uPL-Trainer

--
    ___________________________________________
===|                                           |===
===|        H A R V E Y    T W Y M A N         |===
===| ----------------------------------------- |===
===| Department of Electronics,                |===
===| University of Kent.                       |===
===| Canterbury. U.K.                          |===
===| ----------------------------------------- |===
===| ABOUT ME: http://www.Twyman.org.uk/CV.htm |===
===| ----------------------------------------- |===
===| EMAIL ME: H.E.Twyman@ukc.ac.uk            |===
===|___________________________________________|===


In article <91mdlq$pi6$1@nnrp1.deja.com>,
  hoyte@ucsu.colorado.edu wrote:
> I recently worked on a senior project where we designed a 16-bit RISC
> microprocessor, and implemented the design in an FPGA. I'd like to be
> able to do something similar on my own, and I'm trying to find a good
> FPGA/board combination that is (relatively) affordable, and compatible
> with the Xilinx student edition software. If anyone has any
suggestions,
> they would be greatly appreciated.
>
> Thanks,
> Eric Hoyt
>
> Sent via Deja.com
> http://www.deja.com/
>


Sent via Deja.com
http://www.deja.com/

Article: 28065
Subject: Re: Methods to speed up timings by hdl?
From: "fred" <x@y.z>
Date: Wed, 20 Dec 2000 11:08:09 -0000
Links: << >>  << T >>  << A >>

"Akito" <akito@nergal.net> wrote in message
news:i2_%5.486$PF.36271@newsread1.prod.itd.earthlink.net...
> Greetings to any who read this post.
>
> Currently I am writing a piece of a larger puzzle for a
FPGA project,
> using HDL via Xilinx Foundation.
>
> Presently, my decode & process routine looks like this:
>
> data_buf<=(I0 AND I1) WHEN FUNCTION_CODE =     "0010" ELSE
(repeats similar
> to this up to the binary count of 1011)
I think it would be useful to see a little more of your code
but the IF then ELSE structure that you are using is a clue
your problem. This structure creates a prioritised structure
with a long sequential delay:

if ... then
  else
    else
      else
        else
          else

I hesitate to suggest a solution without fully understanding
your requirement but a CASE statement generally suits FPGA
architectures better:

case ADDRESS is
when 0 =>
  A <= X
when 1 =>
  B <= X
when 2 to 7 => -- optional range
  C <= X
when 8 | 10 | 12 | 14 => -- optional discrete addrs
  D <= X
.
.
when others =>
  nul
end case

This will be quicker but there are many other tricks if you
want to go reeeeeeealy fast.

You may also wish to subscribe to news:comp.lang.vhdl and
view the excellent FAQ for that group at
http://www.vhdl.org/comp.lang.vhdl/FAQ1.html (part 1 with
links to parts 2 - 4).

Fred




Article: 28066
Subject: ttl in cpld
From: zdenko.baksa@zg.tel.hr
Date: Wed, 20 Dec 2000 14:29:43 +0100
Links: << >>  << T >>  << A >>
Hi,
    Wanted 74194 PLD (and others ttl-s to)  fil for CPLD ( gal16v8 or
etc. )
I use CUPL, PALASM an/or Vantis.

Thanks.


Article: 28067
Subject: Re: Question about Xilinx pins at high-frequency
From: "Andrew Ince" <andrew.ince@gecm.com>
Date: Wed, 20 Dec 2000 13:39:28 -0000
Links: << >>  << T >>  << A >>

"fred" <x@y.z> wrote in message news:91ptuj$3t5$1@news7.svr.pol.co.uk...
> "David Hawke" <dhawke@xilinx.com> wrote...
> > If you use Map -pr b then the mapper will place the
> registers for the Output Enable in the IOB, this is only the
> case however if there is one source register per pin (eg 32
> bit bus with single OE register will not be placed in the
> IO). This will give you faster switch-over and make doing
> ZBT interfaces much easier...
> >
> Thank you Dave, the one OE reg per IOB thing is obvious when
> you look at it but I would have missed it - just saved me an
> age in debug time.

But It is only obvious if you look for ways the tool may fail to work.

As users we should expect tools to do simple tasks like automatic
duplication.

Andrew Ince



Article: 28068
Subject: 18v04 programming
From: Petter Gustad <dev.null@dev.null.org>
Date: 20 Dec 2000 14:48:11 +0100
Links: << >>  << T >>  << A >>

Hi,

I'm using two 18v04's to load a Xilinx xcv1000e (virtex-e) device.
However, I'm having problems programming the 18v04's. 

I have an old DataIO 2900 which gives me device over-current faults, I
borrowed a DataIO 3980, but I constantly get verify errors. I've also
been using the Xilinx parallel port and jtag programmer (3.3iSP6) but
I keep getting verify errors and invalid idcode values. However, if I
run the id_code test with a million iterations it works fine, but if I
try to do erase or program it fails.

So what do you use to program the 18v04's?

Thanks
Petter
-- 
________________________________________________________________________
Petter Gustad     8'h2B | (~8'h2B) - Hamlet     http://home.sol.no/~pegu
#include <stdio.h>/* compile/run this program to get my email address */
int main(void) {printf ("pegu\100computer\056org\nmy opinions only\n");}


Article: 28069
Subject: Re: Question about Xilinx pins at high-frequency
From: "Pascal C." <>
Date: Wed, 20 Dec 2000 06:33:34 -0800
Links: << >>  << T >>  << A >>
A few things:

1.  for case 1, we did create a 32-bit registered OE and did PAR with the "-pr b" switch.  What tools do you use David? Personnally, I am using Foundation 3.2i.5 (note: I installed SP6 yesterday and MAP crashed pathethically even when started by the GUI!) with FPGA Express 3.4.3.  Is it possible that FPGA Express made it impossible for the PAR to recognize the OEs and place them properly (I did prevent it from merging the logic)?

In case 2, the chips the FPGA is connected to are about an inch away.  I believe that the measurement was made with a 1" ground, but I'll have to check up on that (I didn't take the measurement myself).

I am already setting the DRIVE through the UCF.  The problem is that PAR won't do its thing when the drive is below 12 mA...  

One trick that was recommended to me was to synthesize with a drive of 12 mA (if that's what it takes), then using FPGA Editor to manually modify each of the pins.  However there are 91 pins to change, and the prospect isn't too thrilling (it wouldn't matter, except we're not yet in production, and the idea of repeating these steps each time I synthesize isn't too exciting)...

Thanks for all your help!

Pascal

Article: 28070
Subject: FPGA'2001 Call for Participation
From: tessier@spock.ecs.umass.edu (Russell Tessier)
Date: 20 Dec 2000 14:33:39 GMT
Links: << >>  << T >>  << A >>
FPGA 2001 Advance Program
2001 ACM/SIGDA Ninth International Symposium on Field Programmable Gate Arrays

Doubletree Hotel, Monterey, California
February 11-13, 2001

http://www.ecs.umass.edu/ece/fpga2001

Sponsored by ACM/SIGDA
with support from Altera, Xilinx, Agere Systems, Cypress and Actel 
 
 
Join us for the ninth ACM/SIGDA International Symposium on Field Programmable 
Gate Arrays (FPGA 2001), the premier forum for novel work in all areas related 
to FPGA technology. This year's symposium features twenty-four papers and 
twenty-three poster presentations describing cutting-edge FPGA research. 
Authors from universities, research laboratories and commercial vendors 
present new work on topics ranging from applications and reconfigurable 
computing to device architecture and design tools. An entire session is 
devoted to applications in image and video compression. Paper sessions are 
separated by ample time to peruse the poster presentations and discuss the 
latest FPGA news.

The panel this year addresses the question of what FPGAs will look like in 
the era of systems-on-a-chip. Is it now clear that programmable logic should 
be combined with ASICs and microprocessors? How should they be combined? What 
tools are needed to support these devices? 

FPGA 2001 provides a relaxed atmosphere for informal information exchange, 
networking and stimulating discussions with the leaders in FPGA research 
and development from industry and academia as well as the next generation 
of FPGA researchers

If you are at all interested in FPGA technology and developments, you won't 
want to miss this event. 
 
Organizing Committee
--------------------
General Chair:   Scott Hauck, U. Washington
Program Chair:   Martine Schlag, UCSC
Publicity Chair: Russ Tessier, U. Mass.-Amherst
Finance Chair:   Steve Trimberger, Xilinx
 

Program Committee
-----------------
Ray Andraka, Andraka Consulting
Mike Bershteyn, Quickturn
Richard Cliff, Altera
Jason Cong, UCLA
Andre DeHon, Caltech
Eugene Ding, Lucent
Carl Ebeling, U. Washington
Scott Hauck, U. Washington
TingTing Hwang, Natl. Tsing Hua U.
Sinan Kaptanoglu, Adaptive Silicon
Tom Kean, Algotronix
Arun Kundu, Actel
Miriam Leeser, Northeastern U.
Wayne Luk, Imperial College
Margaret Marek-Sadowska, UCSB
Jonathan Rose, U. Toronto
Martine Schlag, UCSC
Herman Schmit, CMU
Charles Stroud, UNC-Charlotte
Russ Tessier, U. Mass.-Amherst
Steve Trimberger, Xilinx
Steve Wilton, U. British Columbia


PROGRAM
-------
SUNDAY, FEBRUARY 11, 2001

6:00PM Registration
7:00PM Welcoming Reception

MONDAY, FEBRUARY 12, 2001

7:30AM Continental Breakfast and Registration
8:20AM Opening remarks: Scott Hauck, Martine Schlag

Session 1. Placement and Routing
Chair: Carl Ebeling, University of Washington
8:30AM Timing-Driven Placement for Hierarchical Programmable Logic Devices. 
       Michael Hutton, Khosrow Adibasmii and Andrew Leaver, Altera.
8:50AM LRoute: A Delay Minimal Router for Hierarchical CPLDs. 
       K.K. Lee, Synopsys; Martin D.F. Wong, Univerity of Texas at Austin.
9:10AM A Crosstalk-Aware Timing-Driven Router for FPGAs. 
       Steven J.E. Wilton, University of British Columbia.
9:30AM Runtime and Quality Tradeoffs in FPGA Placement and Routing. 
       Chandra Mulpuri and Scott Hauck, University of Washington.

9:50AM Coffee Break and Poster Presentations.

Session 2. Technology Mapping 
Chair: Steven Wilton, University of British Columbia
10:50AM Performance-Driven Mapping for CPLD Architectures. 
        Deming Chen, Jason Cong, Milos Ercegovac and Zhijun Huang, 
        University of California, Los Angeles.
11:10AM Simultaneous Logic Decomposition with Technology Mapping in FPGA 
        Designs.  Gang Chen and Jason Cong, University of California, 
        Los Angeles.

11:30AM Poster Presentations.

12:00PM Lunch

Session 3. Routing Architectures
Chair: Tom Kean, Algotronix
1:30PM Using Sparse Crossbars within LUT Clusters. 
       Guy G. Lemieux and David M. Lewis, University of Toronto.
1:50PM Detailed Routing Architectures for Embedded Programmable Logic IP Cores.
       Peter Hallschmid and Steven J.E. Wilton, University of British Columbia.
2:10PM Mixing Buffers and Pass Transistors in FPGA Routing Architectures. 
       Mike Sheng and Jonathan Rose, University of Toronto.

2:30PM Coffee Break and Poster Presentations.

Session 4. Applications
Chair: Ray Andraka, Andraka Consulting
3:30PM Reprogrammable Network Packet Processing on the Field Programmable Port 
       Extender (FPX). John W. Lockwood, Naji Naufel, David E. Taylor and 
       Jon S. Turner, Washington University.
3:50PM Fast Implementations of secret-key block ciphers using mixed inner- and 
       outer-round pipelining. Pawel Chodowiec, Po Khuon, and Kris Gaj, 
       George Mason University.
4:10PM Algorithmic Transformations in the Implementation of K-means Clustering 
       on Reconfigurable Hardware. Mike Estlick, Miriam Leeser, Northeastern 
       University; John J. Szymanski, James Theiler, Los Alamos National 
       Laboratory.

6:00PM Dinner
        
7:30PM Panel: Is marriage in the cards for programmable logic, microprocessors 
       and ASICs?
       Moderator: Sinan Kaptanoglu, Adaptive Silicon
       Panelists: John East, Actel,
                  Tim Garverick, Adaptive Silicon,
                  Scott Hauck, University of Washington,
                  Danesh Tavana, Triscend,
                  Steve Trimberger, Xilinx,
                  Ronnie Vasishta, LSI Logic.
                  (Additional panelists to be announced)
        The panelists focus on the possibility, likelihood or inevitability of 
        combinations of programmable logic, microprocessors and ASICs in a 
        single chip. 

        Will they be as general as possible or application specific? 

        Will all three types of logic be involved or perhaps only two?

        How much of the die area should be allocated to programmable logic? 

        How will the CAD tools cope with the speed mismatch between the 
        programmable logic and fixed logic on the same chip? 

        How will the designs be partitioned into programmable and parts; will 
        it be done by humans or by CAD tools? 
        
        These future predictions may depend on the system design size. Are the 
        answers for 500K gate system designs different from those for 5,000K 
        gate system designs? What will happen when 50,000K gate system designs 
        become commonplace in 5 years?

TUESDAY, FEBRUARY 13, 2001

7:30AM Continental Breakfast and Registration

Session 5. Reconfigurable Computing 
Chair: Steve Trimberger, Xilinx
8:30AM Attacking the Semantic Gap Between Application Programming Languages 
       and Configurable Hardware. Greg Snider, Barry Shackleford and 
       Richard J. Carter, Hewlett-Packard Laboratories.
8:50AM Matching and Searching Analysis for Parallel Hardware Implementation 
       on FPGAs. Pablo Moisset, Pedro Diniz and Joonseok Park, University 
       of Southern California/Information Sciences Institute.
9:10AM Evaluation of the Streams-C C-to-FPGA Compiler: An Applications 
       Perspective. Janette Frigo, Maya Gokhale and Dominique Lavenier, 
       Los Alamos National Laboratory.
9:30AM The Effect of Reconfigurable Units in Superscalar Processors.
       Jorge E. Carrillo E. and Paul Chow, University of Toronto.

9:50AM Coffee Break and Poster Presentations.

Session 6. Pipelined Routing Architectures
Chair: Andre DeHon, Cal Tech
10:50AM Interconnect Pipelining in a Throughput-Intensive FPGA Architecture.
        Amit Singh, Arindam Mukherjee and Malgorzata Marek-Sadowska,
        University of California, Santa Barbara.
11:10AM The Case for Registered Routing Switches in Field Programmable Gate 
        Arrays. Deshanand P. Singh and Stephen D. Brown. University of Toronto.

11:30AM Poster Presentations.

12:00PM Lunch

Session 7. Issues in FPGA-based Systems
Chair: Chuck Stroud, University of North Carolina - Charlotte
1:30PM Configuration Compression for FPGA-based Embedded Systems. 
       Andreas Dandalis and Viktor K. Prasanna, 
       University of Southern California.
1:50PM A Memory Coherence Technique for Online Transient Error Recovery of 
       FPGA Configurations. Wei-Je Huang and Edward J. McCluskey, 
       Stanford University.
2:10PM Run-Time Defect Tolerance using JBits. 
       Prasanna Sundararajan and Steven A. Guccione, Xilinx.

2:30PM Coffee Break and Poster Presentations.

Session 8. Applications in Image/Video Compression 
Chair: Miriam Leeser, Northeastern University
3:30PM A pipelined architecture for partitioned DWT based lossy image 
       compression using FPGA's. Jörg Ritter and Paul Molitor, 
       Martin-Luther-University.
3:50PM An FPGA-Based Video Compressor for H.263 Compatible Bitstreams. 
       G. Lienhart, R. Lay, K.H. Noffz and R. Männer, University of Mannheim.
4:10PM FPGA implementation of a novel, fast motion estimation algorithm for 
       real-time video compression. S. Ramachandran and S. Srinivasan, 
       Indian Institute of Technology, Chennai.

4:30PM Closing Remarks: Scott Hauck, Martine Schlag
 
 
 
General Information About Monterey

About Monterey: The Monterey Peninsula is famous for its many attractions and 
recreational activities, such as John Steinbeck's famous Cannery Row and the 
Monterey Bay Aquarium. Also, play one of the 19 championship golf courses. 
Charter fishing is available right at Fisherman's Wharf. Monterey is renowned 
worldwide for its spectacular coastlines, including Big Sur and the 17-Mile 
drive. Shopping opportunities and restaurants abound, and the hotel can 
organize visits to Carmel-by-the-Sea, Cannery Row, and other area sites. 
Recreational activities available to all hotel guests include swimming pool, 
Jacuzzi, land and sea recreational rental equipment (kayaking, rollerblading, 
bicycling and snorkeling). 

Directions to the Doubletree from Monterey Airport: 
Take Highway 68 to the Monterey Fisherman's Wharf exit. At the first light turn
right onto Aguajito. Continue on Aguajito until it ends at Del Monte. Make a 
left onto Del Monte and continue for three lights. At the third light get in 
the left turn lane to continue straight on Del Monte to the Hotel.

>From San Francisco International and San Jose International Airports: 
Take Highway 101 South to Route 156. Travel on Route 156 West to Highway 1 
South to the Del Monte/Pacific Grove exit. Proceed on Del Monte through 7 
lights to Alvarado. (*At the 5th light--McDonald's on left--stay in the left 
lane in order to continue straight on Del Monte.) At Alvarado, turn right 
into the Doubletree entrance.

>From the South/Carmel on Highway One: 
Take the Aguajito exit. Turn left at the first light. Continue on Aguajito 
until it ends at Del Monte. Make a left and continue straight for three lights,
then get in the left turn lane to continue straight on Del Monte to Doubletree.

Hotel Parking: Self-parking for hotel guests is $10 per day, with in and out 
privileges; $12 per day for valet parking. For those who are not staying at 
the hotel there is cheaper parking a block away from the hotel in a parking 
garage.


HOTEL INFORMATION AND RESERVATION FORM
Doubletree Hotel, Monterey, California: ACM/FPGA 2001, February 11-13, 2001.

Name (first middle last):_______________________Date of arrival:______________

Time of Arrival:______________________Departure Date:_________________

Name(s) of additional person(s) sharing room:________________________________

Credit Card Type:______Expiration Date:______Credit Card Number:_______________

Mailing Address:_____________________________________________________________

_____________________________________________________________________________

Phone: (____) _____________

Hotel Rates: (please check all that apply)

_____Single Occupancy - $139        ________Double Occupancy - $139

_____Non-Smoking         ________Additional Person per night - $20 per night

Rates are subject to 10% occupancy tax per night, per room. Please enclose 
one night's deposit or complete credit card information. The deposit is 
refundable up to 48 hours before the symposium with the cancellation notice.

Check-in time is after 3:00 PM / Check-out time is 12 noon.

Reservations must be received by January 17, 2001. Reservations received 
after this date are based upon availability.

Please return this form directly to:
Attn: Reservations Department
      Doubletree Hotel Monterey 
      2 Portola Plaza
      Monterey, CA 93940.

Or you can make reservations directly with the Hotel at (831) 649-4511, or at Doubletree Reservations office at (800) 222-TREE. Be sure to identify yourself as an ACM FPGA 2001 Conference Attendee.

/http://www.hilton.com/doubletree/hotels/MRYADDT/index.html


REGISTRATION FORM FOR FPGA'01
Ninth ACM International Symposium on Field-Programmable Gate Arrays
February 11-13, 2001          Monterey, California


First Name for Badge:__________________________________________________________

Name (first,middle,last):______________________________________________________

Affiliation (for badge):_______________________________________________________

Title/Job Function:____________________________________________________________

Address:_______________________________________________________________________

City:______________________ State:_____________________ Zip Code:______________

Country:___________________  Email:____________________________________________

Phone: (____)________________________ Fax: (_____)_____________________________

ACM/SIG Member ID:_______________________     Student ID:______________________

Special Needs:_______________________   
Special Meal Requirements:    Vegetarian    Kosher     Vegan

Do not include my name, address and e-mail id in the conference 
attendee listing _____.

PLEASE NOTE  Conference registration fee includes one copy of the conference 
proceedings, breakfast, lunch, Sunday Reception, and Monday Banquet.

REGISTRATION FEES  (Please circle appropriate fees)
The cut off date for preregistration is February 2,2001.  
After this date you must register on-site.

     Registration on or before 1/19/01             
	            Member        Non-Member     Student
FPGA Conference     $325.00       $425.00        $ 85.00

     Registration after 1/19/01
	            Member        Non-Member     Student
FPGA Conference     $400.00       $500.00        $ 95.00

Guest Banquet Tickets:   ____ tickets x $60 = ______

Membership:
SIGDA Membership    $ 15    Student SIGDA Membership         $ 15           

ACM Membership      $ 95    ACM Student Membership           $ 38              

Please check the ACM website for other options including proceedings 
packages and digital library.

Total Fees: US $_______________________ 
(Make checks payable to ACM/FPGA'01 Conference)

Payment included (circle one): 

     American Express         Master Card           Visa         Check

Credit Card Number:_____________________ Expiration Date:__________________

Names as it appears on Credit Card:________________________________________

Signature:_________________________________________________________________

For questions (8:30 am - 4:30 PM EST)
Email: acmhelp@acm.org. 
For Credit Card payments, Fax 1-212-944-1318
Telephone: (US and Canada) 1-212-342-6626, (outside the US) 1-212-626-0500.

If paying by check, mail check with registration form to:
            ACM Member Services
	    P.O. Box 11405
	    New York, NY 10286-1405, USA

Cancellations must be received in writing by contacting the ACM Member 
Services Department. A US $50 cancellation fee will be charged.
You should receive e-mail confirmation within 3 business days.  
If you do not please contact our member services department at the above 
contact information.

Article: 28071
Subject: insert a BUFGP in a SPARTAN with foundation3.1
From: "Benoît" <benoit.hamon@elios-informatique.fr>
Date: Wed, 20 Dec 2000 15:48:54 +0100
Links: << >>  << T >>  << A >>
Hi,

Could you tell me how to insert a BUFGP in a SPARTAN with foundation3.1
service pack 6.
(In VHDL file, and/or in .ucf).

It is NOT the same method that with Foundation 2.1.

Thanks,
Benoit.




Article: 28072
Subject: Re: really fast counter in SpartanXL? THANKS!
From: Theron Hicks <hicksthe@egr.msu.edu>
Date: Wed, 20 Dec 2000 10:04:40 -0500
Links: << >>  << T >>  << A >>
My final solution was to use a process as follows and then use its output to
drive a 15 bit fast logiblox counter.

u4 : process(clock)
begin
if clock'event and clock='0' then
temp_data_out(0) <= not(reset16)and(temp_data_out(0)  xor count_ena);
end if;
end process;

    BTW I am finding that I _really_ like logiblox.  In most cases I like it
better than COREGEN as it is easier to declare a logiblox device.  The selection
of parts is better for my design needs (high speed counters and clock dividers,
for example).
    Thanks to all who have chosen to provide advice to me over the past few
weeks.  I was able to use some of the info (on Coregen) in a class project for a
masters class in hardware/software codesign.  Similarily I was able to make use
of the fast counter stuff in a design that will go into production at a start-up
instrumentation manufacturer.  Thanks Again.

Hal Murray wrote:

> [Context is making a fast counter to measure the width of a pulse.]
>
> > In your case, just stay away from global clocks. Route the input clock
> > signal to the clock input of a single CLB flip-flop ( best placed on the
> > left edge of the device.) Make it toggle, using a tight feedback loop
> > (<2ns)
> > Then use this Q as a clock for the next CLB, configured as a 2-bit counter,
> > since the two flip-flops have a common clock. Use the highest Q as clock
> > for the nect CLB, etc.
> > That gives you a ripple counter with the best possible input resolution (
> > yes, and an awful ripple delay.)
> > 400 MHz should be no problem.
>
> Could you get an extra half bit of resolution by clocking things
> on the other edge of the clock too?
>
> I think that requires that both the clock-enable (pulse being measured)
> and the clock be be routed to 2 CLBs with matching routing delays.
>
> --
> These are my opinions, not necessarily my employers.  I hate spam.


Article: 28073
Subject: Samsung SDRAM behavioural models
From: Paul Bateson <paul.bateson@s3group.com>
Date: Wed, 20 Dec 2000 15:06:14 +0000
Links: << >>  << T >>  << A >>
Hi,

Does anyone have  experience with any Samsung SDRAM behavioural models?
I have been simulating the K4s281632b 128Mbit SDRAM model and I get :

** Warning: tRASmax: Maximum Row Active Violation at.....

The strange thing is that the warning occurs during the power up period where
there are no commands sent to the SDRAM.
The warning would make sense if I had activated a row and left it Active for more
than tRASmax (100us).

The problem is that Samsung only provide ModelSim compiled libraries, so I can
not look at the code to see what is happening.

Q. Has anyone used this model before?
Q. Is this a bug in the model?
Q. Are any other bugs in this model I should watch out for.

Q. Why can't manufactures provide the code for their models........

Thanks for your time,
Paul

--
Paul Bateson
Hardware Systems Division
Silicon & Software Systems
South County Business Park
Leopardstown, Dublin 18, IRELAND
tel: +353-1-207-8913
fax: +353-1-207-8801
mailto:paul.bateson@s3group.com
http://www.s3group.com



Article: 28074
Subject: Re: Reverse-engineering FPGA's
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 20 Dec 2000 07:45:54 -0800
Links: << >>  << T >>  << A >>
Harvey,

I assure you that we did not intentionally add any randomness.

Austin Lesea
IC Design
Xilinx

harveytwyman@my-deja.com wrote:

> We had a postgraduate student project a few years ago that investigated
> the internal interconnections of a Xilinx device. The old Xilinx 2064
> device was chosen as being the simplest.
>
> He mananged to develop a method of discovering the interconnect
> positions purely experimentally.
>
> This was done by changing a single bit in the programming code file and
> then observing the difference in Xilinx's "World View" graphics package
> option.
>
> Phrases like "needles in haystacks" springs to mind.
>
> I think the project demonstrated that the major FPGA companies even
> then, "built in" randomness into their internal configuration schemes
> to make reverse engineering more difficult.
>
> He found that a certain configuration bit in one device would be
> totally different to another device, even within the same family.
>
> Hence the project finished with those conclusions.
>
> ----------------------------
> H A R V E Y      T W Y M A N
>
> Department of Electronics,
> University of Kent.
> Canterbury. U.K.
>
> ABOUT ME: http://www.Twyman.org.uk/CV.htm
> EMAIL ME: H.E.Twyman@ukc.ac.uk
> ----------------------------
>
> In article <3A256F33.6483C1C@libertysurf.fr>,
>   Isabelle <isabelle.todescato@libertysurf.fr> wrote:
> > Hello, I am a newbie in FPGAs and am interested especially in
> > test-vector synthesis.
> >
> > My - naive - questions are :
> >
> > 1.Is it possible from the program file of some FPGA to deduce a gate
> or
> > functional block model for the internals of that FPGA ?
> > 2.Do the FPGA manufacturers pusblish the mapping from program files to
> > FPGA internals ?
> >
> > Thanks a lot for reading this
> >
> > Fabien TODESCATO
> >
> >
>
> Sent via Deja.com
> http://www.deja.com/




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search