Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 6350

Article: 6350
Subject: Re: Cheap way to develop for FPGAs?
From: "Richard Schwarz" <aaps@erols.com>
Date: 17 May 1997 14:33:07 GMT
Links: << >>  << T >>  << A >>
It depends on what you mean by cheap. APS offers a complete XILINX
development kit which will take you from synthesis through routing and
simulation and into an actual test board for as little as $650.00!!!!
That's alot of bang for $650.00. See the details at

http://www.erols.com/aaps

Christos Dimitrakakis <mbge4cd1@afs.mcc.ac.uk> wrote in article
<33785149.62F8@afs.mcc.ac.uk>...
> Is there a cheap way to develop for FPGAs, suitable for the enthusiast?
> 
> -- 
> Christos Dimitrakakis
> ---------------------
> mailto:mbge4cd1@fs4.eng.man.ac.uk
> mailto:mbge4cd1@afs.mcc.ac.uk
> http://www.man.ac.uk/~mbge4cd1
> 
Article: 6351
Subject: Fast comparator
From: Svenn-Ivar <sis@hekta.iet.hist.no>
Date: Sat, 17 May 1997 18:09:28 +0200
Links: << >>  << T >>  << A >>
I've been thinking of using an FPGA as a trigger circuit in a (not so
high-end) digital scope. Functions I need are high speed comparison of
two 10-bit digital values against each other and against predetermined
values. Output would be an indication if to trig or not.
I'm not familiar to FPGA's or other 'programmable logic' so I would like
to know if this is possible to do, before I go any further. With high
speed I mean about 10ns from value input to indication output.
Suggestions are highly appreciated!

----------------------------------------
Svenn-Ivar Svendsen, Student
Dept. of Electrical Engeneering
sis@hekta.iet.hist.no
http://hekta.iet.hist.no/~sis
Article: 6352
Subject: Re: universal PCI-Interface with FPGA?
From: app01@aol.com (APP01)
Date: 17 May 1997 17:01:08 GMT
Links: << >>  << T >>  << A >>
Ralf,

In response to PCI  interface within an FPGA, you must be careful. I have
looked as Altera, Xilinx, and Lucent (Orca), and specs can be misleading.
After doin some digging, I found the ORCA to be the only one that was
Fully Compliant. 

They have a pretty good PCI kit and their architecture is very conducent
to PCI implementations.

I have alot of experience with Xilinx, and ORCA and have found ORCA and
the tools in general to be better and easier to use.


Tony
Article: 6353
Subject: Re: FPGA gate counting: No truth in advertising
From: app01@aol.com (APP01)
Date: 17 May 1997 17:10:12 GMT
Links: << >>  << T >>  << A >>
Ok.. yes everyone counts gates differently at least until a year or so
ago.

Altera wrote a white paper (it is on their site) on how they count gates. 
Well sinc then Xilinx(at times)  and Lucent have been using the same
counting techniques.

The counting assumes the following: 70% logic, 30% ram, then they add 4
gates per ram bit and count it all up to get the total gate count. The
latest data books from vendors have been showing this. For Example:
Lucents Orca book shows a range of gates for a given device assuming no
ram, to 30% ram. Thsie 2C40A device which is tauted to have 40k gates, now
has an advertised range of 38k to 98k gates.

The second killer in FPGA's is the  routing resources. Even if an FPGA has
tons of gates, if you can't get to them its useless, so when looking at
gates, or even counting up flops, you MUST also consider the routing
resources. Many of us remember the key number of 65% utilization is an
certian FPGA!!!

Now as far as ASIC versus FPGA gates,  I have a general rule of thumb 
that an FPGA will require about 2.5 x Asic gates. This is very dependent
upon tge FPGA architecture and the design. Some FPGA;s have narrow LUT
functions, which can increase the required gates..

Tony

Article: 6354
Subject: Re: VHDL PCI FPGA Implementation
From: app01@aol.com (APP01)
Date: 17 May 1997 17:12:16 GMT
Links: << >>  << T >>  << A >>
I have used Lucent;s ORCA in a PCI application with very few problems.
Both the Bus Initiator/Target and stand alone Target kits were pretty easy
to get working.
And this kit is the ONLY one that is "really" PCI compliant.

Caution.. Read the specs carefully and compare teh data books.

Article: 6355
Subject: Re: Fast comparator
From: Peter Alfke <peter@xilinx.com>
Date: Sat, 17 May 1997 11:02:16 -0700
Links: << >>  << T >>  << A >>
Svenn-Ivar wrote:
> 
 I need are high speed comparison of
> two 10-bit digital values against each other and against predetermined
> values.
 I mean about 10ns from value input to indication output.

Look-up-table based FPGA are ideally suited to perform this function
very efficiently, but 10 ns is hardly possible without pipelining.  But
I think your application allows pipelining without any penalty. With
pipelining this is very easy ( "piece-of-cake). I would suggest the
fastest flavor of the XC4000E. The smallest part ( XC4003E ) is more
than big enough for your function.
Hope to see you at our seminar in Oslo, June 6.

Peter Alfke, Xilinx Applications
Article: 6356
Subject: Re: VHDL or Verilog?
From: "Dr. Vitit Kantabutra" <vkantabu@howland.isu.edu>
Date: Sat, 17 May 1997 21:16:33 -0700
Links: << >>  << T >>  << A >>
Karl E. Vinacco wrote:
> 
> Hi,
>         The company that I work for is in the process of deciding on a new
> simulation tool.  Right now we use a schematic entry/ABEL-HDL tool, but
> we want to upgrade to a VHDL or Verilog.  I have been left with the task
> of deciding which is better.  I could use some input on the pros and
> cons of each, maybe listing some of the major benefits or drawbacks.
> Also what seems to be the most widely used.  Any help I can get would be
> greatly appreciated.  Please reply to me as well as the newsgroup, and
> no spam please.  Thanks

I use Model Technology's Vsystem Plus, (http://www.model.com) which
supports both VHDL and Verilog, and even allows mixing the two.  As I
have no experience with a different package and am pretty new at this
game anyway, I can't give you a comparative review of this software
package versus others.  But at least I thought that getting this package
would eliminate having to decide between the two languages.  As a
computer scientist, I personally think that these languages are both
pretty clunky, but I guess there isn't a better alternative that's
widely accepted right now.

The company claims they sold more copies of similar software than anyone
else.  So maybe that means that the software is OK?  At least, it gives
you a lot of different windows for looking at different things.

Vitit Kantabutra
Idaho State University
vkantabu@howland.isu.edu
Article: 6357
Subject: Re: xilinx xblox with capture ver 7.00
From: "William E. Lenihan III" <lenihan3we@earthlink.net>
Date: Sat, 17 May 1997 23:37:34 -0700
Links: << >>  << T >>  << A >>
zibby sobota wrote:
> 
> Does anyone know if I can  use xilinx xblox with  orcad capture ver 7.00 ?
> It seems that only Orcad Express can do the job but I am not sure .
> Has anyone had any experience with  that ?
> 
> please help
> 
> Zbigniew Sobota
> Igt Australia

XBLOX is being dumped by Xilinx, so avoid it until you know what, if
anything, will replace it. Better yet, look into synthesis for those
design components that you were thinking of using XBLOX for.

-- 
=====================================================================
 William Lenihan                            lenihan3we@earthlink.net

    "The greatest barrier to communication is the delusion that
     it has already occurred."       -- Peter Cummings
=====================================================================
Article: 6358
Subject: Re: xilinx xblox with capture ver 7.00
From: pss1@hopper.unh.edu (Paul S Secinaro)
Date: 18 May 1997 13:13:25 GMT
Links: << >>  << T >>  << A >>
"William E. Lenihan III" <lenihan3we@earthlink.net> writes:

>XBLOX is being dumped by Xilinx, so avoid it until you know what, if
>anything, will replace it. Better yet, look into synthesis for those
>design components that you were thinking of using XBLOX for.

I would hope that they're moving towards implementing a standard LPM
library.  Anyone know for sure?


-- 
Paul Secinaro (pss1@christa.unh.edu)
Synthetic Vision and Pattern Analysis Laboratory
UNH Dept. of Electrical and Computer Engineering
Article: 6359
Subject: FPGA Lab Kits available NOW
From: "Richard Schwarz" <aaps@erols.com>
Date: 18 May 1997 14:18:46 GMT
Links: << >>  << T >>  << A >>
The APS-X84-FB Lab Kit is available NOW with:

1) Schematic Capture Synthesis
2) Simulator
3) Router Software
4) Serial Xchecker cables
5) Parallel Xchecker Cable
6) 84 pin PLCC X84 board with ISA BUS connector on board 8255 etc.
7) XABEL PLD software 
8) One years XILINX Foundation maint. and upgrades (this would include M1)
9) Examples and Lab Book including not only FPGA/PLD design, but C control
code for using the design in a real world control environment (PC).

Purchasing this kit will give you all you need to start designing for
the soon to be released XILINX Lab Kits (which do not include any hardware
or software upgrades). Get a jump on designing and using these kits NOW
with the APS-X84-FS kits. Special rates are available for accademic users!

XIlinx is really working hard (and smart) to provide low cost solutions to
get starting 
engineers into FPGA kits. APS is pleased to offer our low cost solutions to
engineers, instructors, and students which enable real cost effective tools
for the industry leading XILINX FPGAs and PLDs at reasonable rates. 

Check out the APS family of kits for both low cost development and for more
serious VHDL and full FPGA chip capable solutions at:

http://www.erols.com/aaps



Article: 6360
Subject: Re: Need Address/Phone/Fax List of Semiconductor Companies
From: jlundgre@delta1.deltanet.com (John Lundgren)
Date: 18 May 1997 15:43:36 GMT
Links: << >>  << T >>  << A >>
Bharat Kurani (Bharat.Kurani@add.ssw.abbott.com) wrote:
: I need address/phone/fax list of all semiconductor companines

Then you should be looking in the Thomas Register.  Check your local
library.


: Thank you

: bharat@antrix.com
: Bharat.Kurani@add.ssw.abbott.com

--
 
#===================================================================#
|    John Lundgren - Elec Tech - Info Tech Svcs. |  spamfree@mail.  |
|    Rancho Santiago Community College District  |  rancho.cc.ca.us |
|     17th St at Bristol \ Santa Ana, CA 92706   | http://www.rancho|
| My opinions are my own, and not my employer's. |    .cc.ca.us     |
!  You MAY NOT use my email address for unsolicited Email or lists! !
#======P=G=P==k=e=y==a=v=a=i=l=a=b=l=e==u=p=o=n==r=e=q=u=e=s=t======#
Article: 6361
Subject: Re: Gatefield FPGA Design Experiences
From: "Richard Schwarz" <aaps@erols.com>
Date: 18 May 1997 16:54:48 GMT
Links: << >>  << T >>  << A >>
We have not had any direct experience with them yet, but they have been in
to see us 
many times. The fine grained arch. which they use is appealing, but we
don't really 
know if that will translate well into better designs. They have large
relatively cheap 
chips which can be reprogrammed, but not in circuit without using one their

programmers (which comes with the development kit). I understand they are
working 
on getting BP and DATA IO on board as programmers, and that they are
working 
on a true 5volt in circuit programmable chip. 

We also do not own a suitable synthesis tool which they support. They only 
supported Synopsis, and now work with Leanardo form Exemplar. We have
Gallileo 
from Exemplar and would need to upgrade. 

Over all they have a unique solution for ASIC development in FPGAs, with
their 
FLASH based chips, and sound like they are moving in the right directiion.
They also 
expressed a willingness to implement big HDL designs for users for free on
a case by 
case basis. This is probably the route we will take. 

Richard 

-- 
______________________________________________ 
Richard D. Schwarz, President 
Associated Professional Systems (APS) 
FPGA Solutions/Test Boards/ EDA Software 
SIGTEK Spread Spectrum & Comm. Equipment 
3003 Latrobe Court, Abingdon, Maryland 21009 
Phone: 410-569-5897   Fax: 410-661-2760 
Email: aaps@erols.com 
Web site: http://www.erols.com/aaps 

Terry Spoon <tspoon@pacbell.net> wrote in article
<3377EA15.61BF@pacbell.net>...
> Does anyone have design experience using Gatefield ProASIC family
> design tools? VHDL->Synopsys->Gatefield->Quickhdl ?
> 
Article: 6362
Subject: Re: File Format for Xilinx bitstream
From: "Steven K. Knapp" <optmagic@ix.netcom.com>
Date: 18 May 1997 21:20:31 GMT
Links: << >>  << T >>  << A >>
There may be an easier way than understanding the .bit file format.  For
example, you can create something called a "raw bits" format using the
command line "makebits -r <filename>".  This creates a 1's and 0's file
formatted like it appears in the device.  You can fairly easily see the
pre-amble, length count, dummy bits, and frames.

There is also a fairly useful utility on the Xilinx web site called
'makesrc' (make source).  The makesrc program coverts an MCS file into a
file with the format the way you want it.  Its somewhere in their support
section.  I would provide the URL, but for some reason, my ISP provider is
having problems reaching the Xilinx site at the moment.
-- 
Steven Knapp
OptiMagic(tm) Logic Design Solutions
E-mail:  optmagic@ix.netcom.com
Programmable Logic Jump Station:  http://www.netcom.com/~optmagic

Archer Lawrence <archer@tanisys.com> wrote in article
<337C7534.BBA805F@tanisys.com>...
| I am looking for the file format for  the '.bit' file produced from the
| Xilinx makebit program.  The documentation describes the configuration
| stream format, but not this file.  Thanks in advance
| 
| Archer Lawrence
| Sr. Engineer
| Tanisys Technologies
| 
| 
Article: 6363
Subject: Re: VHDL PCI FPGA Implementation
From: "Steven K. Knapp" <optmagic@ix.netcom.com>
Date: 18 May 1997 21:58:15 GMT
Links: << >>  << T >>  << A >>
| And this kit is the ONLY one that is "really" PCI compliant.
| 
| Caution.. Read the specs carefully and compare teh data books.

I hate to disagree, but I believe that the Xilinx LogiCORE interface for
their XC4013E device is also fully PCI compliant, both electrically, and to
the PCI protocol.  I know that they had some problems with their 1.0
release, but the 1.1 release has resolved the problems (I used to work for
Xilinx back then and helped create the 1.1 release VIEWsim testbench). 
Xilinx did two independent verifications.  One with a
commercially-available PCI bus model written in VHDL
(http://www.vchips.com/products/pcitest.htm) and another with an
independently-produced VIEWsim testbench.  The results from both systems
were cross-checked to avoid errors.  Various customers also did their own
testing with Synopsys PCI testbench
(http://www.synopsys.com/products/bus/pcibus_ds.html) and had similar
results.

You can judge the compliance for yourself by downloading the PCI Protocol
Compliance Checklist at
'http://www.xilinx.com/products/logicore/lounge/pcim/docs/pcicompl.pdf'. 
The interface is also shipping in production systems today.

-- 
Steven Knapp
OptiMagic(tm) Logic Design Solutions
E-mail:  optmagic@ix.netcom.com
Programmable Logic Jump Station:  http://www.netcom.com/~optmagic
Article: 6364
Subject: Aust: Electronics at Work Exhibition
From: P Nibbs <pnibbs@icd.com.au>
Date: Mon, 19 May 1997 10:46:08 +1000
Links: << >>  << T >>  << A >>
Electronics At Work, Exhibition, Conference & Workshops
Melbourne Convention Centre
Monday, 16th to Thursday, 19th of June 1997

Conference:
Telecommunications: Forecasting the Future

Workshops:
1. EMC Workshop/Update
2. Soldering Workshop
3. Software Workshop

Exhibition:
"Australia's only Exhibition dedicated to the Electronics Industry"
Australia's leading electronics suppliers and manufacturers will be
displaying their products. Free Admission.

For further details and to register: http://www.aedc.com.au


Article: 6365
Subject: Re: Anyone using Actel software?
From: "Rich K." <stellare@erols.com>
Date: Sun, 18 May 1997 22:53:08 -0400
Links: << >>  << T >>  << A >>
Richard Dungan wrote:
> 
> Hello everyone,
> 
> I'm thinking about buying the Actel "Designer Series" FPGA design
> package. Can anyone provide any comments or details of practical
> experience with this? I have prior experience with CUPL up to
> moderately complex devices (Atmel ATV2500) but I'll be a newbie to
> very large FPGAa and also to VHDL.
> The intended first application is _very_ register-rich, hence the
> choice of Actel.
> 
> Thanks in advance,
> 
> Richard
> 
> ------------Richard Dungan-------------
> Radix Electronic Designs, Orpington, UK
>   Email> Richard.Radix@BTinternet.com
> ---------------------------------------

Hi,

I've been using Viewlogic/Actel for about 4 1/2 years so have some
experience with this combination.  Note that there are many good chips
out there and many good s/w packages for many of the vendors each with
their own strengths and weaknesses; because of some rather specific
requirements, most of the work that i do is in Actel.  As for register
rich, if you select Actel, you might want to look at the newer stuff
they put out like the 32300dx; this one has their maximum # of storage
elements: 

	~2,000 dedicated flip-flops;
	~2,000 more combinational modules which can be used for storage;
		(1 c-module for a latch, 2 c-modules for a edge-triggerred flip-flop);
	250 i/o modules with an input and output latch in each module; they can
be used either
		individually or combined (via a h/w macro) with a single c-module into
a flip-flop).
	~3,000 bits of SRAM which can be organized in a variety of ways (e.g.
FIFO, dual-port RAM, etc.)

the densest device that i have hands on experience with is their
a32200dx which is one size smaller.

as for the software, here are some comments:

	the older version had a lot of trouble keeping the pins fixed; you had
to remember how to
		run the s/w in non-obvious ways - this was a real pain and is finally
fixed.
	some older versions of s/w wouldn't lock out the probe pins and forced
manual assigning.
		this is typical of the types of bugs seen most often.
	actel removed their 'chip edit' program which allowed you to observe
and change module
		placement with a gui interface; it's back in the latest version with
some of the
		features removed (and which should be back in in future versions).
	most tightly coupled to the viewlogic s/w - a lot of people swear at
it, i've heard few swear
		by it.  personally, i think it's ok, has some real nice features,
licensing is a pain
		in the butt.  you can get the whole system bundled together.
	they use a database system in the newer versions which is a pain to
install and get running
		correctly and sometimes crashes; i believe this database is history in
the soon to
		come out upgrade version.
	they give you a free vhdl compiler; this seems 'ok' at best.  my vhdl
is a bit limited and 
		i am using it more in my design flow; the actel stuff is supported by
other synthesis
		tools - you may want to look at them and have heard some good things
about third
		party synthesizers.
	it takes a pretty good sized 'puter to run their s/w - i would
recommend a 166 mhz pentium
		with 32 meg of ram.  can't talk much about the unix requirements (both
actel and
		viewlogic are on unix).


	the place and route s/w is FANTASTIC.  s/w always routes even for dense
designs; for 'production'
		designs i've used it up to > 90%; for evaluation circuits i use it
close to 100%.  for
		many 'production' circuits i am often hit with changes in requirements
which entail
		significant logic redesigns; i have never had a problem keeping the
pinouts fixed and
		feel quite confident that it will complete successfully with no
significant changes
		in timing.  i consider this to be a critical asset for fpga's since
requests often come
		in too late for redoing boards and being able to reprogram without
modifying the boards
		is extremely valuable.  they also have incremental place and route
which is handy for 
		small changes.  additionally, there is an option for timing driven
layout which will 
		run based on user input requirements.
	another good package they have is a macro generator.  this has a wide
variety of macros for
		standard building blocks with a number of configurations to optimize
for speed or
		area or functionality or structure.  the designs are very tight and it
will be difficult 
		for a human to beat it; in any event, it would take a lot of design
time to beat their
		generator for at best a very small improvement.  this package has been
a very large
		contributor to getting designs done faster and more accurately than
manual
		schematic entry and allows me to concentrate on architecture and
algorithms. a nice
		bonus is (at least w/ viewlogic) automagic symbol generation so blocks
can be generated
		and then placed down on a top-level, road-map schematic very quickly.  
	static timing analyzer: this tool is a big labor saver in timing
analysis and eliminates the
		need to generate worst-case stimulus vectors for back-annotated timing
analysis.  also,
		it can automagically compute the setup and hold times for external
signals.  you can
		dial in whatever conditions you want (i.e., temp, process, voltage,
rad levels, etc.).
	action probe: this s/w allows you to bring off chip any two internal
signals in a running 
		system.  you can either probe the signals using a scope, counter,
logic analyzer, etc.,
		or display values or vectors directly on the screen.  this observation
doesn't require
		any reprogramming and operates w/out interfering with the running
logic (assuming that
		you didn't assign any signals to the probe pins - s/w will lock them
out for you).
	debugger: this tool allows you to either manually or from a file
stimulate a chip on the
		programming head and make observations from either at the chip's
outputs or any
		internal node in either a bit basis or a vector's.	


just a few thoughts,

hope it helps,

rk

Article: 6366
Subject: Qualis Public Verilog training course schedule: Fall '97
From: lindab@qualis.qualis.com (Linda Boyd)
Date: 19 May 1997 03:56:46 GMT
Links: << >>  << T >>  << A >>

Qualis Design Corporation has released the Fall schedule for our many
hands-on, application-focused courses in Verilog- and VHDL-based design.
Our courses are like no other -- just take a look at our lineup:

   Verilog System Design
   ---------------------
        Introductory:
            High Level Design Using Verilog (5 days)
            System Verification Using Verilog (5 days) 
            Verilog for Board-Level Design (5 days)
        Elite:
            ASIC Synthesis and Verification Strategies Using Verilog (5 days) 
            Advanced Techniques Using Verilog (3 days)

   Verilog Synthesis
   -----------------
        Introductory:
            Verilog for Synthesis: A Solid Foundation (5 days) 
        Elite:
            ASIC Synthesis Strategies Using Verilog (3 days) 
            Behavioral Synthesis Strategies Using Verilog (3 days) 


For more info on our suite of HDL classes, to review our Fall schedule,
or if you're interested in an on-site class, check out our web site
at http://www.qualis.com, or send us e-mail at mailto:hot@qualis.com .
You can also call for more info at +1.503.644.9700 .

Qualis Design Corporation
8705 SW Nimbus Suite 118
Beaverton OR 97008 USA
Ph: +1.503.644.9700  Fax: +1.503.643.1583

Copyright (c) 1997 Qualis Design Corporation

Article: 6367
Subject: Qualis Public VHDL training course schedule: Fall '97
From: lindab@qualis.qualis.com (Linda Boyd)
Date: 19 May 1997 04:03:09 GMT
Links: << >>  << T >>  << A >>


Qualis Design Corporation has released the Fall schedule for our many
hands-on, application-focused courses in VHDL- and Verilog-based design.
Our courses are like no other -- just take a look at our lineup:

   VHDL System Design
   ------------------
        Introductory:
            High Level Design Using VHDL (5 days) 
            System Verification Using VHDL (5 days) 
            VHDL for Board-Level Design (5 days) 
        Elite:
            ASIC Synthesis and Verification Strategies Using VHDL (5 days) 
            Advanced Techniques Using VHDL (3 days) 

   VHDL Synthesis
   --------------
        Introductory:
            VHDL for Synthesis: A Solid Foundation (5 days) 
        Elite:
            ASIC Synthesis Strategies Using VHDL (3 days) 
            Behavioral Synthesis Strategies Using VHDL (3 days) 

For more info on our suite of HDL classes, to review our Fall schedule,
or if you're interested in an on-site class, check out our web
site at http://www.qualis.com, or send us e-mail at hot@qualis.com.
You can also call for more info at +1.503.644.9700

Qualis Design Corporation
8705 SW Nimbus Suite 118
Beaverton OR 97008 USA
Ph: +1.503.644.9700  Fax: +1.503.643.1583

Copyright (c) 1997 Qualis Design Corporation

Article: 6368
Subject: Re: suggestion about a pcmcia in a fpga
From: Markku Vähätaini <markku@fincitec.fi>
Date: Mon, 19 May 1997 15:18:56 +0300
Links: << >>  << T >>  << A >>
I think, that you have a problem with 10K programming memories. EPC-1
PROM is available only in DIP or PLCC -packages (too thick to fit Type
II
frame). I've used FLEX8282(TQFP100) and EPC1064 (TQFP32) programming
memory.
This concept has been working fine.

-------------------------------------------------------------
Markku Vahataini                    email: markku@fincitec.fi
Fincitec Oy			       
PO.BOX 11          		       PH: +358 16 221490 
FIN-94601 KEMI                        FAX: +358 16 221561 
FINLAND                              http://www.fincitec.com


Ivan Rossi wrote:
> 
> I want to insert a PCMCIA in an Altera FLEX10K. Anybody has had a positive
> experience about that and could show me any valid partners that could
> supply me the core in vhdl description? Thank you.
>                         Ivan Rossi, Mantova Italy
>                         rossivan@tecna.it
Article: 6369
Subject: Re: Cheap way to develop for FPGAs?
From: CoxJA@augustsl.demon.co.uk (Julian Cox)
Date: Mon, 19 May 1997 12:44:23 GMT
Links: << >>  << T >>  << A >>
Christos Dimitrakakis <mbge4cd1@afs.mcc.ac.uk> wrote:

>Is there a cheap way to develop for FPGAs, suitable for the enthusiast?
>
>-- 

Christos

Cheapest I know of is Warp 2 from Cypress.  You should be able to pick
up a copy for £69 over here.  See
http://www.cypress.com/cypress/warp2/page2.htm for details.  

Good luck

Julian
-- 
---------------------------------------------------------------------
Julian Cox
CoxJA@augustsl.demon.co.uk              error: smartass.sig not found
Hardware development eng.                          August Systems Ltd
---------------------------------------------------------------------
                                          

Article: 6370
Subject: Re: Fast comparator
From: Ray Andraka <randraka@ids.net>
Date: Mon, 19 May 1997 08:47:04 -0400
Links: << >>  << T >>  << A >>
Svenn-Ivar wrote:
> 
> I've been thinking of using an FPGA as a trigger circuit in a (not so
> high-end) digital scope. Functions I need are high speed comparison of
> two 10-bit digital values against each other and against predetermined
> values. Output would be an indication if to trig or not.
> I'm not familiar to FPGA's or other 'programmable logic' so I would like
> to know if this is possible to do, before I go any further. With high
> speed I mean about 10ns from value input to indication output.
> Suggestions are highly appreciated!
> 

For this relatively simple fixed function with the desired 10ns
propagation delay, you'd be better off using a fast CPLD rather than an
FPGA. 

-Ray Andraka, P.E.
Chairman, the Andraka Consulting Group
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://www.ids.net/~randraka
Article: 6371
Subject: Re: File Format for Xilinx bitstream
From: "Steven K. Knapp" <optmagic@ix.netcom.com>
Date: 19 May 1997 13:46:49 GMT
Links: << >>  << T >>  << A >>
Okay, the site is back up.  Here are the links to MAKESRC.

Go to 'http://www.xilinx.com/support/techsup/ftp/htm_index/utils_prom.htm'
and download either MAKESRC.ZIP for the PC or MAKESRC.TAR.Z for UNIX-based
machines.
-- 
Steven Knapp
OptiMagic(tm) Logic Design Solutions
E-mail:  optmagic@ix.netcom.com
Programmable Logic Jump Station:  http://www.netcom.com/~optmagic

Steven K. Knapp <optmagic@ix.netcom.com> wrote in article
<01bc63d0$d7b2d4e0$a181b6c7@default>...
| There may be an easier way than understanding the .bit file format.  For
| example, you can create something called a "raw bits" format using the
| command line "makebits -r <filename>".  This creates a 1's and 0's file
| formatted like it appears in the device.  You can fairly easily see the
| pre-amble, length count, dummy bits, and frames.
| 
| There is also a fairly useful utility on the Xilinx web site called
| 'makesrc' (make source).  The makesrc program coverts an MCS file into a
| file with the format the way you want it.  Its somewhere in their support
| section.  I would provide the URL, but for some reason, my ISP provider
is
| having problems reaching the Xilinx site at the moment.
| -- 
| Steven Knapp
| OptiMagic(tm) Logic Design Solutions
| E-mail:  optmagic@ix.netcom.com
| Programmable Logic Jump Station:  http://www.netcom.com/~optmagic
| 
| Archer Lawrence <archer@tanisys.com> wrote in article
| <337C7534.BBA805F@tanisys.com>...
| | I am looking for the file format for  the '.bit' file produced from the
| | Xilinx makebit program.  The documentation describes the configuration
| | stream format, but not this file.  Thanks in advance
| | 
| | Archer Lawrence
| | Sr. Engineer
| | Tanisys Technologies
| | 
| | 
| 
Article: 6372
Subject: Re: Fast comparator
From: husby@fnal.gov
Date: Mon, 19 May 1997 08:34:11 -0600
Links: << >>  << T >>  << A >>
Svenn-Ivar <sis@hekta.iet.hist.no> wrote:
> I've been thinking of using an FPGA as a trigger circuit in a (not so
> high-end) digital scope. Functions I need are high speed comparison of
> two 10-bit digital values against each other and against predetermined
> values. Output would be an indication if to trig or not.

The Lucent ORCA chip (2Cxxa-4) can implement a 12-bit equaility
comparator in 6.5 ns using the built-in carry chain (3.3 in-cout + 1.1
cin-cout + 2.1 cin-O4).  This leaves you 3.5ns for routing data into and
out of the circuit.  It may be	possible to meet 10ns, but I wouldn't bet
the company on it.

As an alternative, you can implement a 10 or 11-bit comparator in a single
PFU by re-programming the lookup table for each trigger.  This would give
a trigger time of less than 3ns  (PFU setup time to Clock) even using the
slower -3 speed parts.

-------------------==== Posted via Deja News ====-----------------------
      http://www.dejanews.com/     Search, Read, Post to Usenet
Article: 6373
Subject: Re: Cheap way to develop for FPGAs?
From: Steve Casselman <sc@vcc.com>
Date: Mon, 19 May 1997 16:23:41 GMT
Links: << >>  << T >>  << A >>
If you want to develop for a reconfigurable
SYSTEM you might want to look at
http://www.vcc.com/products/pci6200.html
for $995 you get all the software to program
the XC6216 (16,000 gates) 2Meg of fast
SRAM and lots of other features and software.
All this on a PCI card for a "state-of-the-art"
learning experiance.

Steve Casselman, President
Virtual Computer Corporation
Article: 6374
Subject: Re: X-BLOX
From: Kate Meilicke <kate.meilicke@xilinx.com>
Date: Mon, 19 May 1997 12:51:40 -0400
Links: << >>  << T >>  << A >>
Xilinx isn't dropping the concept of XBLOX.  XBLOX is being replaced by
a better tool called LogiBLOX in the M1 software.  It works the same way
as XBLOX except you have to define the bus width.  One of the major
advantages is faster runtime with LogiBLOX.  The other VHDL and Verilog
simulation files if you instantiated LogiBLOX components in your HDL.

Kate
Xilinx FAE


Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search