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Messages from 6250

Article: 6250
Subject: Re: Schmitt trigger inputs?
From: Tom Burgess <tburgess@drao.nrc.ca>
Date: Fri, 02 May 1997 17:26:22 -0700
Links: << >>  << T >>  << A >>
Rodney Myrvaagnes wrote:
> 
> Are there any FPGAs or CPLDs with Schmitt-trigger inputs that could be driven by a slowly varying voltage (i.e. 10s of Hz)?
> 

Xilinx parts have 100 - 200 mV hysteresis on their inputs. For
an app. note describing use of positive feedback for user controlled
hysteresis (applicable to most PLDs) check out:

http://www.xilinx.com/xcell/xl19/xl19-34.pdf

(You will need an Acrobat .PDF viewer)

	regards, tom
Article: 6251
Subject: Re: Schmitt trigger inputs?
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 02 May 1997 18:20:16 -0700
Links: << >>  << T >>  << A >>
It's easiest to "roll your own":
Go into and then out of the programmable device without a signal
inversion.
Connect a high-value resistor R from the chip output to the chip input.
Drive that chip input through a low value resistor r.
If the output is complementary ( CMOS ), then the hysteresis is 
supply voltage times ratio of r over R.
Example: R=10 kilohm, r = 1 kilohm, hysteresis 500 mV.
This, of course, assumes a drive impedance considerably lower than r.

The only bad side is that it occupies two pins, and the trip points are
dictated by the device input threshold.
There was a more elaborate design, published in the 1986 (!) Xilinx data
book, but I consider it unnecessarily complicated.

Peter Alfke, Xilinx Applications
Article: 6252
(removed)


Article: 6253
Subject: Test
From: "Richard Schwarz" <aaps@erols.com>
Date: 4 May 1997 13:34:51 GMT
Links: << >>  << T >>  << A >>

Test
Article: 6254
Subject: ANNOUNCE: XILINX FPGA Kits prices
From: "Richard Schwarz" <aaps@erols.com>
Date: 4 May 1997 13:52:01 GMT
Links: << >>  << T >>  << A >>

ANNOUNCEMENT:

The prices for the APS-X84 FPGA kits were scheduled to be increased, but
APS is
pleased to announce that we are able to extend these prices for the next
60 days. This means you get a complete XILINX FPGA development system  (non
VHDL) kit for as low as $650.00. A VHDL kit can be purchased for as low as
$1200.00. These are serious tools offered at very low prices.

The APS-X84 FPGA kits for XILINX FPGAs include the XILINX
Foundation series package and contains Schematic Capture (which can
take in Viewlogic macros), XACT router tools, XCHECKER cables, XABEL
compiler and post route simulator. The VHDL packages come with VHDL 
editor, VHDL WIZARD, and VHDL multimedia  tutorial. All kits also
includes the multipurpose APS-X84 PC ISA board which comes with an 84
pin PLCC FPGA chip installed and VHDL and C examples. All kits come with
one year XILINX maintenance on the XILINX tools.

 For more information see the following URLs:

http://www.erols.com/aaps

http://www.erols.com/aaps/prices.html

Article: 6255
Subject: Re: Implementing three state output MUXes with Synopsys
From: Ross Swanson <swanson@est07.md.essd.northgrum.com>
Date: Mon, 5 May 1997 12:22:26 GMT
Links: << >>  << T >>  << A >>
Arrigo Benedetti wrote:
> 
> I have some problems implementing a design with a MUX having a three
> state output with Synopsys FPGA Compiler 3.5a targeted to a Xilinx
> 4010E part. The MUX is implemented by the following fragment of VHDL
> code:
> 
>   ybus0 <= ("000000" & yy) when (s(0) = '1') else "ZZZZZZZZZZZZZZZZ";
>   ybus0 <= ("000000" & ff) when (s(1) = '1') else "ZZZZZZZZZZZZZZZZ";
>   ybus0 <= ("0000000000000000") when (s(2) = '1') else "ZZZZZZZZZZZZZZZZ";
>   ybus0 <= ("00000000000000" & cmd) when (s(3) = '1') else "ZZZZZZZZZZZZZZZZ";
> 

The tool is probably trying to build multiple tri state drivers,
one followed by another. I would rearrange the code so that it
matches the H/W structure you have in mind, maybe use a intermediate
signal 'ybus0p' which feeds the tristate driver.

=--                                        --=
       Ross Swanson                           
       swanson@est07.md.essd.northgrum.com
       swan000@erols.com      
=--                                        --=
Article: 6256
Subject: Re: Schmitt trigger inputs?
From: RODNEYM@rodneym.ibm.net (Rodney Myrvaagnes)
Date: 5 May 97 14:03:26 GMT
Links: << >>  << T >>  << A >>
On Fri, 02 May 1997 18:20:16 -0700, Peter Alfke <peter@xilinx.com> wrote:
>
>It's easiest to "roll your own":
snip
>The only bad side is that it occupies two pins, and the trip points are
>dictated by the device input threshold.

Thanks, I knew I could do it that way, but I was hoping to save the pins.
 
Rodney Myrvaagnes    Associate Editor, Electronic Products
rodneym@ibm.net        516-227-1434        Fax 516-227-1444
When possible, sailing J36 Gjo/a

Article: 6257
Subject: Re: Implementing three state output MUXes with Synopsys
From: Thomas Johansson <thomasj@isy.liu.se>
Date: Mon, 05 May 1997 18:38:49 +0200
Links: << >>  << T >>  << A >>

Ross Swanson wrote:
> 
> Arrigo Benedetti wrote:
> >
> > I have some problems implementing a design with a MUX having a three
> > state output with Synopsys FPGA Compiler 3.5a targeted to a Xilinx
> > 4010E part. The MUX is implemented by the following fragment of VHDL
> > code:
> >
> >   ybus0 <= ("000000" & yy) when (s(0) = '1') else "ZZZZZZZZZZZZZZZZ";
> >   ybus0 <= ("000000" & ff) when (s(1) = '1') else "ZZZZZZZZZZZZZZZZ";
> >   ybus0 <= ("0000000000000000") when (s(2) = '1') else "ZZZZZZZZZZZZZZZZ";
> >   ybus0 <= ("00000000000000" & cmd) when (s(3) = '1') else "ZZZZZZZZZZZZZZZZ";
> >
> 
> The tool is probably trying to build multiple tri state drivers,
> one followed by another. I would rearrange the code so that it
> matches the H/W structure you have in mind, maybe use a intermediate
> signal 'ybus0p' which feeds the tristate driver.
> 
> =--                                        --=
>        Ross Swanson
>        swanson@est07.md.essd.northgrum.com
>        swan000@erols.com
> =--                                        --=
Try to rewrite it like this:

  ybus0 <= ("000000" & yy)          when (s(0) = '1') else 
           ("000000" & ff)          when (s(1) = '1') else 
           ("0000000000000000")     when (s(2) = '1') else
           ("00000000000000" & cmd) when (s(3) = '1') else 
           "ZZZZZZZZZZZZZZZZ";

-- 
-------------------------------------------------
Thomas Johansson, assistant Electronics Systems, LiTH

e-mail: thomasj@isy.liu.se
Article: 6258
Subject: Hollywood Blonde
From: Steve Casselman <sc@vcc.com>
Date: Mon, 5 May 1997 23:40:00 GMT
Links: << >>  << T >>  << A >>
For those of you who got a chance to taste
Hollywood Blonde and liked it and would like
to have the beer delivered in their neiborhood,
please email jim@greatbeerco.com with the name
address and phone number of where you buy beer.

Thanks

Steve Casselman, President
Virtual Computer Corporation
and
Associate Brewmaster
The Great Beer Company
Article: 6259
Subject: Re: ISP CPLD from AMD or Cypress???
From: Ed Barrett <ed.barrett@postoffice.worldnet.att.net>
Date: Mon, 05 May 1997 19:35:33 -0500
Links: << >>  << T >>  << A >>
Scott Thomas wrote:
> 
> On Fri, 02 May 1997 12:20:21 -0700, Ed Barrett
> <ed.barrett@worldnet.att.net> wrote:
> 
> >
> >As for speed, the 2032 offers a true 5.0 nsec tpd and 180 Mhz operation.
> >Also, for CPLD architectures tpd is fixed. The Lattice 5.0 nsec is a
> >fixed guaranteed worst case delay.
> 
> Isn't this 5.0 nsec speed only for dedicated inputs (two on the 2032)
> and no more than 4 product terms? Doesn't the timing change if I/O
> pins are used as inputs, more prouct terms are used, if routing pools
> are used? These may be fixed, guaranteed worst case delays, but don't
> these cause the tPD to exceed 5.0 nsec?
> 
> The point Steve was making is the equivalent Vantis device
> (MACH111SP-5) doens't exceed 5.0 nsec.--i.e., Vantis' worst case is
> Lattice's best case.
> 
> Scott Thomas
> Vantis


Wrong again. The 5.0 nsec tpd iScott Thomas wrote:
> 
> On Fri, 02 May 1997 12:20:21 -0700, Ed Barrett
> <ed.barrett@worldnet.att.net> wrote:
> 
> >
> >As for speed, the 2032 offers a true 5.0 nsec tpd and 180 Mhz operation.
> >Also, for CPLD architectures tpd is fixed. The Lattice 5.0 nsec is a
> >fixed guaranteed worst case delay.
> 
> Isn't this 5.0 nsec speed only for dedicated inputs (two on the 2032)
> and no more than 4 product terms? Doesn't the timing change if I/O
> pins are used as inputs, more prouct terms are used, if routing pools
> are used? These may be fixed, guaranteed worst case delays, but don't
> these cause the tPD to exceed 5.0 nsec?
> 
> The point Steve was making is the equivalent Vantis device
> (MACH111SP-5) doens't exceed 5.0 nsec.--i.e., Vantis' worst case is
> Lattice's best case.
> 
> Scott Thomas
> Vantis

-- 
Wrong again. The 5.0 nsec tpd is any I/O pin to any other I/O pin just
like you would expect. No magic No hidden delay.

Ed
Article: 6260
Subject: Advantages/disadvantages between CMOS/BiCMOS
From: mazlaini@ms.mimos.my (Mazlaini Yahya)
Date: 6 May 1997 11:28:31 +0800
Links: << >>  << T >>  << A >>
Does anybody know what are the advantages/disadvantages for chips that were designed for target process CMOS or BiCMOS.

Design engineers widely understand that CMOS consumes less power while BiCMOS
eats lots of power but the trade off is that you get extremely high unity-gain
bandwidths.

Are there any convincing advantages/disadvantages on CMOS/BiCMOS?
From a design point of view, what platform should a designer target his/her
design between CMOS and BiCMOS to get the most cost effective chip out of the
two processes.



********************************************************************
Please visit : http://www.jaring.my/mimos/bi/rd/icdc/icdcprof.html

*******************************************************************
Article: 6261
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Date: Mon, 5 May 1997 23:48:21
Links: << >>  << T >>  << A >>
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Article: 6262
Subject: Re: New Lattice (is)pLSI Resynthesis Server now online
From: Albrecht Ditzinger <albrecht.ditzinger@isdata.de>
Date: Tue, 6 May 1997 10:18:49 GMT
Links: << >>  << T >>  << A >>
Tim Forcer <tmf@ecs.soton.ac.uk.nospam> wrote:
>Frank Dresig wrote:
>>For those of you designing with Lattice (is)pLSI devices
>>it might be interesting to check out our newly announced
>>Lattice Resynthesis server. 
>>..cut.. it accepts a (is)pLSI design and resynthesiszes it to
>>improve speed, resource usage and fittability.
>>..cut.. The service is free, so at least it might
>>be worth a try.
>>..cut..
>
>Tim Forcer <tmf@ecs.soton.ac.uk.nospam> wrote:
>
>..cut..
>
>What is the position on Intellectual Property?  Specifically, would
>ISDATA hold any rights in the resynthesised design?
>

The answer to this one should be simple: Just running tools to process a design does not give 
the tool manufacturer any rights in the design.

>
>What security is there for designs submitted for resynthesis?
>

Here I think it is mainly a problem of what you can gain vs what the risk is. By chance, I've 
just seen a LAF pass the server coming in with 49 GLBs (not fitting a 1048) and returning 
with 48 GLBs (fitting a 1048). I hope this is a little help to the designer provided that all 
other possible obstacles (timing etc) can be removed for this design. So this might be an 
example of what you can get.

The idea to offer such kind of service was born at the overcrowded "CAE on the Web" session 
at DAC 95. There a statement was made that the future of CAE usage could be to use the most 
approriate software for a given problem via the net, instead of installing lots of packages 
locally. This approach is fascinating, especially for the synthesizer / fitter or 
synthesis / P&R combination. As all synthesizers work on a heuristic basis, the very same 
design that costs you days (and nights) to find a fitting Lattice or routable XILINX 
solution, may work immediately when simply run through a different synthesizer using 
different heuristics. By the way, of course we think that our heuristics are somewhat 
better than the other guys heuristics :-) 

So this is a typical case where "CAE on the web" could be benefical.

And the risk? Of course, all design data travelling the net are vulnerable. Of couse, we 
could not adhere to the text of our Web-Page "all design data are processed automatically and 
deleted after processing, with the exeption of some figures for our statistics". I have 
only basic knowledge of the legal side, but I assume, not deleting the design data sent to us 
under such an assumption, would be a breach of the law.

In conclusion: For such a free service, every designer has to evaluate the gain / risk 
situation based on the security needs for the design. If "CAE on the web" becomes a reality 
in the future, with defined provider / customer relations, it should be possible to solve the 
security problem on a contract basis similar to an NDA.

-- 
Albrecht Ditzinger
ISDATA Karlsruhe   WWW: http://www.isdata.de

A very old bavarian saying says: Saving on design tools 
means paying a fortune for devices.


Article: 6263
Subject: Re: Announcing new division & an fpga implementation
From: husby@fnal.gov
Date: Tue, 06 May 1997 08:01:26 -0600
Links: << >>  << T >>  << A >>
Vitit Kantabutra wrote:
> Likewise, I don't know whether Don Husby's implementation was an
> optimal one.  But I am thankful that an implementation exists.
> I never meant to imply that Don Husby endorses the algorithm.
> However, I still think that our algorithm might be faster than the
> traditional bit-by-bit ones, at least for larger word lengths.
>
> It is very important to note that our algorithm only requires ONE
> full-length subtraction to retire 2-3 operand bits, plus a 2-bit
> comparison and a little more simple logic.  Admittedly, my
> experience in only in full-custom design, not FPGA's.  (And in
> fact, I didn't think of FPGA's at all when I wrote that paper.
> I didn't think about FPGA's until Don Husby and a lot of other
> FPGA people wrote me email in response to my earliest Usenet News
> posting a few weeks ago.)
>
> However, it does appear, intuitively speaking, that at least for a
> large enough word length (maybe more than 8 bits?), a circuit using
> our algorithm could be faster than one that needs 2 full-length
> subtractions to retire 2 bits.

I agree.  For long word widths, there will eventually be some
advantage for Kantabutra's algorithm.  My guess is that crossover
point is greater than 32 bits.  Here's an explanation:

FPGA's are based on lookup tables, so implementing some complex
functions is no more costly than implementing simple functions.  A
4-bit adder takes about the same number of resources and time as
a 2-way 4-bit multiplexer.  Also, the routing between logic blocks
is much more dominant in an FPGA than a custom chip.  The time to
route signals between two logic blocks is typically 1/2 to 2 times the
actual logic propagation delay: e.g. A logic block may take 3ns while
the time to route signals beween logic blocks may take 1.5 to 6 ns.
Carry paths have been optimized to eliminate this routing delay
between blocks used as arithmetic units.

Kantabutra's algorithm requires at least a 3-way word-width
multiplexer plus one level of logic to control the multiplexer.
To implement this for a 32-bit data path requires 9 ORCA PFUs
(or 33 Xilinx CLBs) and two levels of logic.  To implement a
32-bit sub-mux requires 8 PFU (or 16 Xilinx CLBs) and about the
same amount of time as two levels of logic.

-------
Included below is a C-language simulation of both algorithms.  It was
written using Borland C.
-------

#include <stdio.h>
#define Iter 9     /* Number of result bits (iterations) Must be < 23  */
#define Filt 16    /* Print any error >= 2^Filt                        */

void PrintB(char *S, long I, int Size)  // Print Bits diagnostic
{ printf("%s",S);
  while (Size--)
  { if (Size%4==3) putchar(' ');
    if (I & (1L<<Size)) putchar('1'); else putchar('0');
} }

long Div_S(long R, long D)  // Simple Division Algorithm
{ // R is a 15-bit positive integer
  // D is an 8-bit positive integer > 128
  // Return 16.16 integer.fraction format

  int  I;         // Number of bits in result
  int  N=24-Iter; // Normalization count
  long T;         // Temporary
  long Q=0;       // Quotient

  D <<= 7L;       // Normalize to 16.16 int.fraction format
  for (I= Iter; I>0; --I)
  { Q <<= 1;
    T = R-D;
    if ((T&0x10000L)==0) { Q |= 1;  R = T; }
    R <<= 1;
  }
  Q <<= N;
  return(Q);
}

long Div_K(long R, long D)  // Kantabutra's Division Algorithm
{ // R is a 16-bit signed integer
  // D is an 8-bit positive integer
  // Return 16.16 integer.fraction format

  long D2,D3;     // 2*D and 3*D
  int  I=Iter;    // Number of bits in result
  int  N=23-Iter; // Normalization count
  int  Case;      // Case is 0 to 3 as described below
  int  T;         // Temporary
  int  Dbit;      // Used in case determination
  long Q=0;       // Quotient

  D <<= 8L;             // Normalize to 16.16 int.fraction format
  Dbit=((D&0x4000)!=0); // Get 2nd MSB
  D2= D+D;
  D3= D+D+D;

  R |= -(R&0x8000L);   // Extend sign of R
  R<<=1L;              // convert to 16.16
  if (R>0 && R>D || R<0 && -R>=D)  // Ensure R<=D
  { R /=2; ++N; }

  while (I>0)          // Main Loop
  { T=(R>>13L) & 15;   // Get 4 bits of R  x.xxx

    // Case determination.  This can be done in a single 5-input LUT.
    if      (T==0 || T==15)           Case= 0;  // R  <  1/8
    else if (T==1 || T==14)           Case= 1;  // R  <  1/4
    else if (T<3  || T>12)            Case= 2;  // 2R <= D
    else if ((T==3 || T==12) && Dbit) Case= 2;  // 2R <= D
    else                              Case= 3;  // 2R >  D

    if (Case==1)                  // Handle cases
    { R <<= 1L; Q <<= 1L; I-=1;   // Case 1, shift a zero into Q
      continue; }

    R <<= 2L; Q <<= 2L; I-=2;     // Case 0,2,3 shift 2 bits
    if (Case==0) continue;        // Case 0: shift 2 zeros

    if (Case==3) D=D3; else D=D2; // Choose D
    if ((T&8)==0)                 // Get sign of R
    { R-=D; Q += Case; }          // If sign is positive
    else
    { R+=D; Q -= Case; }          // If negative
  }
  Q <<= (N+I);
  return(Q);
}

main()
{ long R,D;
  long F,Q,X;
  int E=0;
  int Log;
  long Histo[32];
  for (Log=32; Log--;) Histo[Log]=0;
  printf("Testing division algorithm with %d iterations\n",Iter);

  for (R=16384L; R<32768L; ++R) for (D=128; D<256; ++D)  // Test all
combinations
  { F= (R*65536L)/D;                // Compute quotient using cpu
    Q= Div_K(R,D);                  // Compute using division algorithm
    X= (F-Q); if (X<0) X= -X;       // Find ABS(F-Q)
    for (Log=0; X; X>>=1L) ++Log;   // Find Log2(X)
    ++Histo[Log];                   // Enter into histogram
    if ((Log>=Filt) && (E < 10))    // If error bigger than Filter, print
    { ++E;
      printf("%5ld / %5ld\n",R,D);
      PrintB(" Expect: ",F,32); printf(" =%10.5f\n",F/65536.0);
      PrintB("    Got: ",Q,32); printf(" =%10.5f\n",Q/65536.0);
    }
  }
  for (Log= 32; Log--;) printf("%2d %8ld\n",Log,Histo[Log]);
  printf("Press return to exit."); getchar();
  return(0);
}

-------------------==== Posted via Deja News ====-----------------------
      http://www.dejanews.com/     Search, Read, Post to Usenet
Article: 6264
Subject: Re: FPGA chip on Khepera robot
From: Roger Gook <104330.1033@compuserve.com>
Date: 6 May 1997 15:37:21 GMT
Links: << >>  << T >>  << A >>
Asger Sporring wrote:
> 
> I'm doing my master thesis on EvolHard, and am going to use the
> Khepera robot for some practical testing.
> 
> But I need to place a FPGA chip (right now I'm looking into using the
> Xilinx chips(like Splash 2), but this is not fixed) on the robot, for
> it to be of any use.
> 
> Does anybody have any experience with this (using, I assume, the
> general IO turret).
> 

Embedded Solutions Ltd. markets a modular board package known as the 
Accelerator System. Modules are equipped with a mezzanine daughter board 
I/O connector. This system is planned to be supported by a commercial 
release of the Handel-C programming language, which enables a programmer 
to directly target the FPGA, without recourse to a HDL, in a similar 
fashion to a classical microprocessor cross-compiler. 
http://www.embedded-solutions.ltd.uk

*******  Crossposted: comp.robotics.research (moderated)  *******
  Summary: Academic, government & industry research in robotics.  
      Archives and information: http://www.robot.ireq.ca/CRR      
         Charter: ftp://ftp.robot.ireq.ca/pub/crr/Charter         
      Meta-discussions/information: crr-request@robot.ireq.ca     
Article: 6265
Subject: Re: Global GSR net in a Xilinx design (Synopsys)
From: ploog <ploog@baltic.e-technik.uni-rostcok.de>
Date: Tue, 06 May 1997 19:15:57 +0200
Links: << >>  << T >>  << A >>
Arrigo Benedetti wrote:
> 
> Dear all,
> 
> I have a question about the instantiation of the STARTUP block in a
> design implemented in Synopsys ver. 3.5a.
> What it is not clear to me is the example in the Xilinx Synopsys
> Interface for FPGAs ``Interface/Tutorial Guide'' presented in chapter 7,
> fig. 7-1. What I don't understand is why the STARTUP component is not
> instantiated in the count8 architecture: in this way in fact the GSR net is
> totally useless. If you look at the count8_vss.vhd generated by xnf2vss
> (a copy of it is in $XACT/tutorial/synopsys/vss/xc4000) you will see that
> each flip-flop is connected both to GSR and CLR.
> In other words my question is: is it possible to exploit the global GSR net
> and still perform a timing simulation ?
> I've not been able to try instantiating the STARTUP block and run xnf2vss
> only beacause at my site the Xact core tools license has not been
> installed yet.
> 
> Thanks in advance
> 
> -Arrigo
> --
> Arrigo Benedetti                    e-mail: arrigo@vision.caltech.edu
> Caltech, MS 136-93                              phone: (818) 395-3695
> Pasadena, CA 91125                              fax:   (818) 795-8649


Yes, you are right. For BEHAVIORAL simulation the GSR-signal is useless,
BUT
if you are going to simulate the backannotated file (count8_vss.vhd) you
still
need the GSR-signal, because there IS a startup-phase in your design and
so the
flipflops will have a default-state even without any signals on the
reset-pin
(remember clock-devider-ff, they do NOT need an reset-signal for
working). What XILINX
did (maybe) is a timing-simulation of their behavioral-model.
So my advice for you:
 - write your 'normal' VHDL-file (without any GSR, STARTUP ..)
 - create a higher level of hierarchy and instantiate your modul & GSR &
STARTUP..
 - create a testbench (one for both : behavioral AND timing simulation)
 - all things will work pretty fine...(hopefully)

 Hope that helps,
   Hagen
Article: 6266
Subject: USB, PCI, ISA ref material pointers wanted
From: eteam@aracnet.com (bob elkind)
Date: Tue, 6 May 1997 19:03:05 +0100
Links: << >>  << T >>  << A >>
Fellow comrades, I need and covet your assistance.

I'm looking for design, specification, reference material
(etc.) on USB, PCI, and ISA interfaces.

Any/all pointers will be most warmly appreciated.  Thanx!

-- Bob Elkind

****************************************************************
Bob Elkind                              mailto:eteam@aracnet.com 
7118 SW Lee Road               part-time fax number:503.357.9001
Gaston, OR 97119           cell:503.709.1985   home:503.359.4903
****** Video processing, R&D, ASIC, FPGA design consulting *****
Article: 6267
Subject: CFP: Computing Surveys Tutorial Paper Contest
From: cavazos@mimas.cs.umass.edu (John Cavazos)
Date: 6 May 1997 20:17:44 GMT
Links: << >>  << T >>  << A >>


--
-----------------------------------------------------------------------
John Cavazos                                       cavazos@cs.umass.edu
Department of Computer Science                           (413) 545-0256
University of Massachusetts at Amherst              Fax: (413) 545-1249
Amherst, Ma. 01003                     http://www.cs.umass.edu/~cavazos
Article: 6268
Subject: CFP: Computing Surveys Tutorial Paper Contest
From: cavazos@pilgrim.umass.edu (Johnny Cavazos)
Date: 6 May 1997 23:20:41 GMT
Links: << >>  << T >>  << A >>
Let me try this again...


                               CALL FOR PAPERS
              Computing Surveys Student Tutorial Paper Contest

Computing Surveys is sponsoring an annual competition for the best student
tutorial paper. The paper should be in the form of a substantive tutorial of
5000 to 12000 words that examines a topic of computer science at a level
understandable by senior undergraduate students. It should conform to the
standards of Surveys tutorials, combining tutorial clarity, historical and
scholarly perspective, and technical interest.

Submissions will initially be judged by a panel of students who will
recommend between five and ten papers to a panel selected by the Editors of
Computing Surveys. The panel will select the best paper from among these for
publication in Surveys and select runners-up for honorable mention. Student
ACM chapters as well as undergraduate computer science departments should
actively promote this competition as a way for students to develop their
writing and tutorial skills.

Papers should have been written in the previous two years and should not
have been previously published in commercial publications. However, papers
previously published in the ACM student mazazine Crossroads or in other
student publications will be accepted. The paper should be accompanied by a
letter from a faculty sponsor that certifies it as the work of the author or
authors and describes the circumstances under which it was written. Authors
should normally be undergraduates or graduate students with less than two
years of graduate school and should normally be members of the ACM, but
exceptions will be considered based on letters from the faculty sponsor.
International participation is encouraged, as in the student programming
contest. Information on becoming a Student ACM member can be found at
http://www.acm.org/membership/. Further information about the contest can be
found at http://osl-www.cs.umass.edu/~cavazos/Contest/. Updated information
will be posted on this page periodically.

Submission for the 1997 competition are due by June 30, 1997. Students will
make a recommendation to the Editors of Surveys by August 31, and the winner
will be announced by October 31 and published in an issue of Surveys no
later than the summer of 1998. It is desirable though not required that
contestants indicate their intention to submit, with a provisional title.
Submissions can be sent electronically to cavazos@cs.umass.edu, or submitted 
in hard copy form to:

John Cavazos
Dept of Computer Science
University of Massachusetts at Amherst
Amherst, Mass, 01003
Article: 6269
Subject: Re: Advantages/disadvantages between CMOS/BiCMOS
From: jws@billy.mlb.semi.harris.com (James W. Swonger)
Date: 7 May 1997 13:25:37 GMT
Links: << >>  << T >>  << A >>
>Does anybody know what are the advantages/disadvantages for chips that 
>were designed for target process CMOS or BiCMOS.
 
>Design engineers widely understand that CMOS consumes less power while 
>BiCMOS eats lots of power but the trade off is that you get extremely 
>high unity-gain bandwidths.
 
>Are there any convincing advantages/disadvantages on CMOS/BiCMOS?
>From a design point of view, what platform should a designer target 
>his/her design between CMOS and BiCMOS to get the most cost effective 
>chip out of the two processes.

CMOS advantages: low static power dissipation, most advanced feature size
 (if you want to push it), largest number of foundry sources, simpler
 process architecture usually means lower wafer cost. A very small
 geometry CMOS process may be faster in analog applications than a 
 less advanced bipolar or BiCMOS process (see RF work being done in
 CMOS-only processes - Berkely?) 

CMOS disadvantages: No bipolars, some circuits not practicable or more
 difficult to implement

BiCMOS advantages: richer device set. Bipolars are easier to make high 
 frequency analog circuits, precision references, low-offset amplifiers
 with. And you can always constrain yourself to only use the CMOS if
 you're trying to keep static power down. CMOS circuits at speed may
 have more total losses (capacitance is higher) than bipolars. May 
 allow more compact circuits for some types. 

BiCMOS disadvantages: More complex process, higher wafer cost, probably
 less advanced lithography (process probably took longer to get up and
 running since there were more device types to global-optimize). 
 
Since you can use the CMOS in either case, designers would generally opt 
for the greater up-front design freedom. Meanwhile whoever's holding the
money bag will press for straight CMOS implementations. If you know the
circuit functional content you can make a more considered choice. There
is no generalization that works - else why would there be options?
-- 
##########################################################################
#Irresponsible rantings of the author alone. Any resemblance to persons  #
#living or dead then yer bummin. May cause drowsiness. Alcohol may inten-#
#sify this effect. Pay no attention to the man behind the curtain. Billy!#
Article: 6270
Subject: [Help] Buggy LFSR in Xilinx Application notes???
From: Christos Dimitrakakis <mbge4cd1@afs.mcc.ac.uk>
Date: Wed, 07 May 1997 14:47:15 +0100
Links: << >>  << T >>  << A >>
i just did (ie copied) the circuit illustrated in [figure 5] of
'Efficient Shift Registers, LSFR Counters, and Long Pseudo-Random
Sequence Generators' (p. 4) 
I used Mentor Graphics for the schematic capture.
I had a few problems when simulating (quicksim2)
The address sequence seems to be 16 cycles long (which is right), the
RAM seems to be loaded with the right values, BUT as soon as I switch
load to low one of the following happens, depending on my loaded-in
sequence.
1) The output is always 0
2) The output is always 1
3) The output is the same as any of the address bus bits, but shifted
and repeats every 16 cycles...

Any ideas?
Did I do something wrong?

(I used 16x1 xc4000 RAMs in place of the 15x1 RAMs displayed in the
schematic
I always hold WE high
Presumably the address-generating FFs feedback to Q1..Q4)

*HHEELLP* 

-- 
Christos Dimitrakakis
---------------------
mailto:mbge4cd1@fs4.eng.man.ac.uk
mailto:mbge4cd1@afs.mcc.ac.uk
http://www.man.ac.uk/~mbge4cd1
Article: 6271
Subject: universal PCI-Interface with FPGA?
From: koehler@mst.uni-hannover.de (Ralf Koehler)
Date: 7 May 1997 15:26:21 GMT
Links: << >>  << T >>  << A >>
Hi,

we are looking for an universal PCI interface for a board design.
A possible solution would be a FPGA based PCI bridge. 
Are there any practical experiences with such PCI interfaces ? 

Thanks in advance

Ralf


Article: 6272
Subject: Re: Advantages/disadvantages between CMOS/BiCMOS
From: tk@ai.mit.edu (Tom Knight)
Date: 07 May 1997 15:46:14 GMT
Links: << >>  << T >>  << A >>
> From: jws@billy.mlb.semi.harris.com (James W. Swonger)
> Newsgroups: sci.electronics.design,sci.electronics.misc,sci.electronics.cad,sci.electronics.components,sci.electronics.repair,sci.engr.semiconductors,comp.arch.fpga,comp.arch.embedded
> Date: 7 May 1997 13:25:37 GMT
> Organization: Harris Semiconductor, Melbourne, Florida
> 
> >Does anybody know what are the advantages/disadvantages for chips that 
> >were designed for target process CMOS or BiCMOS.

An important issue which was left out of the previous list is the
scalability of the process to smaller feature sizes (and therefore
lower voltages).  Right now, a .25 micron process really wants to run
at about 2.5 volts or less; as we scale to .15 or below, the voltages
continue to go down.

Unfortunately, the Vbe of bipolar devices does not scale with
dimension, but remains a constant (roughly) since it depends on the
log of the doping concentrations and the temperature.

So, since for most bipolar circuits we need 5Vbe to 3Vbe of power
supply voltage, and Vbe is about 0.75 volts, we have a severe
conflict.

BiCMOS thus has a very limited life span, due to scaling laws.

Do your design in pure CMOS and take advantage of the next 15 years of
scaling.

Note that this is what Intel is doing, as opposed to what they were
saying three years ago, when BiCMOS was the "killer technology" which
would soon wipe everyone else off the map.  Anyone with a half decent
process oriented education knew this was BS then, but the trade and
financial press thought it was great.

Homework: Compare and contrast Exponential.




Article: 6273
Subject: Re: [Help] Buggy LFSR in Xilinx Application notes???
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 07 May 1997 12:55:56 -0700
Links: << >>  << T >>  << A >>
I wrote this app note, and I never heard of a problem with it. But then
we usually don't know how many people implement such app notes....

The address counter is supposed to divide by 15, not by 16, as you
wrote. The front page of the app note describes how this 4-bit counter
divides by 15, but there are hundreds of other ways to build a 4-bit
counter that skips one of its codes.

I wrote 15 x 1 into the RAM because that's the way they are being used.
Of course, they are really 16 x 1 RAMs, but one location is never used.
Four times fifteen is sixty. Plus three flip-flops makes it a 63-bit
shift register. That was carefully chosen, since 61, 62, 64, 65, 66, 67
etc -bit LFSR counters require a more complex feedback.

Best way to debug is to break the feedback chain and exercise this
design as just a 63-bit shift register. If that doesn't work, look at
intermediate points and see where the mistake is buried. 

The divide-by-15 counter has to work, and the 63-bit shift register has
to work before you can close the XNOR loop and make it an LFSR.
Please e-mail me with the results of your debugging.
peter@xilinx.com

Peter Alfke, Xilinx Applications
Article: 6274
Subject: US - San Jose - Firmware Engineer (Analog, Digital, DSP)
From: Volt Services Group <volt1@ix.netcom.com>
Date: 7 May 1997 21:20:53 GMT
Links: << >>  << T >>  << A >>


Will be responsible for analog and digital circuit design for wide-dynamic  
low noise instruments.  Requires a high degree of ability to make tradeoffs 
between competing goals and customer requirements.

These designs have a high degree of interaction between analog and  
digital circuitry in order to make the desired measurements.  The position  
will utilize a wide range of design skills, from frequency analog design, to  
nonlinear systems analysis, to DSP (digital signal processing) and real-time 
firmware design.

Requirements:

BSEE minimum (MSEE preferred)
DSP
C and/or C++
Windows NT or Windows 95 experience is desired
Superb written and verbal communication skills

Lloyd D. Songne, Jr.
Regional Recruiting Manager
Volt Services Group
Email: volt1@ix.netcom.com

Visit our interactive employment web site at http://www.volt-tech.com




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