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> > Does anyone know what is needed to work with surface mount > > ic's, what sort of starting price tag are we talking about? > > (Assuming I have ready made boards, i.e. only the soldering > > phase is required) > > > > > How long's your piece of string? > Specifically, what type of SMT package are you using? If SOIC, PLCC > etc., you can do it with just a fine-tip soldering iron. > Poeple have reported doing BGA's in a toaster, but I haven't tried it > myself. > Is this a one-off hobbyest situation, or volume production? As I said, starting price tag, meaning proffessional one off production. Or hobbyist will do, as long as it is not ad-hoc type scenario.Article: 114001
Ulrich Bangert wrote: > Addressed to the XILINX insiders: > > I have made me myself a small pcb which is basically a replica of the simple > Xilinx JTAG download cable. This JTAG interface works well with Xilinx CPLDs > and also with Altera FPGAs and CPLDs (after some pin mapping on the printer > port side, of course, making it look like a Byteblaster cable to the Altera > tools). > > However, if I try to program a Spartan XC3S400 on a board coming from > > http://www.siphec.com > > the JTAG id is read wrong and programming fails. After some experiments and > talking to the developers at Siphec it turned out that a resistor in the > order of 560 Ohms to ground on the TCK line will solve the problem. At the > first glance one might think that this resistor works as kind of cable > termination reducing reflections on the clock line. > > The strange thing is: The positive effect of the resistor takes place ONLY > if the resistor is mounted close to the 74HC125, i.e. BEFORE the JTAG cable > connection to the aimed board. If the resistor is soldered to the aimed > board near the fpga(where it could work as a termination) programming will > fail as well. This all looks very mysterious to me! > > Is there some special TCK conditioning necessary for the Spartans that I am > not aware of and that lets them behave different to other fpgas/cplds ?? > > TIA for your help > Ulrich Bangert There is a schematic on the Xilinx web site for their Parallel-III programming cable. This cable is used to program both CPLDs and FPGAs. Notice that there are _no_ pull down resistors. However, there are capacitors from the outputs of the HC125s to ground. schematic - http://www.xilinx.com/support/programr/files/0380507.pdf HTH -Dave PollumArticle: 114002
colin wrote: > Hi all > > I'm having trouble finding pcb layout recomendations on the altera and > xilinx web sites for lead free bga's. I'm wanting to use an altera F256 > package and I can find all I need for the leaded version but nothing > for the rohs packages. Does anyone know where I should be looking or > what changes to the leaded footprints I should make? > > all the best in 07 > > Colin I'm facing that issue right now for a FT256 package, and I'll do what I've done with all the other RoHS BGA parts I've had done leadfree (and that's quite a few) - use non-SMD pads with the recommended sizes from the leaded versions. If my manufacturer thinks it needs to be tweaked - after all, they do a *lot* of BGAs - they'll let me know. So far I haven't had any problems provided I use a gold finish; of course, I haven't had sufficient time to get decent long term reliability data. Cheers PeteSArticle: 114003
"Piotr Wyderski" <wyderski@mothers.against.spam-ii.uni.wroc.pl> wrote in message news:en97g5$8hu$1@news.dialog.net.pl... > KJ wrote: > >> If you go about the process as figuring out the requirements of the >> arbitration function and work through the requirements that each master >> presents and the target SRAM slave then it should start to fall into >> place. > > Well, think of many DMA channels connected to much slower > clock domains, it's a good model. The problem is how to pass > their data and configuration parameters between the main clock > domain and their respective domains. > > Now I think that a separate RAM clock domain is too hard to > be implemented reliably Why would you think that? It's not true. > so I can redesign the system in order > to run the CPU at the same clock rate. It will allow me to > implement the arbitrator in an old way, i.e. to add the HLD > signal to the CPU and state that the DMA controller has > higher priority, but it will require more (mostly unidirectional) > synchronization bridges elsewhere. The arbitrator will get implemented however you want it to be, you're not constrained to a simple priority scheme....the arbitration function is what you're designing. > They must be made of > CLBs, because I need BRAMs for better purposes. > As a general approach, transferring between different clock domains is accomplished with a dual clock fifo. In many cases a full blown fifo is not really needed, mainly just some handshaking signals to go back and forth are the tricky part. In any case, the address, data and control signals get sampled in the clock domain that they originate from and the handshake acknowledge signal gets generated in the 'other' clock domain. All of this though has absolutely nothing to do with memory controllers or arbitration it has to do with clock domain transfers. Although the SRAM can operate without a clock, it is very unlikely (also read as very difficult, many times just not possible in an FPGA environment) to design an arbitrator to operate without a clock so you'll most likely need to choose one clock from your system; if this clock happens to be the same as the CPU (or any of the other SRAM masters) than that particular master(s) will be able to operate synchronously and directly with the arbitrator. Any master device that operates synchronous to another clock will need to be synchronized first. Whether or not the clock domain crossing fifos require CLBs or BRAMs depends mostly on how quickly data comes in from a particular master and how much latency it can tolerate. Usually the quicker the memory request comes in the more depth you need to your fifo otherwise you compromise system performance. You can implement the fifo in CLBs or BRAMs as you see fit, it's a tradeoff you make based on resource usage, clock speed and system performance. Kevin JenningsArticle: 114004
Rick North wrote: > Hi all, > > I want to load my PPC program in an external SRAM connected to the PLB > bus on the PPC. But I fail to find any suitable IP with in EDK. For now Checkout the documentation on opb_emc and plb_emc. Or just create a BSB design for a board that has SRAM and look at the design. /SivaArticle: 114005
hello i had the same troubles (but with ISE 8.1). i found i can generate the hex files in command line : promgen -w -p hex -c FF -o fichier.hex -u 0 fichier.bit -b let me know if it works for you ( to bad that AVNET doesnt have o correct support ! we could gain a lot of time )Article: 114006
smount wrote: > As I said, I did look, but coudn't find > >> If you don't wish to do the work of looking, reading and >> *understanding*, then our help would be futile anyway. >> >> Cheers >> >> PeteS > > I don't have the datasheets in front of me, but here's a suggestion: Go to htttp://www.xilinx.com/ Get to the XL9536 page: Look for 'application notes' I am sure there's one on using GCLK Cheers PeteSArticle: 114007
Symon wrote: > <smount> wrote in message news:4599cdbe$1_4@mk-nntp-2.news.uk.tiscali.com... > > Does anyone know what is needed to work with surface mount > > ic's, what sort of starting price tag are we talking about? > > (Assuming I have ready made boards, i.e. only the soldering > > phase is required) > > > Hi, > Try this Google search:- > solder group:comp.arch.fpga author:freidin > > Philip gives a list of links you'll find interesting. > HTH, Syms. > > p.s. On the subject of US vs. UK toasting techniques, IMO the problem in the > US is not the toaster machines, it's the post-toasting technology. The toast > just gets piled up on a plate. The US seems to be a veritable toast rack > desert, so the toast always ends up soggy. I guess that's why it's IHOP and > not IHOT! :-) I live in the US and use a toaster to toast bread. The bread goes in vertically. I don't know what restaurants use. A toaster oven is a small counter top appliance. I've never used a toaster oven to toast bread or cook anything - I use mine to relow SMD parts using solder paste ;) For a more commercial SMD oven, I think Zephyrtronics has some desk-top units. They sell solder paste that's a lot cheaper than Digikey. -Dave PollumArticle: 114008
"Dave Pollum" <vze24h5m@verizon.net> writes: > I've never used a toaster oven to toast bread or cook anything - I > use mine to relow SMD parts using solder paste ;) I use the toaster oven to toast bread, and a hot plate to reflow SMD parts.Article: 114009
The default radix on waveforms is decimal and although I can right click the waveforms and change the radix to hex, it reverts back to decimal if I resimulate the design. Is there any way in the test bench VHDL file, or anywhere else, I can force the radix to remain to be hexadecimal?Article: 114010
Hi, I'm new to Xilinx devices and tools so please bear with my ignorance. I have an on-chip component that interfaces off chip devices (ADC's, etc.) to the Microblaze processor. The interface is precisely a port of a dual-port BRAM. 1) Initially, I thought it would be easiest to simply map the various signals into GPIO of the Microblaze (speed at this point is not important, getting something running is). But the GPIO seem to only want to talk to the device pins. Anyone know how to insert a component between GPIO and device pins? 2) I've also tried to use a memory style interface using either the OPB-to-BRAM controller or the LMB-to-BRAM controller. However, no "Wizard" or component instaniator will fill in all the parameters correctly, and if I try to modify the files (*.mpd or wrapper *.vhd) either they get rewritten over with the original incorrect values or won't compile. Any suggestions on working this interface will be appreciated. Thanks for any help. TomArticle: 114011
Oops, I realized I omitted that it's a Virtex-4, in particular the Avnet LX25 Evaluation board. TomArticle: 114012
Fred wrote:
> Is there any way in the test bench VHDL file, or anywhere else, I can force
> the radix to remain to be hexadecimal?
If you mean ISE/modelsim, the command is
radix hex
at the modelsim prompt.
-- Mike Treseler
Article: 114013"DJ Delorie" <dj@delorie.com> wrote in message news:xnhcv9ayfq.fsf@delorie.com > "Dave Pollum" <vze24h5m@verizon.net> writes: >> I've never used a toaster oven to toast bread or cook anything - I >> use mine to relow SMD parts using solder paste ;) > > I use the toaster oven to toast bread, and a hot plate to reflow SMD > parts. And there is some else out there in "net land" that uses an electric skillet to reflow SMD parts although I personally think they are better for making grilled cheese sandwitches...... -- James T. WhiteArticle: 114014
"Mike Treseler" <mike_treseler@comcast.net> wrote in message news:5003s1F1dp3p6U1@mid.individual.net... > Fred wrote: > >> Is there any way in the test bench VHDL file, or anywhere else, I can >> force >> the radix to remain to be hexadecimal? > > If you mean ISE/modelsim, the command is > > radix hex > > at the modelsim prompt. > > -- Mike Treseler Many thanks for your reply. I'm using the ISE Simulator and thought Modelsim was a different simulator. Using ISE Navigator there doesn't seem to be prompt where I can enter such text.Article: 114015
That fixed the problems I was having and cut my code by about 50 lines. Thanks! mk wrote: > On Sun, 31 Dec 2006 23:14:29 +0100, Sean Durkin <news_jan07@durkin.de> > wrote: > > >idp2 wrote: > >> That is only one of my always blocks that works with cal_ram_di. I > >> have two others but they are based ont the conditions if(~done > >> &stepCnt==1) and if(~done & stepCnt ==2)...is that what is causing the > >> problem?? > >Probably. The synthesis tool probably found an occassion where two or > >more if-conditions are possible met at the same time, hence the signal > >is assigned in two different places, and the tool doesn't know which of > >the assigments is to be carried out. > > If only synthesis tools were that smart. Independent of the condition > the register is assigned, you will get this error if two always blocks > assign a register. Just don't do it. One solution is to move all the > assignment into a combinational always block ie one which generates > the D input of the flops to be assigned. Then you can add multiple > independent if conditions more easily and assign the d input to the > register in a clocked always block. > > ie > always @(*) > begin > if (some condition) > cal_ram_di_d = first; > if (some other condition) > cal_ram_di_d = second; > end > > always @(posedge clk) > cal_ram_di <= cal_ram_di_d;Article: 114016
"James T. White" <SPAMjtwhiteGUARD@hal-pc.org> writes: > And there is some else out there in "net land" that uses an electric > skillet to reflow SMD parts I got the idea from sparkfun.com See also http://www.delorie.com/pcb/hotplate/ for a picture of the hotplate I use. It's a small but cheap $20 unit from Target. Here's a board I reflowed on it: http://www.delorie.com/pcb/m3a/Article: 114017
> > 2) I've also tried to use a memory style interface using either the > OPB-to-BRAM controller or the LMB-to-BRAM controller. However, no > "Wizard" or component instaniator will fill in all the parameters > correctly, and if I try to modify the files (*.mpd or wrapper *.vhd) > either they get rewritten over with the original incorrect values or > won't compile. Any suggestions on working this interface will be > appreciated. > Try creating an EDK design that has opb_bram. This will instantiate a bram block with one port of the BRAM connected to the opb_bram controller. Connect the other port of the BRAM to your peripheral. /SivaArticle: 114018
I'm using WebPACK 8.2 and EDK 8.2, and created a board definition file
(.xbd) for the Digilent Spartan-3 starter board with XC3S1000, based on
the Xilinx Spartan-3 starter board .xbd file. That works fine, and
now I want to add GPIO devices for the A2 and B1 expansion connectors.
None of the .xbd files supplied with EDK 8.2 show bidir GPIOs, so I
dug around in the .mpd file to figure out how to do it. I tried adding
this to the .xbd:
BEGIN IO_INTERFACE
ATTRIBUTE IOTYPE = XIL_GPIO_V1
ATTRIBUTE_INSTANCE = Exp_Conn_A2
PARAMETER num_bits = 32, IO_IS=num_bits
PARAMETER is_dual=0, IO_IS=is_dual
PARAMETER bidir_data=1, IO_IS=is_bidir # bidir data pins
PARAMETER all_inputs=0, IO_IS=all_inputs
PORT A2_4 = CONN_A2_4, IO_IS = gpio_io[0]
PORT A2_5 = CONN_A2_5, IO_IS = gpio_io[1]
PORT A2_6 = CONN_A2_6, IO_IS = gpio_io[2]
#...
PORT A2_34 = CONN_A2_34, IO_IS = gpio_io[30]
PORT A2_35 = CONN_A2_35, IO_IS = gpio_io[31]
END
and in the FPGA section:
### Expansion connector A2 ###
PORT A2_4 = CONN_A2_4, UCF_NET_STRING=("LOC=e6")
PORT A2_5 = CONN_A2_5, UCF_NET_STRING=("LOC=d5")
PORT A2_6 = CONN_A2_6, UCF_NET_STRING=("LOC=c5")
#...
PORT A2_34 = CONN_A2_34, UCF_NET_STRING=("LOC=b14")
PORT A2_35 = CONN_A2_35, UCF_NET_STRING=("LOC=d9")
Unfortuantely it doesn't seem to work. The BSB doesn't complain,
but it shows a mostly empty box where my peripheral should be
(between the DIP switches and the SRAM controller).
Is gpio_io[x] the wrong signal name for a bidir pin? Or am
I doing smoething else wrong?
Thanks!
Eric
Article: 114019Tom J wrote: > Hi, I'm new to Xilinx devices and tools so please bear with my > ignorance. > > I have an on-chip component that interfaces off chip devices (ADC's, > etc.) to the Microblaze processor. The interface is precisely a port > of a dual-port BRAM. > > 1) Initially, I thought it would be easiest to simply map the various > signals into GPIO of the Microblaze (speed at this point is not > important, getting something running is). But the GPIO seem to only > want to talk to the device pins. Anyone know how to insert a component > between GPIO and device pins? > > 2) I've also tried to use a memory style interface using either the > OPB-to-BRAM controller or the LMB-to-BRAM controller. However, no > "Wizard" or component instaniator will fill in all the parameters > correctly, and if I try to modify the files (*.mpd or wrapper *.vhd) > either they get rewritten over with the original incorrect values or > won't compile. Any suggestions on working this interface will be > appreciated. > > Thanks for any help. > > Tom > This may be of interest: http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/9af5a3a80c9ae87/f47a83956ec2ac3f?lnk=st&q=&rnum=4&hl=en#f47a83956ec2ac3f http://www.enterpoint.co.uk/techitips/OPB_RAM3.VHD take the above file through the import IP wizard, tell it you have a OPB slave interface, and map the IOs to OPB signals as appropriate. I was able to make this compile and route painlessly, though I haven't tested it out by actually running it.Article: 114020
On Jan 1, 4:58 am, tersono <ethel.thef...@ntlworld.com> wrote: > Check your email. > -- > Per ardua ad nauseam Thank you for your kindly help... I have tried your program on my board, however, I still can't get my desired result... I am now trying a new program on my board in a different way... to check whether the board can receive incoming signal correctly or not...Article: 114021
Rick North wrote: > Hi all, > > I want to load my PPC program in an external SRAM connected to the PLB > bus on the PPC. But I fail to find any suitable IP with in EDK. For now > I have bypassed the PPC and use a mux which either lets the PPC control > the SRAM or the FPGA fabric. Since the program gets loaded at start up > the PPC is hold in reset until the program is loaded. > > However, I would like to have a general PLB master function which can > access the PPC address space from the FPGA fabric. Does such an IP > exist or am I missing something about EDK IPs which makes this > possible? I am in the same boat - i.e. I have the need to develop a master PLB interface for my own FPGA fabric logic. From what I have gathered so far, there is a PLB IPIF type component. However, I tend to agree with some on this NG who question how useful that really is - you still need to understand how the client side IPIF interface works, it takes up logic and will probably not be optimized for your application. At the end of the day, it may be better to just bite the bullet and read the PLB coreconnect spec and whip up your own interface with just the functionality you need. What I am unclear on is what type of simulation models are available for helping me debug my own interface design. I just have Modelsim Xilinx Edition (not PE or EE). I haven't been able to get a clear picture of what is available for MXE. I have seen reference to bus functional models, but I think you need the outrageously expensive version of Modelsim to run it - can anybody verify whether this is true? For your booting problem, could you allocate one or two block rams to hold a PPC bootloader? The bootloader could read your flash or wherever your code comes from using the DCR bus or something and initialize your external big RAM space that way. -JeffArticle: 114022
highZ wrote: > Which one, there are many datasheets for the 9500 familiy and > for each specific one. I had a glance at all of them and couldn't > see all these things. What exactly does 'reset' do in the first > place, well I will see again if I can find it. Thanks CPLD data is not the most user friendly, and can give the impression they do not chase new users. For Xilinx, look at both the pdf called "XC9500 In-System Programmable CPLD Family", and also the device data sheet, and you do need to make the odd leap. Fig 1 has some overview, Fig 3, Fig4 have more details. In fig 1, GCK is tagged as 3 lines, and Data Sheet PIN map shows GCK1, GCK2, GCK3 Fig4 shows how those GCKx lines feed all FF's (Fig 3 calls them Global Clocks) Most common Macrocell resource ( CLK, SET, RESET in 9536 case) have the choice of Global, or Product Term drive. Pin resource also has Global OE, but called GTSx in some places, and Global OE in others (see Fig 10) GSR can map to either SET or RESET, so you can use one gobal signal, to load one initial pattern into your macrocells (any mix of 1's and 0's ) Both Global and PT drive work, but Global is faster and uses less product terms, so is preferred. Usually you move from using Global only when they are all committed. The fitter will choose Global, if given the choice. Write some code both ways: map CLK to a GCK1 pin, and to a IO pin , and compare the Fitter report files.(IIRC Xilinx tag these DesignName.RPT) You will need to be able to read and understand the fitter report files, but the compile/fit process is fast, so when faced with questions like this again, just try it both ways, and look at the fitter report, to see what the final nett effect is. -jgArticle: 114023
I feel sorry for anyone who does not know what "reset" means, and then tries to make sense of a halfway-modern CPLD (or FPGA) data sheet. These data sheets are really written for the knowledgeable engineer; they are not a basic tutorial. For that there are many textbooks. Our industry (CPLD and FPGA) is now over 25 years old, and we cannot let every data sheet go back to square one. That would bore the serious designers to death. I am a fan of tutorial information, and I try to sneak explanations in whenever I see a need. But there is a limit. Our data sheets will not explain the function of a master-slave D-flip-flop and its clocking and reset and preset (except saying whether it is synchronou or asynchronous, and which one overrides the other.) The fundamentals are up to schools and universities and libraries to convey. Peter Alfke, Xilinx Applications On Jan 2, 9:23 pm, Jim.Granvi...@gmail.com wrote: > highZ wrote: > > Which one, there are many datasheets for the 9500 familiy and > > for each specific one. I had a glance at all of them and couldn't > > see all these things. What exactly does 'reset' do in the first > > place, well I will see again if I can find it. ThanksCPLD data is not the most user friendly, and can give the impression > they do not chase new users. > > For Xilinx, look at both the pdf called "XC9500 In-System Programmable > CPLD Family", and also the device data sheet, and you do need to make > the odd leap. > > Fig 1 has some overview, Fig 3, Fig4 have more details. > > In fig 1, GCK is tagged as 3 lines, and Data Sheet PIN map shows GCK1, > GCK2, GCK3 Fig4 shows how those GCKx lines feed all FF's (Fig 3 calls > them Global Clocks) > > Most common Macrocell resource ( CLK, SET, RESET in 9536 case) have the > choice of Global, or Product Term drive. Pin resource also has Global > OE, but called GTSx in some places, and Global OE in others (see Fig > 10) > > GSR can map to either SET or RESET, so you can use one gobal signal, to > load one initial pattern into your macrocells (any mix of 1's and 0's > ) > > Both Global and PT drive work, but Global is faster and uses less > product terms, so is preferred. Usually you move from using Global only > when they are all committed. > > The fitter will choose Global, if given the choice. > > Write some code both ways: map CLK to a GCK1 pin, and to a IO pin , and > compare the > Fitter report files.(IIRC Xilinx tag these DesignName.RPT) > > You will need to be able to read and understand the fitter report > files, but the compile/fit process is fast, so when faced with > questions like this again, just try it both ways, and > look at the fitter report, to see what the final nett effect is. > > -jgArticle: 114024
I tried USB software update online, but failed. When connect the download cable to computer, the ISE always ask for update USB software confirmation, so I update it, but no effect result. I am afraid some protection diodes were damaged, but I am not sure. Thank you. Sun Lei. "Andreas Ehliar" <ehliar@lysator.liu.se> 写入消息新闻:enda32$2cp$1@news.lysator.liu.se... > On 2007-01-01, SunLei <iamsunlei@gmail.com> wrote: >> hi, >> >> Can anyone tell me how to repair the xilinx download cable? >> >> I have ever bought two USB cables from xilinx, they have been running >> well. But one day, when I plug the JTAG flyers in/out my evaluation >> board, >> it can not be recognized by the computer any more. The power led still be >> green, which indicate the power is on, but the software can not connect >> the >> cable. I suppose I have damaged the cable because of power on-line >> plugin. > > The power led is actually controlled by the software in the FX2 > microcontroller > in the USB cable. So the microcontroller is probably at least partially > working. > > You might have some luck if you try to force an update of the CPLD inside > the USB cable. You can find out how to do this by looking at the following > URL: > > http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&sGlobalNavPick=&sSecondaryNavPick=&getPagePath=20429 > > > /Andreas
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