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Messages from 90075

Article: 90075
Subject: Re: Xilinx dev board with high quality video?
From: "Antti Lukats" <antti@openchip.org>
Date: Tue, 4 Oct 2005 18:18:40 +0200
Links: << >>  << T >>  << A >>

"Ed McGettigan" <ed.mcgettigan@xilinx.com> schrieb im Newsbeitrag
news:4342A6AA.6020500@xilinx.com...
> Antti Lukats wrote:
> > "Ed McGettigan" <ed.mcgettigan@xilinx.com> schrieb im Newsbeitrag
> >
> >>We have improved the VGA quality on the upcoming ML405 and ML410 boards
> >>that will be released early next year.
> >>
> >>Ed
> >
> >
> > Hi Ed,
> >
> > your comment about 405 "to be released early next year" (2006) sounds
like
> > firm indication that Xilinx has serious problems with 4FX? The ML405 was
> > announced no later than jan 2005 (maybe earlier), now you are saying
that it
> > is coming sometime in 2006 ? Why announce products that are 'maybe'
coming
> > more than a year later? I would have expect ML405 to be available by
now.
> > Well if there is really an issue with 4FX that would explain why no FX
> > boards are available from Xilinx online shop. Just wondering.
> >
>
> Right now almost all of the FX20 silicon is being shipped to customers
> on a priority basis.  We do have fully functional ML405 and ML410 boards
> in house that we are now making available to our processor specialist
> FAEs and available on a limited loaner basis to customers and this will
> increase over coming months.
>
> It takes 3-4 months from this point before we can complete all of the
> rest of the material in order to turn it from early access board that
> requires a knowledgeable and trained person to use it into a general
> availability product with full manufacturing tests, documentation,
> reference designs and packaging.  Also, our internal processes has
> certain requirements that must be met before we place boards in the Xilinx
> Online Store, this should happen 1-2 months after the boards are
> available from our distributors.
>
> We haven't formally announced the ML405 and ML410, but we have shown
> them at trade shows and forums such as this as an upcoming development
> vehicle for Virtex-4. We do this so that our customers and partners can
> understand what our plans our for support collateral so that they can
> develop their own product development and test roadmaps.
>
> Ed

Ok that explains it a bit. I expected that Xilinx internally should have
ml405 boards. So the deal is that the boards are there, but are just not
going to be made available until someday in 2006.

I still dont see a point to have the ml405 being mentioned in Xilinx
publications in JAN 2005, and then ship sometime in 2006

Antti






Article: 90076
Subject: Re: Xilinx IMPACT Problem... detects 101 unknown devices
From: "Andy Peters" <Bassman59a@yahoo.com>
Date: 4 Oct 2005 10:21:05 -0700
Links: << >>  << T >>  << A >>
Subhasri krishnan wrote:
> Hi all,
> I have a custom designed hardware.... when i ran the xilinx iMPACT to
> configure the device, it ended up detecting the FPGA and a 101 unknown
> devices and then just stopped dead? has anyone ever had a similar
> problem? Please do help.

Sounds like your JTAG chain is screwed up.

-a


Article: 90077
Subject: Re: Prob in Synthesizing and Simulating large Mux
From: "Andy Peters" <Bassman59a@yahoo.com>
Date: 4 Oct 2005 10:26:40 -0700
Links: << >>  << T >>  << A >>
vssumesh wrote:
> The problem is i want that in a single chip. How can i link those huge
> control signals out of FPGA.
> But i am still wondering why the ISE is not working with my design.

Probably because your expectations are not inline with the device
capability?

You're trying to create a huge combinatorial mux.  It's not at all a
surprise that you're not meeting your timing requirements.

-a


Article: 90078
Subject: Re: Altera NIOS PIO interrupt problem
From: "GMM50" <gfm5050@gmail.com>
Date: 4 Oct 2005 10:29:21 -0700
Links: << >>  << T >>  << A >>
In the interrupt routine you need to clear the interrupt.
Check to see that you are doing that.

George


Article: 90079
Subject: Re: vhdl question
From: "Andy Peters" <Bassman59a@yahoo.com>
Date: 4 Oct 2005 10:30:37 -0700
Links: << >>  << T >>  << A >>
CMOS wrote:
> please someone let me know the effects of having "ibuf_lvcmos33" for
> each input , "obuf_lvcmos33" for each output and "bufg" in some entity
> declarations.

The ibuf and obufs tell the tools what sort of I/O structure is to be
used.  There's some detail on this in the device datasheets.

> In addition please let me know the effect of mappimg clk to clock in
> the following entity declaration.
>
> entity test is port (clock : in std_logic )
>
> end clock ;
>
> architecture arch_test of test is
>
> signal clk : std_logic ;
> clk <= clock;
>
> end architecture arch_test ;
>
> in the remainder of the definition, only "clk" is used. "clock" is
> never used. Why cant we just use "clock".

Perhaps there's a language barrier here, but I have no idea what you're
asking.  I suspect that Symon feels the same way.

-a


Article: 90080
Subject: Re: Avoiding meta stability?
From: "rhnlogic@yahoo.com" <rhnlogic@yahoo.com>
Date: 4 Oct 2005 11:18:31 -0700
Links: << >>  << T >>  << A >>
Bill wrote:
> Is the following a good way to avoid meta stability problems?
...
> At least one of the signals a,b or c could end up in a meta stabel
> condition.
...
> It then takes the median of the 3 samples.
... [VHDL stuff]
>       q <= (a and b) or (a and c) or (b and c);

You ask about metastability, which is a problem down to the
transistor and parasitic capacitance level, and then suggest some
VHDL. The actual behavior of this function is unknown until you
know what logic gates and transistors (and other physical circuit
items) your VHDL will produce after synthesis, optimization and layout,
etc. Depending on the actual realization of your majority function,
it could actually worsen the resolution time of the circuit over
that of just using a closely spaced register pair delay on the
same clock.


IMHO. YMMV.
-- 
rhn A.T nicholson d.O.t C-o-M


Article: 90081
Subject: Radiation + CoolRunner2 CPLD?
From: Bob <bob@notrealmail.com>
Date: Tue, 04 Oct 2005 14:21:45 -0400
Links: << >>  << T >>  << A >>
Hi I know that the CoolRunner2 CPLD TQ144, XC2C256-7TQ144I is not
designed to be radiation tollerent, but...

I would be interested if anyone reading this has ever radiated a CPLD
or know of some CPLD radiation data on the web.
I have google searched but found very little.
Most ics like 74hc04 parts can take about 10,000 or more rads of total
dose (Co60).
I hope to do some total dose testing this month.
Also as it has a reprogramable memory, it will be suseptible to SEU.
I wont be able to test for that.


Article: 90082
Subject: Re: Xilinx IMPACT Problem... detects 101 unknown devices
From: "Subhasri krishnan" <subhasri.krishnan@gmail.com>
Date: 4 Oct 2005 11:26:11 -0700
Links: << >>  << T >>  << A >>
please tell me what should i do now to set it right? should i read
something or should i check for something? why does it detect so many
devices when i have only one FPGA in there?
...thanks


Article: 90083
Subject: Re: Xilinx IMPACT Problem... detects 101 unknown devices
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Tue, 04 Oct 2005 11:48:41 -0700
Links: << >>  << T >>  << A >>
Subhasri krishnan wrote:
> please tell me what should i do now to set it right? should i read
> something or should i check for something? why does it detect so many
> devices when i have only one FPGA in there?
> ...thanks
> 

Scanning the JTAG chain for devices is done by reseting the TAP controllers
which loads the devices IDCODE into the TAP output register and then shifting
the register out and waiting until you get a set of 32 ones (zeros??)
indicating the end of the chain.

The most likely cause is that you have connected the TDO cable pin to
something other than the TDO pin of the last device in the chain that is
generating bad data back to the cable.

Ed

Article: 90084
Subject: Re: Xilinx IMPACT Problem... detects 101 unknown devices
From: Sean Durkin <smd@despammed.com>
Date: Tue, 04 Oct 2005 20:54:42 +0200
Links: << >>  << T >>  << A >>
Subhasri krishnan:
> please tell me what should i do now to set it right? should i read
> something or should i check for something? why does it detect so many
> devices when i have only one FPGA in there?
> ...thanks
I've had problems with too many detected devices when the cable
frequency was too high. You can change it in the cable setup settings.
If you use a Parallel Cable IV and it is properly detected, iMPACT
usually sets it to a default of 5MHz. Try lowering the frequency and see
if it gets any better.

cu,
Sean

Article: 90085
Subject: Re: Radiation + CoolRunner2 CPLD?
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 04 Oct 2005 11:55:47 -0700
Links: << >>  << T >>  << A >>
(Not Real) 'Bob',

If you want an answer to this, why haven't you already contacted our 
Xilinx Aerospace/Defense Field Applications Engineers?

We have plenty of data that we are willing to share with (Real) 'customers'.

If you need a contact, I can send their name to you once you email me 
your (Real) 'Bob' email address (and real affiliation).

It is Xilinx' interest to be sure that any aerospace/defense application 
(as well as any other) of our products uses all of the best information 
that we can provide.

Austin



Bob wrote:

> Hi I know that the CoolRunner2 CPLD TQ144, XC2C256-7TQ144I is not
> designed to be radiation tollerent, but...
> 
> I would be interested if anyone reading this has ever radiated a CPLD
> or know of some CPLD radiation data on the web.
> I have google searched but found very little.
> Most ics like 74hc04 parts can take about 10,000 or more rads of total
> dose (Co60).
> I hope to do some total dose testing this month.
> Also as it has a reprogramable memory, it will be suseptible to SEU.
> I wont be able to test for that.
> 

Article: 90086
Subject: Re: Altera why so QUIET !?
From: Ben Twijnstra <btwijnstra@gmail.com>
Date: Tue, 04 Oct 2005 21:44:54 +0200
Links: << >>  << T >>  << A >>
Hi Austin,

First of all, thanks for having been polite and courteous to everyone while
I was on paternity leave.

Second, to reiterate, I do _not_ work for Altera. I did, but I don't, and
haven't done so for several years. Thus, any reference to Altera with 'you'
when replying to my stuff is wrong.

> By the way, if Altera doesn't use "faulty bits" why do you have:
> ...
> 9 Patents (plus) for them?

Yep, and for you too. Not sure whether you actually had to use Altera's
cross-licensed patents to make EasyPath see the light of day, but it surely
must have saved on attorney fees, and $DEITY knows all of us should avoid
feeding those critters.

> Your use of laser frapped fuses to replace bad columns is identical to
> EasyPath (we just avoid the defects, the same as you).

Those patent cross-licensing deals are good, aren't they?

To be honest, I always understood that EasyPath devices were carefully
selected defective parts where the defect happened not to interfere with
the specific user's design. Thanks for clarifying this. You just can't
trust Marketing people these days.

> Meanwhile, 'EasyPath' remains easy, and now includes the standard option
> of being able to change the logic (LUTs may be reprogrammed) or change
> the IO (strength).

Just like with an FPGA... Ok, but now I'm thoroughly confused. Can you tell
me, on a hardware level, what is the difference between your standard
XC4Vxxx offering and its accompanying EasyPath device?

> Every try to ECO an ASIC?

Yep, and it's something best avoided. I FIBbed a few dies. Not fun, and I
was a lucky bastard for getting two of the bloody things to work that way.
Then it was bow-in-shame time for requesting a new mask from the boss...

Best regards,



Ben

Article: 90087
Subject: Re: Xilinx dev board with high quality video?
From: "Antonio Pasini" <removethis_pasini.a@tin.it>
Date: Tue, 4 Oct 2005 21:45:02 +0200
Links: << >>  << T >>  << A >>
>> We have improved the VGA quality on the upcoming ML405 and ML410 boards
>> that will be released early next year.
>
> I have done the "tie all grounds together" mistake myself, so I know
> how you feel.
>

Jecel, could you give me some advice on this ?  Same application; maybe 
using TI THS8133.

I feel I'm going to do the same mistake again :-)

Splitting grounds didn't always give me the best results. But I'm not so 
expert in high speed layout.





Article: 90088
Subject: Re: Radiation + CoolRunner2 CPLD?
From: Bob <bob@notrealmail.com>
Date: Tue, 04 Oct 2005 15:53:16 -0400
Links: << >>  << T >>  << A >>
Sorry I don't use (real) info on newsgroups to keep spam to a minimum.
I will email you with my (real) contact info.
However I have tried before and was told that there was no info on the
CoolRunner 2 as it is not intended for radiation and there are other
parts that are designed for radiation. However that was last year.
I have also searched on the NASA and ERRIC web sites and was
unsuccessful in finding data.


On Tue, 04 Oct 2005 11:55:47 -0700, Austin Lesea <austin@xilinx.com>
wrote:

>(Not Real) 'Bob',
>
>If you want an answer to this, why haven't you already contacted our 
>Xilinx Aerospace/Defense Field Applications Engineers?
>
>We have plenty of data that we are willing to share with (Real) 'customers'.
>
>If you need a contact, I can send their name to you once you email me 
>your (Real) 'Bob' email address (and real affiliation).
>
>It is Xilinx' interest to be sure that any aerospace/defense application 
>(as well as any other) of our products uses all of the best information 
>that we can provide.
>
>Austin
>
>
>
>Bob wrote:
>
>> Hi I know that the CoolRunner2 CPLD TQ144, XC2C256-7TQ144I is not
>> designed to be radiation tollerent, but...
>> 
>> I would be interested if anyone reading this has ever radiated a CPLD
>> or know of some CPLD radiation data on the web.
>> I have google searched but found very little.
>> Most ics like 74hc04 parts can take about 10,000 or more rads of total
>> dose (Co60).
>> I hope to do some total dose testing this month.
>> Also as it has a reprogramable memory, it will be suseptible to SEU.
>> I wont be able to test for that.
>> 


Article: 90089
Subject: ise (lin64) and debian
From: "T. Irmen" <tirmen@gmx.net_NO_SPAM>
Date: Tue, 4 Oct 2005 21:59:45 +0200
Links: << >>  << T >>  << A >>
Hi,

i spend one week to figure out how this combination could work - with no 
success.

currently we install the rh ws 3.0  into a separate directory ; chroot to it 
and start the software, that works

I think something with the X libraries doensīt work with current amd 64 port 
of debian, ise produces a segmentation fault at startup.

does anyone have some ideas / suggestions?

regards,
thomas

BTW: I know that Xilinx says:RH WS3.0 is the ONLY supported distribution. 
System is dual opteron (2600MHz), 8GB mem, SATA etc... I īd like to use 
debian for a lot of reasons.... 



Article: 90090
Subject: Re: Avoiding meta stability?
From: "Peter Alfke" <peter@xilinx.com>
Date: 4 Oct 2005 13:21:55 -0700
Links: << >>  << T >>  << A >>
"Metastability" is a popular word to scare inexperienced designers.

If you run a 1.8 MHz clock (even with a similar asynchronous data
rate), your chance of having a 3 ns extra metastable delay is once per
billion years (at 24 MHz it would be only 5 million years).
For every additional ns of acceptable settling time, the
mean-time-between-failure increases at least a million times. (see
XAPP094 on the Xilinx website)
The probability of your flip-flop failing during the life of this
universe (even if you do nothing) with more than 10 ns of
unaccounted-for delay is so minute it is practically zero.
There are more important things to worry about, forget metastability...
Peter Alfke, Xilinx Applications (who actually has created quantitative
data about metastability)


Article: 90091
Subject: Re: Xilinx IMPACT Problem... detects 101 unknown devices
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Tue, 4 Oct 2005 13:24:19 -0700
Links: << >>  << T >>  << A >>
I have had some problems similar to that in that I would get a strange 
number
of devices rather than the six I have on the board.  The Xilinx people 
pointed
out the signal integrity issues I designed.  Mostly the TCK line was the 
culprit.
How is your TCK line routed? Is there a series resistance? Or perhaps you
put an end Thevenin termination at the end? How long are the lines?

> Hi all,
> I have a custom designed hardware.... when i ran the xilinx iMPACT to
> configure the device, it ended up detecting the FPGA and a 101 unknown
> devices and then just stopped dead? has anyone ever had a similar
> problem? Please do help.
> Thanks
> 



Article: 90092
Subject: How to make XST understand to pack mux(A,B,A+B) in a single level
From: Sylvain Munaut <com.246tNt@tnt>
Date: Tue, 04 Oct 2005 22:33:40 +0200
Links: << >>  << T >>  << A >>
Hello,

Here is my problem :

I want to have a combinatorial block with 4 inputs :
 - 2 vectors A and B
 - 2 control signal 'passthru' & 'sel'

that produces either A+B (if passthru=0),
A (if sel=0) or B (if sel=1). And all that in a
signle layer of logic.


In VHDL:

process(a,b,passthru,sel)
begin
 if passthru = '0' then
  q <= a + b;
 else
  if sel = '0' then
   q <= a;
  else
   q <= b;
  end if;
 end if;
end process;

I know it's possible :
 - using a(n), b(n), not passthru, sel as F1 F2 F3 F4
 - using MULT_AND to stop carry propagation

and I could do it for just mux(A, A+B) by describing it as

bp <= b when passthru='0' else (others=>'0');
q <= a + bp;

(and that must be a + bp, when putting bp + a that doesnt work, it
produces two level!)


Does any one know the good 'template' to use ?


	Sylvain

Article: 90093
Subject: EasyPath, demystified
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 04 Oct 2005 13:51:09 -0700
Links: << >>  << T >>  << A >>
Ben,

See below,

-snip-

> First of all, thanks for having been polite and courteous to everyone while
> I was on paternity leave.

Congratulations.

> Second, to reiterate, I do _not_ work for Altera. I did, but I don't, and
> haven't done so for several years. Thus, any reference to Altera with 'you'
> when replying to my stuff is wrong.

I will remember that in future.

>>By the way, if Altera doesn't use "faulty bits" why do you have:
>>...
>>9 Patents (plus) for them?
> 
> Yep, and for you too.

We do not use any laser, or other non-volatile methods to improve, or 
increase die yield (yet).

  Not sure whether you actually had to use Altera's
> cross-licensed patents to make EasyPath see the light of day,

Nope.

  but it surely
> must have saved on attorney fees, and $DEITY knows all of us should avoid
> feeding those critters.

Altera's patent portfolio is quite respectable.  So is ours.  Due to the 
last legal settlement, I can not comment on any of it.

>>Your use of laser frapped fuses to replace bad columns is identical to
>>EasyPath (we just avoid the defects, the same as you).
>  
> Those patent cross-licensing deals are good, aren't they?

Again, no comment.  I am all for avoiding those 'critters' as well...

> To be honest, I always understood that EasyPath devices were carefully
> selected defective parts where the defect happened not to interfere with
> the specific user's design. Thanks for clarifying this. You just can't
> trust Marketing people these days. 

Who at Xilinx every represented EasyPath as any other than what you 
described above?  I understand Altera tells everyone EasyPath are 
"defective" parts.  They also fail to mention that ALL of their parts 
use redundancy to repair defective portions of their FPGAs.  At least 
our non-EasyPath FPGAs really have no defects whatsoever.

EasyPath is tested to the customer's pattern, and represents an 
extremely high test coverage for their specific application.

One advantage of EasyPath is that our method of testing provides a much 
higher quality part than ASIC testing is capable of.

>>Meanwhile, 'EasyPath' remains easy, and now includes the standard option
>>of being able to change the logic (LUTs may be reprogrammed) or change
>>the IO (strength).
>  
> Just like with an FPGA... Ok, but now I'm thoroughly confused. Can you tell
> me, on a hardware level, what is the difference between your standard
> XC4Vxxx offering and its accompanying EasyPath device?

Absolutely nothing at all.

No difference (in silicon).

The EasyPath component is just tested (and marked) for a specific 
bitstream (or two).

A customer can have a bistream for in-house manufacturing test, and 
another one for the application, or any two of their choice as an option.

Try that with an ASIC sometimes!

>>Every try to ECO an ASIC?
> 
> Yep, and it's something best avoided. I FIBbed a few dies. Not fun, and I
> was a lucky bastard for getting two of the bloody things to work that way.
> Then it was bow-in-shame time for requesting a new mask from the boss...

Then you can imagine what fun it is to do backside fib'ing of flip chip 
die.  But, one advantage of "hardtocopy" is that Altera has to do the 
fib'ing when something doesn't work (not the customer).

We just change bits and the customer keeps shipping, uninterrupted.

Article: 90094
Subject: Re: Radiation + CoolRunner2 CPLD?
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 04 Oct 2005 13:55:06 -0700
Links: << >>  << T >>  << A >>
(Real) Bob,

Thanks for sending to me directly.

There is an aerospace/defense FAE who will contact you shortly to 
provide you with what you need (if we have what you need).

I know we had Coolrunner II in the LANSCE facility in May of this year, 
as it was my group that set it up, and was there for the testing.

(surreal) Austin

Bob wrote:

> Sorry I don't use (real) info on newsgroups to keep spam to a minimum.
> I will email you with my (real) contact info.
> However I have tried before and was told that there was no info on the
> CoolRunner 2 as it is not intended for radiation and there are other
> parts that are designed for radiation. However that was last year.
> I have also searched on the NASA and ERRIC web sites and was
> unsuccessful in finding data.
> 
> 
> On Tue, 04 Oct 2005 11:55:47 -0700, Austin Lesea <austin@xilinx.com>
> wrote:
> 
> 
>>(Not Real) 'Bob',
>>
>>If you want an answer to this, why haven't you already contacted our 
>>Xilinx Aerospace/Defense Field Applications Engineers?
>>
>>We have plenty of data that we are willing to share with (Real) 'customers'.
>>
>>If you need a contact, I can send their name to you once you email me 
>>your (Real) 'Bob' email address (and real affiliation).
>>
>>It is Xilinx' interest to be sure that any aerospace/defense application 
>>(as well as any other) of our products uses all of the best information 
>>that we can provide.
>>
>>Austin
>>
>>
>>
>>Bob wrote:
>>
>>
>>>Hi I know that the CoolRunner2 CPLD TQ144, XC2C256-7TQ144I is not
>>>designed to be radiation tollerent, but...
>>>
>>>I would be interested if anyone reading this has ever radiated a CPLD
>>>or know of some CPLD radiation data on the web.
>>>I have google searched but found very little.
>>>Most ics like 74hc04 parts can take about 10,000 or more rads of total
>>>dose (Co60).
>>>I hope to do some total dose testing this month.
>>>Also as it has a reprogramable memory, it will be suseptible to SEU.
>>>I wont be able to test for that.
>>>
> 
> 

Article: 90095
Subject: Re: How to make XST understand to pack mux(A,B,A+B) in a single level ?
From: "John_H" <johnhandwork@mail.com>
Date: Tue, 04 Oct 2005 21:14:03 GMT
Links: << >>  << T >>  << A >>
In verilog I'd try to use:
  q <= (~sel | passthru ? A : 0) + (sel | passthru ? B : 0);

The trouble is the MULT_AND doesn't like the OR functions for the "enable."
If the sel and passthru are redefined to the control terms above, the single
layer of logic for A and B would work.  If you need sel, passthru, A, and B
to all be single levels of logic, you can't do it because the MULT_AND wants
two inputs: one of your vectors and one control term.

q <= (useA ? A : 0) + (useB ? B : 0);  // 1 level



"Sylvain Munaut" <com.246tNt@tnt> wrote in message
news:4342e651$0$25209$ba620e4c@news.skynet.be...
> Hello,
>
> Here is my problem :
>
> I want to have a combinatorial block with 4 inputs :
>  - 2 vectors A and B
>  - 2 control signal 'passthru' & 'sel'
>
> that produces either A+B (if passthru=0),
> A (if sel=0) or B (if sel=1). And all that in a
> signle layer of logic.
>
>
> In VHDL:
>
> process(a,b,passthru,sel)
> begin
>  if passthru = '0' then
>   q <= a + b;
>  else
>   if sel = '0' then
>    q <= a;
>   else
>    q <= b;
>   end if;
>  end if;
> end process;
>
> I know it's possible :
>  - using a(n), b(n), not passthru, sel as F1 F2 F3 F4
>  - using MULT_AND to stop carry propagation
>
> and I could do it for just mux(A, A+B) by describing it as
>
> bp <= b when passthru='0' else (others=>'0');
> q <= a + bp;
>
> (and that must be a + bp, when putting bp + a that doesnt work, it
> produces two level!)
>
>
> Does any one know the good 'template' to use ?
>
>
> Sylvain



Article: 90096
Subject: Re: How to make XST understand to pack mux(A,B,A+B) in a single level
From: Sylvain Munaut <com.246tNt@tnt>
Date: Tue, 04 Oct 2005 23:34:20 +0200
Links: << >>  << T >>  << A >>
John_H wrote:
> In verilog I'd try to use:
>   q <= (~sel | passthru ? A : 0) + (sel | passthru ? B : 0);
> 
> The trouble is the MULT_AND doesn't like the OR functions for the "enable."
> If the sel and passthru are redefined to the control terms above, the single
> layer of logic for A and B would work.  If you need sel, passthru, A, and B
> to all be single levels of logic, you can't do it because the MULT_AND wants
> two inputs: one of your vectors and one control term.
> 
> q <= (useA ? A : 0) + (useB ? B : 0);  // 1 level
> 

Actually, I don't see how to fit your representation (useA useB) into a
single level ...


What I wanted the tool to do is : (pt_n is not passthru)

.                            cout
.                            _|_
.                        ,--/___\ CYMUX
.                        |   | |
.                ______  |   | |
. a(b) ---------|      | |   | |     ____  XORCY
. b(n) ------x--| LUT4 |-x----------\\   \_____
. pt_n ---x--|--|      |     | x----//___/
. sel  ---|--|--|______|     | |
.         |  |              /  |
.         |  |       __    /   |
.         |  '------|  \ _/    cin
.         '---------|__/
.                  MULT_AND


	Sylvain

Article: 90097
Subject: Re: Avoiding meta stability?
From: "rhnlogic@yahoo.com" <rhnlogic@yahoo.com>
Date: 4 Oct 2005 14:36:53 -0700
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> "Metastability" is a popular word to scare inexperienced designers.
>
> If you run a 1.8 MHz clock (even with a similar asynchronous data
> rate), your chance of having a 3 ns extra metastable delay is once
> per billion years (at 24 MHz it would be only 5 million years).
> For every additional ns of acceptable settling time, the
> mean-time-between-failure increases at least a million times.

This certainly depends on the logic family, which the OP didn't
specify.  I have seen IO equipment, constructed with older slower
logic families, fail due to improper synchronization at clock rates
of much less than 24 MHz.  Even today, with fast submicron CMOS,
you can still create reliability problems with worse case register
placements or interconnect routing.


IMHO. YMMV.
-- 
rhn A.T nicholson d.O.t C-o-M


Article: 90098
Subject: Re: EasyPath, demystified
From: Adam Megacz <megacz@cs.berkeley.edu>
Date: Tue, 04 Oct 2005 14:37:30 -0700
Links: << >>  << T >>  << A >>

Austin Lesea <austin@xilinx.com> writes:
>> To be honest, I always understood that EasyPath devices were carefully
>> selected defective parts where the defect happened not to interfere with
>> the specific user's design.

This was my understanding as well.  I think most people who take the
time to read about it come to this conclusion.

> Who at Xilinx every represented EasyPath as any other than what you
> described above?

Well, to be honest, going from the marketing materials alone, I wasn't
quite sure if it was a new flavor of peanut butter or a boiled cabbage
accelerator.  But Xilinx's marketing department isn't really any worse
than any other silicon valley company in that regard. ;)

> I understand Altera tells everyone EasyPath are "defective" parts.
> They also fail to mention that ALL of their parts use redundancy to
> repair defective portions of their FPGAs.

Interesting, I didn't know that.

> At least our non-EasyPath FPGAs really have no defects whatsoever.

Er, really?  I thought you had to pay extra for the 100% tested ones.
Does Xilinx really test every net on every chip for (say) stuck-at
faults before shipping?

  - a

-- 
PGP/GPG: 5C9F F366 C9CF 2145 E770  B1B8 EFB1 462D A146 C380

Article: 90099
Subject: Re: EasyPath, demystified
From: Ben Twijnstra <btwijnstra@gmail.com>
Date: Tue, 04 Oct 2005 23:53:22 +0200
Links: << >>  << T >>  << A >>
Hi Austin,

> Who at Xilinx every represented EasyPath as any other than what you
> described above? 

I unfortunately don't get to talk to Xilinx people very often nowadays,
which is a bit of a pity because I used to get along well with the whole
Xilinx FAE team in Belgium - including Marc Defossez.

> I understand Altera tells everyone EasyPath are "defective" parts.

Well, they were presented to me as 'possibly partially defective parts, but
happening to work OK with the specific customer design'.

> They also fail to mention that ALL of their parts 
> use redundancy to repair defective portions of their FPGAs. 

Not quite true. When the EP20K1500E and its slightly less bulky brethren
came out Altera quite proudly presented the redundancy as a yield
improvement technique. The redundancy 'feature' was also present in Stratix
customer presentations. I don't remember about Stratix II presentations
though.

> At least our non-EasyPath FPGAs really have no defects whatsoever.

Oh, once Altera's repair department is done with a die, so does a Stratix
(II), which is 100% tested as well.

> EasyPath is tested to the customer's pattern, and represents an
> extremely high test coverage for their specific application.

So, can I then summarize that EasyPath is basically a standard Virtex II/4
but with less time on the testbed (only the cells and routing used by the
customer are tested) in order to reduce cost?

Best regards,


Ben




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