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Messages from 75850

Article: 75850
Subject: Re: Spartan3 Block RAM from WebPACK
From: cs_posting@hotmail.com (Chris Stratton)
Date: 16 Nov 2004 20:25:08 -0800
Links: << >>  << T >>  << A >>
hmurray@suespammers.org (Hal Murray) wrote in message 

> The suggestion of using data2mem is one of the ways I was looking for.
> (It doesn't support the parity bit.) 

I knew there must be some good reason why I didn't surrender to the
temptation to stretch my 32 bit processor to a 36 bit instruction
word...

Quick and dirty suggestion: disable parity checking in the development
version and use data2mem to shorten the process of developoing
preliminary code.  Then at some point as the project approaches
finalization, re-enable parity and put the code in there in synthesis
with the INITP's to set the parity bits.

Could one figure out how to write a data2mem replacement that would
load them?
Is sythesis repeatable enough that you could map the parity bit
locations by changing one parity bit location in the HDL code's
INITP's and diff'ing the bitstreams?

Chris

Article: 75851
Subject: ISO Free cores repository
From: ghazan.haider@gmail.com (Ghazan Haider)
Date: 16 Nov 2004 21:30:34 -0800
Links: << >>  << T >>  << A >>
I have generally kept away from fpga technologies because I thought
the use of any core requires a purchase. I discovered recently the
8051 core is available for free.

What other cores are available for free or noncommercial use? I have
DSPs, 32-bit MCUs, dacs, ethernet and atm controllers etc in mind...

Article: 75852
Subject: Re: ISO Free cores repository
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Wed, 17 Nov 2004 15:33:39 +1000
Links: << >>  << T >>  << A >>
Ghazan Haider wrote:
> I have generally kept away from fpga technologies because I thought
> the use of any core requires a purchase. I discovered recently the
> 8051 core is available for free.
> 
> What other cores are available for free or noncommercial use? I have
> DSPs, 32-bit MCUs, dacs, ethernet and atm controllers etc in mind...

www.opencores.org



Article: 75853
Subject: Re: ISO Free cores repository
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Wed, 17 Nov 2004 18:07:50 +1100
Links: << >>  << T >>  << A >>
On Wed, 17 Nov 2004 15:33:39 +1000, John Williams
<jwilliams@itee.uq.edu.au> wrote:

>Ghazan Haider wrote:
>> I have generally kept away from fpga technologies because I thought
>> the use of any core requires a purchase. I discovered recently the
>> 8051 core is available for free.
>> 
>> What other cores are available for free or noncommercial use? I have
>> DSPs, 32-bit MCUs, dacs, ethernet and atm controllers etc in mind...
>
>www.opencores.org

A lot of open cores *aren't* on opencores.  Opencollector attempts to
list them all:
http://www.opencollector.org/summary.php#Designs

Regards,
Allan

Article: 75854
Subject: Re: ISO Free cores repository
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Wed, 17 Nov 2004 17:09:43 +1000
Links: << >>  << T >>  << A >>
Allan Herriman wrote:

> A lot of open cores *aren't* on opencores.  Opencollector attempts to
> list them all:
> http://www.opencollector.org/summary.php#Designs

Ah yes - good catch.

John

Article: 75855
Subject: Re: ModelSim
From: "Alan Fitch" <alan.fitch@doulos.com>
Date: Wed, 17 Nov 2004 09:32:18 -0000
Links: << >>  << T >>  << A >>
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message
news:10pl8guj9m2qgb4@corp.supernews.com...
> I launch Modelsim from the Xilinx IDE.  I would like it run all the
way
> through, to a wait; statement in the testbench. How do I do that?
In fact,
> since my testbed outputs to text files, I would rather not see the
ModelSim
> workings at all, and would rather just stay in the Xilinx IDE.
>
> Brad Smallridge
>
>
>

You can create a custom do file and tell ISE about that. Alternatively
if you just want to run to the end, replace the option that says "run
timevalue"
with "run -all". You can just put "run -all" in the dialogue box in
the
properties for the process in ISE that launches Modelsim,

regards
Alan


-- 
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223                          mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573                           Web:
http://www.doulos.com

The contents of this message may contain personal views which are not
the
views of Doulos Ltd., unless specifically stated.




Article: 75856
Subject: Re: Suggestion for Xilinx parallel port cable replacement.
From: Laurent Gauch <laurent.gauch@DELETEALLCAPSamontec.com>
Date: Wed, 17 Nov 2004 11:55:01 +0100
Links: << >>  << T >>  << A >>
Petter Gustad wrote:
> tony.p.lee@gmail.com (T Lee) writes:
> 
> 
>>How about creating a ethernet to jtag cable replacement?
> 
> 
> I've made my own Ethernet based programmer. Works on virtually any OS
> and does not require a device driver. Also works with Xilinx Impact
> and Altera Quartus.
> 
> Petter

Hi Petter,

Could you please tell me how works the interface with Impact and Quartus?

Are there any application notes explaining the how-to-do ?

Article: 75857
Subject: Re: Digital LP filter in multiplier free FPGA
From: "markp" <map.nospam@f2s.com>
Date: Wed, 17 Nov 2004 11:04:26 -0000
Links: << >>  << T >>  << A >>
Thanks Henk, this seems a nice tool. I'll have a play!

Mark.

"mtx" <mtx@xs4all.nl> wrote in message
news:4198a8f9$0$176$e4fe514c@dreader4.news.xs4all.nl...
> Dear Mark,
> Seems to be a half-band filter (half of the Nyquist freq of 6 MHz) so,
when
> you use a FIR filter you can leave out half of the taps. The Xilinx core
> generator can generate a nice filter for you. For the tap values use some
> FIR design tool, look at www.mediatronix.com/tools for a free one, it can
> export to Xilinx .coe files.
> Regards,
> Henk van Kampen
> www.mediatronix.com
>
> "markp" <map.nospam@f2s.com> wrote in message
> news:2vn75sF2o7m4kU1@uni-berlin.de...
> > Hi All,
> >
> > I need to implement a low pass digital filter on 12 bit ADC data in a
> > Spatan
> > IIE device, but I'd like it to be multiplier free - in other words just
> > use
> > adders and bit shifting for the coefficients. The sample rate is 12Mhz
and
> > I
> > need a sharp cut-off at around 3MHz. Does anyone know of a simple design
> > (IIR?) to do this, or a website/tutorial to give me some pointers? I've
> > seen
> > several websites with coefficient calculators, there are always a few
> > coefficients that can't be easily calculated with bit shifting and
adding.
> >
> > Thanks!
> >
> > Mark.
> >
> >
>
>



Article: 75858
Subject: Setup violation warning with constant signal in Modelsim/Webpack
From: "Ken" <aeu96186@NOSPAM.yahoo.co.uk>
Date: Wed, 17 Nov 2004 14:52:15 +0100
Links: << >>  << T >>  << A >>
Hi folks,


Xilinx ISE Webpack 6.3.02i (XST VHDL)
Modelsim Starter 5.8c
160MHz clock

During a post par back annotated simulation I am getting the following 
warnings occuring about 40/50 times (i.e. not all the time and they are 
occuring after the reset phase is over):

# ** Warning: /X_SFF SETUP High VIOLATION ON CE WITH RESPECT TO CLK;
#   Expected := 0.095 ns; Observed := 0.088 ns; At : 111.338 ns
#    Time: 111338 ps  Iteration: 2  Instance: 
/filtertestbench/uut/dualportcyclicrambuffer_state0_ffd3_424
# ** Warning: /X_SFF SETUP  Low VIOLATION ON CE WITH RESPECT TO CLK;
#   Expected := 0.095 ns; Observed := 0.088 ns; At : 117.588 ns
#    Time: 117588 ps  Iteration: 2  Instance: 
/filtertestbench/uut/dualportcyclicrambuffer_state0_ffd3_424

The strange thing is that the CE signal in question is hard-coded to 1 in 
the port mapping like this:

DualPortCyclicRAMBuffer : DualPortCyclicBuffer

 generic map (
  DATA_DEPTH => FILTER_LENGTH
  )

 port map (

  clk => clk,
  ce => '1',
  reset => reset,
  rfs => rfs,
  nsi => nsi,
  dataIn => x,
  dataOut1stHalf => cyclicRAMDataOut,
  dataOut2ndHalf => cyclicRAMDataOutDualPort,
  finalSample => cyclicRAMFinalSample,
  sor => cyclicRAMSOR
  );


So, how can there be setup violations on a signal that doesn't change?

Can I just ignore this?

Many thanks for your time and insight.

Cheers,

Ken







Article: 75859
Subject: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Wed, 17 Nov 2004 14:10:11 +0000
Links: << >>  << T >>  << A >>
On Tue, 16 Nov 2004 16:57:01 -0800, "Brad Smallridge"
<bradsmallridge@dslextreme.com> wrote:

>I would eventually like to be able to read a BMP file directly into the 
>ModelSim simulator.  I understand now with VHDL the only file you can read 
>are text files.  Is there a way to read in binary data in another way, 
>perhaps by using Verilog?

VHDL certainly can read binary data; Mike Treseler's example is
excellent, and starting from it made reading my binary data very easy.

If you can constrain the BMP files you want to read to a specific format
(24bits/pixel is probably simplest) go for it, otherwise you may have to
interpret many different formats, which is a bit more work...

- Brian


Article: 75860
Subject: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
From: JFrensch@HarmanBecker.com (Jochen Frensch)
Date: 17 Nov 2004 07:50:54 -0800
Links: << >>  << T >>  << A >>
Mike Treseler <mike_treseler@comcast.net> wrote in message news:<df6dnalj_9evUQfcRVn-pw@comcast.com>...

> Here's one possibility:
> http://groups.google.com/groups?q=vhdl+char_array
> 
>       -- Mike Treseler

VERY good example !!!

will help me a lot !!

just one remark: shouldn't it be 

   function spew(i_arg : integer) return char_array is
      variable result : char_array(0 to i_arg-1);
      variable index  : char_index;
   begin
       for i in 0 to i_arg-1 loop
         index     := i mod (char_index'right + 1); -- <<<<<<<<<<  ??
         result(i) := character'val(index);
      end loop;
      return result;
   end function spew;

to get full 8-Bit numbers ?

** Jochen Frensch **

Article: 75861
Subject: Re: Setup violation warning with constant signal in Modelsim/Webpack
From: "Andrea Sabatini" <andrea@dapdesign_N_O_S_P_A_M_.com>
Date: Wed, 17 Nov 2004 17:02:17 +0100
Links: << >>  << T >>  << A >>
hi,

did you check in the par vhd file that the ce input of the instance:

/filtertestbench/uut/dualportcyclicrambuffer_state0_ffd3_424

is stuck to 1? did you see that signal stuck to 1 during simulation at the
time indicated in the warnings (111.338 ns and 117.588) ?

andrea



Article: 75862
Subject: Re: video camera interface to FPGA
From: gabor@alacron.com (Gabor Szakacs)
Date: 17 Nov 2004 08:22:38 -0800
Links: << >>  << T >>  << A >>
htj@es.lth.se (Hongtu) wrote in message news:<842b837e.0411161440.5f8cc802@posting.google.com>...
> Thank you guys! that is very helpful for me. 
> I just wanna ask one last question: After processing the input video
> stream, I got a binary outputs to be displayed in a either a monitor
> or sent back to a computer for real-time supervision, any
> recommendations on how to implement this?
> 
Again this depends on the video resolution and update rates.  If
you have a high-speed data path to the computer, it's fairly easy
to get the data on the computer monitor (just a small matter of
software).  In fact if you had something like a bus-mastering PCI
interface you can write the image directly to the screen for most
VGA displays.  If your device is located away from the computer
I'd look into just a standard network interface like Ethernet
as long as it gives you the bandwidth you need.

For a local monitor (no computer involved) you can use a RAM/DAC
if you want to get fancy.  I've used the ADV7160 / ADV7162 (Analog
Devices) with good results on PC-style analog video monitors.  Depending
on image quality and pixel rate there may be much simpler and cheaper
solutions for analog RGB video.

If you want to use a TV-style monitor look into the Philips SAA7125
video encoder.  It's small and relatively easy to use, but you will
need to set a bunch of internal I2C registers to set it up.

Finally if this is a one-up project (research?) I'd suggest re-
creating standard camera video like you take in and then using
on off-the-shelf framegrabber card for computer connection and
video display.

> 
> BR, Hongtu

Article: 75863
Subject: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Wed, 17 Nov 2004 08:36:36 -0800
Links: << >>  << T >>  << A >>
Looks promising.
How do I generate the test file char_file.bin ? 



Article: 75864
Subject: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Wed, 17 Nov 2004 08:48:14 -0800
Links: << >>  << T >>  << A >>
Belay that silly question. Duh.
The program generates char_file.bin

> How do I generate the test file char_file.bin ?



Article: 75865
Subject: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
From: Mike Treseler <mike_treseler@comcast.net>
Date: Wed, 17 Nov 2004 09:28:34 -0800
Links: << >>  << T >>  << A >>
Jochen Frensch wrote:

>>Here's one possibility:
>>http://groups.google.com/groups?q=vhdl+char_array
>>
>>      -- Mike Treseler
> 
> VERY good example !!!
> 
> will help me a lot !!

Thanks, I'm happy to hear about it.

> just one remark: shouldn't it be 
> 
>    function spew(i_arg : integer) return char_array is
>       variable result : char_array(0 to i_arg-1);
>       variable index  : char_index;
>    begin
>        for i in 0 to i_arg-1 loop
>          index     := i mod (char_index'right + 1); -- <<<<<<<<<<  ??
>          result(i) := character'val(index);
>       end loop;
>       return result;
>    end function spew;
> 
> to get full 8-Bit numbers ?

To cover all 256 characters, yes!
Notice there is a seam in my hex file
between FE and 100, and I think you have
the fix. Try it and see.

         -- Mike Treseler

Article: 75866
Subject: Re: 5V inputs with series resistor on Spartan-3
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 17 Nov 2004 09:43:17 -0800
Links: << >>  << T >>  << A >>
Eric,

Spartan 3 has clamp diodes that always prevent the voltage on the pin 
from being more than a diode drop above Vcco (or below ground).

So, if Vcco is 3.3V, and the diode drop is ~ 0.5V at the current thru 
the 270 ohms, then the max V is 3.8V, well below the abs max limit of 
4.05V in the data sheet.

But, take care, as if you have Vcco = 3.45V, then you are getting 
uncomfortably close to the 4.05V abs max limit.

As it turns out, the characterization work we have done has shown that 
the nmos gate is very robust, and the pmos gate is the one limited to 
the no greater than 4.05V restriction (in .25u IO used by V2P, S3, and 
V4).  In order to stress the pmos gate, you would have to have a voltage 
below ground, AND a high Vcco!  So for the 5V and a resistor case, even 
if you had 3.45V Vcco, it still does not represent a reliability issue 
with the nmos gate oxide.

I have stated here before, that the pmos stress >4.05V results in a 
leakage of ~ 10uA over time, and a weakening of the pmos output 
transistor by as much as 10%.  This is not affected or accelerated by 
temperature.  If the IO is always used as an input, then you don't care 
about the driver becoming weaker over time.  If the input is thru a 270 
ohm resistor from a 5V CMOS output, you probably also don't care about 
10uA of input leakage.  But, the leakage is an indication of gate oxide 
damage of the pmos pullup, so we can not recommend operating it under 
these conditions.

Austin

Eric Smith wrote:
> I was looking for information on driving Spartan-3 inputs from 5V CMOS
> signals using series resistors, and eventually found answer record 19146
> which covers this in detail.  Executive summary: for LVCMOS33 input with
> Vcco min/max of 3.0/3.45V and 5V+/-10% CMOS signal, use minimum 263 ohms
> series resistance.  That answers my question.  But...
> 
> Before I found that, I found XAPP 429, on interfacing 5V to
> CoolRunner-II CPLDs.  On page 3, it says "A simple series terminating
> resistor is NOT an acceptable solution to interfacing 5V signals.  In
> this situation, the current applied to the pin is not the offending
> factor.  Since the cumulative damage to the gate oxide impedance is
> caused by voltage, merely limiting the input current does not protect
> the oxide."
> 
> Why is the Spartan-3 different than the CoolRunner-II in this regard?
> XAPP 429 goes into great detail on the gate oxide, but doesn't make any
> mention of clamp diodes in the input pad structures.  Did the CR-II
> really not have clamp diodes on the inputs?  Or were the CR-II clamp
> diodes rated for significantly less current than those of the S-3?
> 
> Without some understanding of why such different advice is given for the
> CR-II and S-3, I'm reluctant to use the series resistor approach.
> 
> Eric
> 

Article: 75867
Subject: Re: 5V inputs with series resistor on Spartan-3
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 17 Nov 2004 11:57:32 -0800
Links: << >>  << T >>  << A >>
Austin Lesea <austin@xilinx.com> writes:
> Spartan 3 has clamp diodes that always prevent the voltage on the pin
> from being more than a diode drop above Vcco (or below ground).

And CoolRunner-II do not?

Article: 75868
Subject: Re: Setup violation warning with constant signal in Modelsim/Webpack
From: "Jim Wu" <nospam@nospam.com>
Date: Wed, 17 Nov 2004 15:38:40 -0500
Links: << >>  << T >>  << A >>
The CE pin of the instance
/filtertestbench/uut/dualportcyclicrambuffer_state0_ffd3_424 may not be the
same "ce" connected to your component instantiation.

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips


"Ken" <aeu96186@NOSPAM.yahoo.co.uk> wrote in message
news:cnfl2g$nam$01$1@news.t-online.com...
> Hi folks,
>
>
> Xilinx ISE Webpack 6.3.02i (XST VHDL)
> Modelsim Starter 5.8c
> 160MHz clock
>
> During a post par back annotated simulation I am getting the following
> warnings occuring about 40/50 times (i.e. not all the time and they are
> occuring after the reset phase is over):
>
> # ** Warning: /X_SFF SETUP High VIOLATION ON CE WITH RESPECT TO CLK;
> #   Expected := 0.095 ns; Observed := 0.088 ns; At : 111.338 ns
> #    Time: 111338 ps  Iteration: 2  Instance:
> /filtertestbench/uut/dualportcyclicrambuffer_state0_ffd3_424
> # ** Warning: /X_SFF SETUP  Low VIOLATION ON CE WITH RESPECT TO CLK;
> #   Expected := 0.095 ns; Observed := 0.088 ns; At : 117.588 ns
> #    Time: 117588 ps  Iteration: 2  Instance:
> /filtertestbench/uut/dualportcyclicrambuffer_state0_ffd3_424
>
> The strange thing is that the CE signal in question is hard-coded to 1 in
> the port mapping like this:
>
> DualPortCyclicRAMBuffer : DualPortCyclicBuffer
>
>  generic map (
>   DATA_DEPTH => FILTER_LENGTH
>   )
>
>  port map (
>
>   clk => clk,
>   ce => '1',
>   reset => reset,
>   rfs => rfs,
>   nsi => nsi,
>   dataIn => x,
>   dataOut1stHalf => cyclicRAMDataOut,
>   dataOut2ndHalf => cyclicRAMDataOutDualPort,
>   finalSample => cyclicRAMFinalSample,
>   sor => cyclicRAMSOR
>   );
>
>
> So, how can there be setup violations on a signal that doesn't change?
>
> Can I just ignore this?
>
> Many thanks for your time and insight.
>
> Cheers,
>
> Ken
>
>
>
>
>
>



Article: 75869
Subject: Newbie FPGA Qs
From: gsletch@yahoo.com (Greg)
Date: 17 Nov 2004 12:49:30 -0800
Links: << >>  << T >>  << A >>
First of all, I am a newbie to FPGAs and trying to learn the tools...I
have had coursework in Verilog as it applies to ASICs, etc. I have an
Insight Electronics FPGA Spartan II(100,000 gates) prototype
board...it is a couple of years old. I am using the latest free Xilinx
WebPack tools, etc.

The board came with the simple counter design already loaded and
ready. You just put power to it and it starts counting. I don't have
access to the Verilog code. I want to take the design, make a small
change and reconfigure just to get a handle on the flow, etc. Is it
possible to extract the .bit file from the ISP PROM and generate the
source code via WebPack tools?

It appears that it can be configured by master serial mode via an ISP
PROM. I have the JTAG header on the board and the JTAG cable. Do I
just plug the JTAG cable into the PC's parallel port and the other end
on the board, power-up the board and bring up the WebPack tools? The
board has a switch that toggles the FPGA between "normal" and
"configuration" modes. Without the JTAG plugged in, the switch just
seems to reset the counter...

Thanks for any help....

Article: 75870
Subject: Re: Suggestion for Xilinx parallel port cable replacement.
From: tony.p.lee@gmail.com (T Lee)
Date: 17 Nov 2004 12:58:38 -0800
Links: << >>  << T >>  << A >>
Laurent Gauch <laurent.gauch@DELETEALLCAPSamontec.com> wrote in message news:<419B2E05.2080205@DELETEALLCAPSamontec.com>...
> Petter Gustad wrote:
> > tony.p.lee@gmail.com (T Lee) writes:
> > 
> > 
> >>How about creating a ethernet to jtag cable replacement?
> > 
> > 
> > I've made my own Ethernet based programmer. Works on virtually any OS
> > and does not require a device driver. Also works with Xilinx Impact
> > and Altera Quartus.
> > 
> > Petter
> 
> Hi Petter,
> 
> Could you please tell me how works the interface with Impact and Quartus?
> 
> Are there any application notes explaining the how-to-do ?

Yes, Petter,  I would love to know how to do this too.

BTW, does it work with xmd?

-Tony

Article: 75871
Subject: Re: Suggestion for Xilinx parallel port cable replacement.
From: tony.p.lee@gmail.com (T Lee)
Date: 17 Nov 2004 13:04:44 -0800
Links: << >>  << T >>  << A >>
"Amontec, Larry" <laurent.gauch@amon-tec.com> wrote in message news:<419A7079.8090702@amon-tec.com>...
> T Lee wrote:
> > How about creating a ethernet to jtag cable replacement?
> > 
> > In that case, you only need to write a user mode program to 
> > tunnel (forward) info from network <-> JTAG.
> > 
> > It will make the xmd, xst, etc on both windows and Unix 
> > platform much easier to develop, maintain and use.
> > 
> > TCP/UDP Socket programming is so much easier to develop nad
> > debug for all the platform.
> > 
> > Right now, I have to build xilinx_pp drivers for different
> > version of linux kernels.  
> > 
> > Does anyone have a patch for xilinx_pp driver for 2.6 kernel
> > (Redhat FC 3 release)?
> > 
> > 
> > -Tony
> 
> Or use Chameleon POD on www.amontec.com


I check the website.  I only find the replacment for parallel port cable.

The HW for ethernet cable is not hard.  The more difficult part to get 
the software (xmd, impact) working with the new cable.  

-Tony

Article: 75872
Subject: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
From: "Jim Wu" <nospam@nospam.com>
Date: Wed, 17 Nov 2004 17:44:15 -0500
Links: << >>  << T >>  << A >>
> Hi,
>
> Well, let me know if you figure this one out.  I had
> a similar issue -- I wanted a Verilog simulation to
> write out a TIFF file.  I couldn't find a way to write
> out a binary file, so wrote out ASCII data values to
> text file and then post-processed it into a binary
> TIFF file using a small program I wrote in C.

The attached code is kind of kludge, but it works, with modelsim 5.8e
anyway.

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips



module wr_bin ();

reg [7:0] data;

integer fd;
integer i;

initial begin
    fd = $fopen("test.bin", "wb");

    for (i = 0; i < 256; i = i + 1) begin
        data = i;

        if (data == 0) begin
            $fwriteb(fd, "%u", data);
            $fseek(fd, 1, 0);
        end
        else
            $fwriteb(fd, "%c", data);
    end

    $fclose(fd);
    $display("Done");
    $finish;
end

endmodule



Article: 75873
Subject: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
From: "Jim Wu" <nospam@nospam.com>
Date: Wed, 17 Nov 2004 17:44:15 -0500
Links: << >>  << T >>  << A >>
> Hi,
>
> Well, let me know if you figure this one out.  I had
> a similar issue -- I wanted a Verilog simulation to
> write out a TIFF file.  I couldn't find a way to write
> out a binary file, so wrote out ASCII data values to
> text file and then post-processed it into a binary
> TIFF file using a small program I wrote in C.

The attached code is kind of kludge, but it works, with modelsim 5.8e
anyway.

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips



module wr_bin ();

reg [7:0] data;

integer fd;
integer i;

initial begin
    fd = $fopen("test.bin", "wb");

    for (i = 0; i < 256; i = i + 1) begin
        data = i;

        if (data == 0) begin
            $fwriteb(fd, "%u", data);
            $fseek(fd, 1, 0);
        end
        else
            $fwriteb(fd, "%c", data);
    end

    $fclose(fd);
    $display("Done");
    $finish;
end

endmodule



Article: 75874
Subject: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Wed, 17 Nov 2004 15:10:25 -0800
Links: << >>  << T >>  << A >>

Dude, you rock!!!  Since I'm using Modelsim at home
for my hobby projects, this will work fantastic...
Now I can write out TIFF files direct from Verilog.

Let me ask another question, if you don't mind.  Do
you (or anyone reading) know if it's possible to
open files with dynamic file names?  By that, I
mean instead of using the string "test.bin" in $fopen
is there a way to form a string with a 2D reg and
then pass that as the file name?  I tried playing
around with this, but the simulator I was using at
the time did not like anything but actual strings...

My desire is to have a loop, that writes each display
frame to a separate file, with names like:

frame01.tif
frame02.tif
frame03.tif
frame04.tif
and so on...

Thanks, I appreciate your help,
Eric

Jim Wu wrote:
> 
> > Hi,
> >
> > Well, let me know if you figure this one out.  I had
> > a similar issue -- I wanted a Verilog simulation to
> > write out a TIFF file.  I couldn't find a way to write
> > out a binary file, so wrote out ASCII data values to
> > text file and then post-processed it into a binary
> > TIFF file using a small program I wrote in C.
> 
> The attached code is kind of kludge, but it works, with modelsim 5.8e
> anyway.
> 
> HTH,
> Jim
> jimwu88NOOOSPAM@yahoo.com (remove capital letters)
> http://www.geocities.com/jimwu88/chips
> 
> module wr_bin ();
> 
> reg [7:0] data;
> 
> integer fd;
> integer i;
> 
> initial begin
>     fd = $fopen("test.bin", "wb");
> 
>     for (i = 0; i < 256; i = i + 1) begin
>         data = i;
> 
>         if (data == 0) begin
>             $fwriteb(fd, "%u", data);
>             $fseek(fd, 1, 0);
>         end
>         else
>             $fwriteb(fd, "%c", data);
>     end
> 
>     $fclose(fd);
>     $display("Done");
>     $finish;
> end
> 
> endmodule



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